[X86] Improve F16C CVT schedules on SNB/HSW/BDW
[llvm-project.git] / llvm / docs / AMDGPU / gfx90a_vaddr_0212e3.rst
blob63daa4238313642ce051b19a21f262d311131501
1 ..
2     **************************************************
3     *                                                *
4     *   Automatically generated file, do not edit!   *
5     *                                                *
6     **************************************************
8 .. _amdgpu_synid_gfx90a_vaddr_0212e3:
10 vaddr
11 =====
13 A 64-bit flat global address or a 32-bit offset depending on addressing mode:
15 * Address = :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_0212e3>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid_gfx90a_saddr_a37373>` set to :ref:`off<amdgpu_synid_off>`.
16 * Address = :ref:`saddr<amdgpu_synid_gfx90a_saddr_a37373>` + :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_0212e3>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid_gfx90a_saddr_a37373>` is not :ref:`off<amdgpu_synid_off>`.
18 *Size:* 1 or 2 dwords.
20 *Operands:* :ref:`v<amdgpu_synid_v>`