llvm/lib/MCA/Context.cpp

   1 //===---------------------------- Context.cpp -------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 ///
  10 /// This file defines a class for holding ownership of various simulated
  11 /// hardware units.  A Context also provides a utility routine for constructing
  12 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
  13 /// stages.
  14 ///
  15 //===----------------------------------------------------------------------===//
  16
  17 #include "llvm/MCA/Context.h"
  18 #include "llvm/MCA/HardwareUnits/RegisterFile.h"
  19 #include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
  20 #include "llvm/MCA/HardwareUnits/Scheduler.h"
  21 #include "llvm/MCA/Stages/DispatchStage.h"
  22 #include "llvm/MCA/Stages/EntryStage.h"
  23 #include "llvm/MCA/Stages/ExecuteStage.h"
  24 #include "llvm/MCA/Stages/InOrderIssueStage.h"
  25 #include "llvm/MCA/Stages/MicroOpQueueStage.h"
  26 #include "llvm/MCA/Stages/RetireStage.h"
  27
  28 namespace llvm {
  29 namespace mca {
  30
  31 std::unique_ptr<Pipeline>
  32 Context::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr,
  33                                CustomBehaviour &CB) {
  34   const MCSchedModel &SM = STI.getSchedModel();
  35
  36   if (!SM.isOutOfOrder())
  37     return createInOrderPipeline(Opts, SrcMgr, CB);
  38
  39   // Create the hardware units defining the backend.
  40   auto RCU = std::make_unique<RetireControlUnit>(SM);
  41   auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
  42   auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
  43                                       Opts.StoreQueueSize, Opts.AssumeNoAlias);
  44   auto HWS = std::make_unique<Scheduler>(SM, *LSU);
  45
  46   // Create the pipeline stages.
  47   auto Fetch = std::make_unique<EntryStage>(SrcMgr);
  48   auto Dispatch =
  49       std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth, *RCU, *PRF);
  50   auto Execute =
  51       std::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis);
  52   auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU);
  53
  54   // Pass the ownership of all the hardware units to this Context.
  55   addHardwareUnit(std::move(RCU));
  56   addHardwareUnit(std::move(PRF));
  57   addHardwareUnit(std::move(LSU));
  58   addHardwareUnit(std::move(HWS));
  59
  60   // Build the pipeline.
  61   auto StagePipeline = std::make_unique<Pipeline>();
  62   StagePipeline->appendStage(std::move(Fetch));
  63   if (Opts.MicroOpQueueSize)
  64     StagePipeline->appendStage(std::make_unique<MicroOpQueueStage>(
  65         Opts.MicroOpQueueSize, Opts.DecodersThroughput));
  66   StagePipeline->appendStage(std::move(Dispatch));
  67   StagePipeline->appendStage(std::move(Execute));
  68   StagePipeline->appendStage(std::move(Retire));
  69   return StagePipeline;
  70 }
  71
  72 std::unique_ptr<Pipeline>
  73 Context::createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr,
  74                                CustomBehaviour &CB) {
  75   const MCSchedModel &SM = STI.getSchedModel();
  76   auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
  77   auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
  78                                       Opts.StoreQueueSize, Opts.AssumeNoAlias);
  79
  80   // Create the pipeline stages.
  81   auto Entry = std::make_unique<EntryStage>(SrcMgr);
  82   auto InOrderIssue = std::make_unique<InOrderIssueStage>(STI, *PRF, CB, *LSU);
  83   auto StagePipeline = std::make_unique<Pipeline>();
  84
  85   // Pass the ownership of all the hardware units to this Context.
  86   addHardwareUnit(std::move(PRF));
  87   addHardwareUnit(std::move(LSU));
  88
  89   // Build the pipeline.
  90   StagePipeline->appendStage(std::move(Entry));
  91   StagePipeline->appendStage(std::move(InOrderIssue));
  92   return StagePipeline;
  93 }
  94
  95 } // namespace mca
  96 } // namespace llvm