[Clang/AMDGPU] Zero sized arrays not allowed in HIP device code. (#113470)
[llvm-project.git] / llvm / lib / Target / AMDGPU / AMDGPUIGroupLP.h
blobaff7096f26d671b06e3d2997976c9ac5653bbeac
1 //===- AMDGPUMFMAIGroupLP.h - AMDGPU MFMA IGroupLP --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMFMAIGROUPLP_H
10 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMFMAIGROUPLP_H
12 #include "llvm/CodeGen/ScheduleDAGMutation.h"
13 #include <memory>
14 #include <vector>
16 namespace llvm {
18 namespace AMDGPU {
19 // The current phase of instruction scheduling
20 enum class SchedulingPhase { Initial, PreRAReentry, PostRA };
21 } // namespace AMDGPU
23 std::unique_ptr<ScheduleDAGMutation>
24 createIGroupLPDAGMutation(AMDGPU::SchedulingPhase Phase);
26 } // namespace llvm
28 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUMFMAIGROUPLP_H