llvm/lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces which we are implementing
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 include "ARMFeatures.td"
  19 include "ARMArchitectures.td"
  20
  21 //===----------------------------------------------------------------------===//
  22 // Register File Description
  23 //===----------------------------------------------------------------------===//
  24
  25 include "ARMRegisterInfo.td"
  26 include "ARMRegisterBanks.td"
  27 include "ARMCallingConv.td"
  28
  29 //===----------------------------------------------------------------------===//
  30 // ARM schedules.
  31 //===----------------------------------------------------------------------===//
  32 //
  33 include "ARMPredicates.td"
  34 include "ARMSchedule.td"
  35
  36 //===----------------------------------------------------------------------===//
  37 // Instruction Descriptions
  38 //===----------------------------------------------------------------------===//
  39
  40 include "ARMInstrInfo.td"
  41 def ARMInstrInfo : InstrInfo;
  42
  43 //===----------------------------------------------------------------------===//
  44 // ARM schedules
  45 //
  46 include "ARMScheduleV6.td"
  47 include "ARMScheduleA8.td"
  48 include "ARMScheduleA9.td"
  49 include "ARMScheduleSwift.td"
  50 include "ARMScheduleR52.td"
  51 include "ARMScheduleA57.td"
  52 include "ARMScheduleM4.td"
  53 include "ARMScheduleM55.td"
  54 include "ARMScheduleM7.td"
  55 include "ARMScheduleM85.td"
  56
  57 include "ARMProcessors.td"
  58
  59 //===----------------------------------------------------------------------===//
  60 // Declare the target which we are implementing
  61 //===----------------------------------------------------------------------===//
  62
  63 def ARMAsmWriter : AsmWriter {
  64   string AsmWriterClassName  = "InstPrinter";
  65   int PassSubtarget = 1;
  66   int Variant = 0;
  67   bit isMCAsmWriter = 1;
  68 }
  69
  70 def ARMAsmParser : AsmParser {
  71   bit ReportMultipleNearMisses = 1;
  72   let PreferSmallerInstructions = true;
  73 }
  74
  75 def ARMAsmParserVariant : AsmParserVariant {
  76   int Variant = 0;
  77   string Name = "ARM";
  78   string BreakCharacters = ".";
  79 }
  80
  81 def ARM : Target {
  82   // Pull in Instruction Info.
  83   let InstructionSet = ARMInstrInfo;
  84   let AssemblyWriters = [ARMAsmWriter];
  85   let AssemblyParsers = [ARMAsmParser];
  86   let AssemblyParserVariants = [ARMAsmParserVariant];
  87   let AllowRegisterRenaming = 1;
  88 }