1 //===-- ARMHazardRecognizer.h - ARM Hazard Recognizers ----------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines hazard recognizers for scheduling ARM functions.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_ARM_ARMHAZARDRECOGNIZER_H
14 #define LLVM_LIB_TARGET_ARM_ARMHAZARDRECOGNIZER_H
16 #include "ARMBaseInstrInfo.h"
17 #include "llvm/ADT/BitmaskEnum.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
20 #include "llvm/Support/DataTypes.h"
21 #include <initializer_list>
26 class MachineFunction
;
30 // Hazards related to FP MLx instructions
31 class ARMHazardRecognizerFPMLx
: public ScheduleHazardRecognizer
{
32 MachineInstr
*LastMI
= nullptr;
33 unsigned FpMLxStalls
= 0;
36 ARMHazardRecognizerFPMLx() { MaxLookAhead
= 1; }
38 HazardType
getHazardType(SUnit
*SU
, int Stalls
) override
;
39 void Reset() override
;
40 void EmitInstruction(SUnit
*SU
) override
;
41 void AdvanceCycle() override
;
42 void RecedeCycle() override
;
45 // Hazards related to bank conflicts
46 class ARMBankConflictHazardRecognizer
: public ScheduleHazardRecognizer
{
47 SmallVector
<MachineInstr
*, 8> Accesses
;
48 const MachineFunction
&MF
;
51 bool AssumeITCMBankConflict
;
54 ARMBankConflictHazardRecognizer(const ScheduleDAG
*DAG
, int64_t DDM
,
56 HazardType
getHazardType(SUnit
*SU
, int Stalls
) override
;
57 void Reset() override
;
58 void EmitInstruction(SUnit
*SU
) override
;
59 void AdvanceCycle() override
;
60 void RecedeCycle() override
;
63 inline HazardType
CheckOffsets(unsigned O0
, unsigned O1
);
66 } // end namespace llvm