llvm/lib/Target/ARM/ARMLatencyMutations.h

   1 //===- ARMLatencyMutations.h - ARM Latency Mutations ----------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file This file contains the ARM definition DAG scheduling mutations which
  10 /// change inter-instruction latencies
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_ARM_LATENCYMUTATIONS_H
  15 #define LLVM_LIB_TARGET_ARM_LATENCYMUTATIONS_H
  16
  17 #include "llvm/CodeGen/MachineScheduler.h"
  18 #include "llvm/CodeGen/ScheduleDAGMutation.h"
  19
  20 namespace llvm {
  21
  22 class AAResults;
  23 class ARMBaseInstrInfo;
  24
  25 /// Post-process the DAG to create cluster edges between instrs that may
  26 /// be fused by the processor into a single operation.
  27 class ARMOverrideBypasses : public ScheduleDAGMutation {
  28 public:
  29   ARMOverrideBypasses(const ARMBaseInstrInfo *t, AAResults *a)
  30       : ScheduleDAGMutation(), TII(t), AA(a) {}
  31
  32   void apply(ScheduleDAGInstrs *DAGInstrs) override;
  33
  34 private:
  35   virtual void modifyBypasses(SUnit &) = 0;
  36
  37 protected:
  38   const ARMBaseInstrInfo *TII;
  39   AAResults *AA;
  40   ScheduleDAGInstrs *DAG = nullptr;
  41
  42   static void setBidirLatencies(SUnit &SrcSU, SDep &SrcDep, unsigned latency);
  43   static bool zeroOutputDependences(SUnit &ISU, SDep &Dep);
  44   unsigned makeBundleAssumptions(SUnit &ISU, SDep &Dep);
  45   bool memoryRAWHazard(SUnit &ISU, SDep &Dep, unsigned latency);
  46 };
  47
  48 /// Note that you have to add:
  49 ///   DAG.addMutation(createARMLatencyMutation(ST, AA));
  50 /// to ARMPassConfig::createMachineScheduler() to have an effect.
  51 std::unique_ptr<ScheduleDAGMutation>
  52 createARMLatencyMutations(const class ARMSubtarget &, AAResults *AA);
  53
  54 } // namespace llvm
  55
  56 #endif