llvm/lib/Target/ARM/ARMMCInstLower.cpp

   1 //===-- ARMMCInstLower.cpp - Convert ARM MachineInstr to an MCInst --------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains code to lower ARM MachineInstrs to their corresponding
  10 // MCInst records.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "ARM.h"
  15 #include "ARMAsmPrinter.h"
  16 #include "ARMBaseInstrInfo.h"
  17 #include "ARMMachineFunctionInfo.h"
  18 #include "ARMSubtarget.h"
  19 #include "MCTargetDesc/ARMAddressingModes.h"
  20 #include "MCTargetDesc/ARMBaseInfo.h"
  21 #include "MCTargetDesc/ARMMCExpr.h"
  22 #include "llvm/ADT/APFloat.h"
  23 #include "llvm/CodeGen/MachineBasicBlock.h"
  24 #include "llvm/CodeGen/MachineInstr.h"
  25 #include "llvm/CodeGen/MachineOperand.h"
  26 #include "llvm/IR/Constants.h"
  27 #include "llvm/MC/MCContext.h"
  28 #include "llvm/MC/MCExpr.h"
  29 #include "llvm/MC/MCInst.h"
  30 #include "llvm/MC/MCInstBuilder.h"
  31 #include "llvm/MC/MCStreamer.h"
  32 #include "llvm/Support/ErrorHandling.h"
  33 #include <cassert>
  34 #include <cstdint>
  35
  36 using namespace llvm;
  37
  38 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
  39                                       const MCSymbol *Symbol) {
  40   MCSymbolRefExpr::VariantKind SymbolVariant = MCSymbolRefExpr::VK_None;
  41   if (MO.getTargetFlags() & ARMII::MO_SBREL)
  42     SymbolVariant = MCSymbolRefExpr::VK_ARM_SBREL;
  43
  44   const MCExpr *Expr =
  45       MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
  46   switch (MO.getTargetFlags() & ARMII::MO_OPTION_MASK) {
  47   default:
  48     llvm_unreachable("Unknown target flag on symbol operand");
  49   case ARMII::MO_NO_FLAG:
  50     break;
  51   case ARMII::MO_LO16:
  52     Expr =
  53         MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
  54     Expr = ARMMCExpr::createLower16(Expr, OutContext);
  55     break;
  56   case ARMII::MO_HI16:
  57     Expr =
  58         MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
  59     Expr = ARMMCExpr::createUpper16(Expr, OutContext);
  60     break;
  61   case ARMII::MO_LO_0_7:
  62     Expr = MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
  63     Expr = ARMMCExpr::createLower0_7(Expr, OutContext);
  64     break;
  65   case ARMII::MO_LO_8_15:
  66     Expr = MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
  67     Expr = ARMMCExpr::createLower8_15(Expr, OutContext);
  68     break;
  69   case ARMII::MO_HI_0_7:
  70     Expr = MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
  71     Expr = ARMMCExpr::createUpper0_7(Expr, OutContext);
  72     break;
  73   case ARMII::MO_HI_8_15:
  74     Expr = MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
  75     Expr = ARMMCExpr::createUpper8_15(Expr, OutContext);
  76     break;
  77   }
  78
  79   if (!MO.isJTI() && MO.getOffset())
  80     Expr = MCBinaryExpr::createAdd(Expr,
  81                                    MCConstantExpr::create(MO.getOffset(),
  82                                                           OutContext),
  83                                    OutContext);
  84   return MCOperand::createExpr(Expr);
  85
  86 }
  87
  88 bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
  89                                  MCOperand &MCOp) {
  90   switch (MO.getType()) {
  91   default: llvm_unreachable("unknown operand type");
  92   case MachineOperand::MO_Register:
  93     // Ignore all implicit register operands.
  94     if (MO.isImplicit())
  95       return false;
  96     assert(!MO.getSubReg() && "Subregs should be eliminated!");
  97     MCOp = MCOperand::createReg(MO.getReg());
  98     break;
  99   case MachineOperand::MO_Immediate:
 100     MCOp = MCOperand::createImm(MO.getImm());
 101     break;
 102   case MachineOperand::MO_MachineBasicBlock:
 103     MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(
 104         MO.getMBB()->getSymbol(), OutContext));
 105     break;
 106   case MachineOperand::MO_GlobalAddress:
 107     MCOp = GetSymbolRef(MO,
 108                         GetARMGVSymbol(MO.getGlobal(), MO.getTargetFlags()));
 109     break;
 110   case MachineOperand::MO_ExternalSymbol:
 111     MCOp = GetSymbolRef(MO,
 112                         GetExternalSymbolSymbol(MO.getSymbolName()));
 113     break;
 114   case MachineOperand::MO_JumpTableIndex:
 115     MCOp = GetSymbolRef(MO, GetJTISymbol(MO.getIndex()));
 116     break;
 117   case MachineOperand::MO_ConstantPoolIndex:
 118     if (Subtarget->genExecuteOnly())
 119       llvm_unreachable("execute-only should not generate constant pools");
 120     MCOp = GetSymbolRef(MO, GetCPISymbol(MO.getIndex()));
 121     break;
 122   case MachineOperand::MO_BlockAddress:
 123     MCOp = GetSymbolRef(MO, GetBlockAddressSymbol(MO.getBlockAddress()));
 124     break;
 125   case MachineOperand::MO_FPImmediate: {
 126     APFloat Val = MO.getFPImm()->getValueAPF();
 127     bool ignored;
 128     Val.convert(APFloat::IEEEdouble(), APFloat::rmTowardZero, &ignored);
 129     MCOp = MCOperand::createDFPImm(bit_cast<uint64_t>(Val.convertToDouble()));
 130     break;
 131   }
 132   case MachineOperand::MO_RegisterMask:
 133     // Ignore call clobbers.
 134     return false;
 135   }
 136   return true;
 137 }
 138
 139 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
 140                                         ARMAsmPrinter &AP) {
 141   OutMI.setOpcode(MI->getOpcode());
 142
 143   // In the MC layer, we keep modified immediates in their encoded form
 144   bool EncodeImms = false;
 145   switch (MI->getOpcode()) {
 146   default: break;
 147   case ARM::MOVi:
 148   case ARM::MVNi:
 149   case ARM::CMPri:
 150   case ARM::CMNri:
 151   case ARM::TSTri:
 152   case ARM::TEQri:
 153   case ARM::MSRi:
 154   case ARM::ADCri:
 155   case ARM::ADDri:
 156   case ARM::ADDSri:
 157   case ARM::SBCri:
 158   case ARM::SUBri:
 159   case ARM::SUBSri:
 160   case ARM::ANDri:
 161   case ARM::ORRri:
 162   case ARM::EORri:
 163   case ARM::BICri:
 164   case ARM::RSBri:
 165   case ARM::RSBSri:
 166   case ARM::RSCri:
 167     EncodeImms = true;
 168     break;
 169   }
 170
 171   for (const MachineOperand &MO : MI->operands()) {
 172     MCOperand MCOp;
 173     if (AP.lowerOperand(MO, MCOp)) {
 174       if (MCOp.isImm() && EncodeImms) {
 175         int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm());
 176         if (Enc != -1)
 177           MCOp.setImm(Enc);
 178       }
 179       OutMI.addOperand(MCOp);
 180     }
 181   }
 182 }
 183
 184 void ARMAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
 185 {
 186   const MachineFunction *MF = MI.getParent()->getParent();
 187   if (MF->getInfo<ARMFunctionInfo>()->isThumbFunction()) {
 188     const Function &Fn = MF->getFunction();
 189     DiagnosticInfoUnsupported Unsupported(
 190         Fn,
 191         "An attempt to perform XRay instrumentation for a"
 192         " Thumb function (not supported). Detected when emitting a sled.",
 193         MI.getDebugLoc());
 194     Fn.getContext().diagnose(Unsupported);
 195     return;
 196   }
 197   static const int8_t NoopsInSledCount = 6;
 198   // We want to emit the following pattern:
 199   //
 200   // .Lxray_sled_N:
 201   //   ALIGN
 202   //   B #20
 203   //   ; 6 NOP instructions (24 bytes)
 204   // .tmpN
 205   //
 206   // We need the 24 bytes (6 instructions) because at runtime, we'd be patching
 207   // over the full 28 bytes (7 instructions) with the following pattern:
 208   //
 209   //   PUSH{ r0, lr }
 210   //   MOVW r0, #<lower 16 bits of function ID>
 211   //   MOVT r0, #<higher 16 bits of function ID>
 212   //   MOVW ip, #<lower 16 bits of address of __xray_FunctionEntry/Exit>
 213   //   MOVT ip, #<higher 16 bits of address of __xray_FunctionEntry/Exit>
 214   //   BLX ip
 215   //   POP{ r0, lr }
 216   //
 217   OutStreamer->emitCodeAlignment(Align(4), &getSubtargetInfo());
 218   auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
 219   OutStreamer->emitLabel(CurSled);
 220   auto Target = OutContext.createTempSymbol();
 221
 222   // Emit "B #20" instruction, which jumps over the next 24 bytes (because
 223   // register pc is 8 bytes ahead of the jump instruction by the moment CPU
 224   // is executing it).
 225   // By analogy to ARMAsmPrinter::lowerPseudoInstExpansion() |case ARM::B|.
 226   // It is not clear why |addReg(0)| is needed (the last operand).
 227   EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc).addImm(20)
 228     .addImm(ARMCC::AL).addReg(0));
 229
 230   emitNops(NoopsInSledCount);
 231
 232   OutStreamer->emitLabel(Target);
 233   recordSled(CurSled, MI, Kind, 2);
 234 }
 235
 236 void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
 237 {
 238   EmitSled(MI, SledKind::FUNCTION_ENTER);
 239 }
 240
 241 void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
 242 {
 243   EmitSled(MI, SledKind::FUNCTION_EXIT);
 244 }
 245
 246 void ARMAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
 247 {
 248   EmitSled(MI, SledKind::TAIL_CALL);
 249 }