llvm/lib/Target/ARM/ARMSelectionDAGInfo.h

   1 //===-- ARMSelectionDAGInfo.h - ARM SelectionDAG Info -----------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the ARM subclass for SelectionDAGTargetInfo.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_ARM_ARMSELECTIONDAGINFO_H
  14 #define LLVM_LIB_TARGET_ARM_ARMSELECTIONDAGINFO_H
  15
  16 #include "MCTargetDesc/ARMAddressingModes.h"
  17 #include "llvm/CodeGen/RuntimeLibcallUtil.h"
  18 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
  19
  20 namespace llvm {
  21
  22 namespace ARM_AM {
  23   static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) {
  24     switch (Opcode) {
  25     default:          return ARM_AM::no_shift;
  26     case ISD::SHL:    return ARM_AM::lsl;
  27     case ISD::SRL:    return ARM_AM::lsr;
  28     case ISD::SRA:    return ARM_AM::asr;
  29     case ISD::ROTR:   return ARM_AM::ror;
  30     //case ISD::ROTL:  // Only if imm -> turn into ROTR.
  31     // Can't handle RRX here, because it would require folding a flag into
  32     // the addressing mode.  :(  This causes us to miss certain things.
  33     //case ARMISD::RRX: return ARM_AM::rrx;
  34     }
  35   }
  36 }  // end namespace ARM_AM
  37
  38 class ARMSelectionDAGInfo : public SelectionDAGTargetInfo {
  39 public:
  40   bool isTargetMemoryOpcode(unsigned Opcode) const override;
  41
  42   SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
  43                                   SDValue Chain, SDValue Dst, SDValue Src,
  44                                   SDValue Size, Align Alignment,
  45                                   bool isVolatile, bool AlwaysInline,
  46                                   MachinePointerInfo DstPtrInfo,
  47                                   MachinePointerInfo SrcPtrInfo) const override;
  48
  49   SDValue
  50   EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
  51                            SDValue Dst, SDValue Src, SDValue Size,
  52                            Align Alignment, bool isVolatile,
  53                            MachinePointerInfo DstPtrInfo,
  54                            MachinePointerInfo SrcPtrInfo) const override;
  55
  56   // Adjust parameters for memset, see RTABI section 4.3.4
  57   SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl,
  58                                   SDValue Chain, SDValue Op1, SDValue Op2,
  59                                   SDValue Op3, Align Alignment, bool isVolatile,
  60                                   bool AlwaysInline,
  61                                   MachinePointerInfo DstPtrInfo) const override;
  62
  63   SDValue EmitSpecializedLibcall(SelectionDAG &DAG, const SDLoc &dl,
  64                                  SDValue Chain, SDValue Dst, SDValue Src,
  65                                  SDValue Size, unsigned Align,
  66                                  RTLIB::Libcall LC) const;
  67 };
  68
  69 }
  70
  71 #endif