llvm/lib/Target/ARM/ARMTargetMachine.h

   1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file declares the ARM specific subclass of TargetMachine.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
  14 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
  15
  16 #include "ARMSubtarget.h"
  17 #include "llvm/ADT/StringMap.h"
  18 #include "llvm/ADT/StringRef.h"
  19 #include "llvm/Analysis/TargetTransformInfo.h"
  20 #include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
  21 #include "llvm/Support/CodeGen.h"
  22 #include "llvm/Target/TargetMachine.h"
  23 #include <memory>
  24 #include <optional>
  25
  26 namespace llvm {
  27
  28 class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {
  29 public:
  30   enum ARMABI {
  31     ARM_ABI_UNKNOWN,
  32     ARM_ABI_APCS,
  33     ARM_ABI_AAPCS, // ARM EABI
  34     ARM_ABI_AAPCS16
  35   } TargetABI;
  36
  37 protected:
  38   std::unique_ptr<TargetLoweringObjectFile> TLOF;
  39   bool isLittle;
  40   mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
  41
  42   /// Reset internal state.
  43   void reset() override;
  44
  45 public:
  46   ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
  47                        StringRef FS, const TargetOptions &Options,
  48                        std::optional<Reloc::Model> RM,
  49                        std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
  50                        bool isLittle);
  51   ~ARMBaseTargetMachine() override;
  52
  53   const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
  54   // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
  55   // subtargets are per-function entities based on the target-specific
  56   // attributes of each function.
  57   const ARMSubtarget *getSubtargetImpl() const = delete;
  58   bool isLittleEndian() const { return isLittle; }
  59
  60   TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
  61
  62   // Pass Pipeline Configuration
  63   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
  64
  65   TargetLoweringObjectFile *getObjFileLowering() const override {
  66     return TLOF.get();
  67   }
  68
  69   bool isTargetHardFloat() const {
  70     return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
  71            TargetTriple.getEnvironment() == Triple::GNUEABIHFT64 ||
  72            TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
  73            TargetTriple.getEnvironment() == Triple::EABIHF ||
  74            (TargetTriple.isOSBinFormatMachO() &&
  75             TargetTriple.getSubArch() == Triple::ARMSubArch_v7em) ||
  76            TargetTriple.isOSWindows() ||
  77            TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
  78   }
  79
  80   bool targetSchedulesPostRAScheduling() const override { return true; };
  81
  82   MachineFunctionInfo *
  83   createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
  84                             const TargetSubtargetInfo *STI) const override;
  85
  86   /// Returns true if a cast between SrcAS and DestAS is a noop.
  87   bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
  88     // Addrspacecasts are always noops.
  89     return true;
  90   }
  91
  92   yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
  93   yaml::MachineFunctionInfo *
  94   convertFuncInfoToYAML(const MachineFunction &MF) const override;
  95   bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
  96                                 PerFunctionMIParsingState &PFS,
  97                                 SMDiagnostic &Error,
  98                                 SMRange &SourceRange) const override;
  99 };
 100
 101 /// ARM/Thumb little endian target machine.
 102 ///
 103 class ARMLETargetMachine : public ARMBaseTargetMachine {
 104 public:
 105   ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
 106                      StringRef FS, const TargetOptions &Options,
 107                      std::optional<Reloc::Model> RM,
 108                      std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
 109                      bool JIT);
 110 };
 111
 112 /// ARM/Thumb big endian target machine.
 113 ///
 114 class ARMBETargetMachine : public ARMBaseTargetMachine {
 115 public:
 116   ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
 117                      StringRef FS, const TargetOptions &Options,
 118                      std::optional<Reloc::Model> RM,
 119                      std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
 120                      bool JIT);
 121 };
 122
 123 } // end namespace llvm
 124
 125 #endif // LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H