llvm/lib/Target/ARM/Thumb2InstrInfo.h

   1 //===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
  14 #define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
  15
  16 #include "ARMBaseInstrInfo.h"
  17 #include "ThumbRegisterInfo.h"
  18
  19 namespace llvm {
  20 class ARMSubtarget;
  21
  22 class Thumb2InstrInfo : public ARMBaseInstrInfo {
  23   ThumbRegisterInfo RI;
  24 public:
  25   explicit Thumb2InstrInfo(const ARMSubtarget &STI);
  26
  27   /// Return the noop instruction to use for a noop.
  28   MCInst getNop() const override;
  29
  30   // Return the non-pre/post incrementing version of 'Opc'. Return 0
  31   // if there is not such an opcode.
  32   unsigned getUnindexedOpcode(unsigned Opc) const override;
  33
  34   void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
  35                                MachineBasicBlock *NewDest) const override;
  36
  37   bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
  38                            MachineBasicBlock::iterator MBBI) const override;
  39
  40   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
  41                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
  42                    bool KillSrc, bool RenamableDest = false,
  43                    bool RenamableSrc = false) const override;
  44
  45   void storeRegToStackSlot(MachineBasicBlock &MBB,
  46                            MachineBasicBlock::iterator MBBI, Register SrcReg,
  47                            bool isKill, int FrameIndex,
  48                            const TargetRegisterClass *RC,
  49                            const TargetRegisterInfo *TRI,
  50                            Register VReg) const override;
  51
  52   void loadRegFromStackSlot(MachineBasicBlock &MBB,
  53                             MachineBasicBlock::iterator MBBI, Register DestReg,
  54                             int FrameIndex, const TargetRegisterClass *RC,
  55                             const TargetRegisterInfo *TRI,
  56                             Register VReg) const override;
  57
  58   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  59   /// such, whenever a client has an instance of instruction info, it should
  60   /// always be able to get register info as well (through this method).
  61   ///
  62   const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
  63
  64   MachineInstr *optimizeSelect(MachineInstr &MI,
  65                                SmallPtrSetImpl<MachineInstr *> &SeenMIs,
  66                                bool) const override;
  67
  68   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
  69                                        unsigned OpIdx1,
  70                                        unsigned OpIdx2) const override;
  71
  72   bool isSchedulingBoundary(const MachineInstr &MI,
  73                             const MachineBasicBlock *MBB,
  74                             const MachineFunction &MF) const override;
  75
  76 private:
  77   void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
  78 };
  79
  80 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
  81 /// to llvm::getInstrPredicate except it returns AL for conditional branch
  82 /// instructions which are "predicated", but are not in IT blocks.
  83 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);
  84
  85 // getVPTInstrPredicate: VPT analogue of that, plus a helper function
  86 // corresponding to MachineInstr::findFirstPredOperandIdx.
  87 int findFirstVPTPredOperandIdx(const MachineInstr &MI);
  88 ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI,
  89                                       Register &PredReg);
  90 inline ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI) {
  91   Register PredReg;
  92   return getVPTInstrPredicate(MI, PredReg);
  93 }
  94
  95 // Recomputes the Block Mask of Instr, a VPT or VPST instruction.
  96 // This rebuilds the block mask of the instruction depending on the predicates
  97 // of the instructions following it. This should only be used after the
  98 // MVEVPTBlockInsertion pass has run, and should be used whenever a predicated
  99 // instruction is added to/removed from the block.
 100 void recomputeVPTBlockMask(MachineInstr &Instr);
 101 } // namespace llvm
 102
 103 #endif