llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp

   1 //===-- AVRMCCodeEmitter.cpp - Convert AVR Code to Machine Code -----------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the AVRMCCodeEmitter class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "AVRMCCodeEmitter.h"
  14
  15 #include "MCTargetDesc/AVRMCExpr.h"
  16 #include "MCTargetDesc/AVRMCTargetDesc.h"
  17
  18 #include "llvm/ADT/APFloat.h"
  19 #include "llvm/ADT/SmallVector.h"
  20 #include "llvm/MC/MCContext.h"
  21 #include "llvm/MC/MCExpr.h"
  22 #include "llvm/MC/MCFixup.h"
  23 #include "llvm/MC/MCInst.h"
  24 #include "llvm/MC/MCInstrInfo.h"
  25 #include "llvm/MC/MCRegisterInfo.h"
  26 #include "llvm/MC/MCSubtargetInfo.h"
  27 #include "llvm/Support/Casting.h"
  28 #include "llvm/Support/EndianStream.h"
  29
  30 #define DEBUG_TYPE "mccodeemitter"
  31
  32 #define GET_INSTRMAP_INFO
  33 #include "AVRGenInstrInfo.inc"
  34 #undef GET_INSTRMAP_INFO
  35
  36 namespace llvm {
  37
  38 /// Performs a post-encoding step on a `LD` or `ST` instruction.
  39 ///
  40 /// The encoding of the LD/ST family of instructions is inconsistent w.r.t
  41 /// the pointer register and the addressing mode.
  42 ///
  43 /// The permutations of the format are as followed:
  44 /// ld Rd, X    `1001 000d dddd 1100`
  45 /// ld Rd, X+   `1001 000d dddd 1101`
  46 /// ld Rd, -X   `1001 000d dddd 1110`
  47 ///
  48 /// ld Rd, Y    `1000 000d dddd 1000`
  49 /// ld Rd, Y+   `1001 000d dddd 1001`
  50 /// ld Rd, -Y   `1001 000d dddd 1010`
  51 ///
  52 /// ld Rd, Z    `1000 000d dddd 0000`
  53 /// ld Rd, Z+   `1001 000d dddd 0001`
  54 /// ld Rd, -Z   `1001 000d dddd 0010`
  55 ///                 ^
  56 ///                 |
  57 /// Note this one inconsistent bit - it is 1 sometimes and 0 at other times.
  58 /// There is no logical pattern. Looking at a truth table, the following
  59 /// formula can be derived to fit the pattern:
  60 //
  61 /// ```
  62 /// inconsistent_bit = is_predec OR is_postinc OR is_reg_x
  63 /// ```
  64 //
  65 /// We manually set this bit in this post encoder method.
  66 unsigned
  67 AVRMCCodeEmitter::loadStorePostEncoder(const MCInst &MI, unsigned EncodedValue,
  68                                        const MCSubtargetInfo &STI) const {
  69
  70   assert(MI.getOperand(0).isReg() && MI.getOperand(1).isReg() &&
  71          "the load/store operands must be registers");
  72
  73   unsigned Opcode = MI.getOpcode();
  74
  75   // Get the index of the pointer register operand.
  76   unsigned Idx = 0;
  77   if (Opcode == AVR::LDRdPtrPd || Opcode == AVR::LDRdPtrPi ||
  78       Opcode == AVR::LDRdPtr)
  79     Idx = 1;
  80
  81   // Check if we need to set the inconsistent bit
  82   bool IsPredec = Opcode == AVR::LDRdPtrPd || Opcode == AVR::STPtrPdRr;
  83   bool IsPostinc = Opcode == AVR::LDRdPtrPi || Opcode == AVR::STPtrPiRr;
  84   if (MI.getOperand(Idx).getReg() == AVR::R27R26 || IsPredec || IsPostinc)
  85     EncodedValue |= (1 << 12);
  86
  87   // Encode the pointer register.
  88   switch (MI.getOperand(Idx).getReg()) {
  89   case AVR::R27R26:
  90     EncodedValue |= 0xc;
  91     break;
  92   case AVR::R29R28:
  93     EncodedValue |= 0x8;
  94     break;
  95   case AVR::R31R30:
  96     break;
  97   default:
  98     llvm_unreachable("invalid pointer register");
  99     break;
 100   }
 101
 102   return EncodedValue;
 103 }
 104
 105 template <AVR::Fixups Fixup>
 106 unsigned
 107 AVRMCCodeEmitter::encodeRelCondBrTarget(const MCInst &MI, unsigned OpNo,
 108                                         SmallVectorImpl<MCFixup> &Fixups,
 109                                         const MCSubtargetInfo &STI) const {
 110   const MCOperand &MO = MI.getOperand(OpNo);
 111
 112   if (MO.isExpr()) {
 113     Fixups.push_back(
 114         MCFixup::create(0, MO.getExpr(), MCFixupKind(Fixup), MI.getLoc()));
 115     return 0;
 116   }
 117
 118   assert(MO.isImm());
 119
 120   // Take the size of the current instruction away.
 121   // With labels, this is implicitly done.
 122   auto target = MO.getImm();
 123   AVR::fixups::adjustBranchTarget(target);
 124   return target;
 125 }
 126
 127 /// Encodes a `memri` operand.
 128 /// The operand is 7-bits.
 129 /// * The lower 6 bits is the immediate
 130 /// * The upper bit is the pointer register bit (Z=0,Y=1)
 131 unsigned AVRMCCodeEmitter::encodeMemri(const MCInst &MI, unsigned OpNo,
 132                                        SmallVectorImpl<MCFixup> &Fixups,
 133                                        const MCSubtargetInfo &STI) const {
 134   auto RegOp = MI.getOperand(OpNo);
 135   auto OffsetOp = MI.getOperand(OpNo + 1);
 136
 137   assert(RegOp.isReg() && "Expected register operand");
 138
 139   uint8_t RegBit = 0;
 140
 141   switch (RegOp.getReg().id()) {
 142   default:
 143     Ctx.reportError(MI.getLoc(), "Expected either Y or Z register");
 144     return 0;
 145   case AVR::R31R30:
 146     RegBit = 0;
 147     break; // Z register
 148   case AVR::R29R28:
 149     RegBit = 1;
 150     break; // Y register
 151   }
 152
 153   int8_t OffsetBits;
 154
 155   if (OffsetOp.isImm()) {
 156     OffsetBits = OffsetOp.getImm();
 157   } else if (OffsetOp.isExpr()) {
 158     OffsetBits = 0;
 159     Fixups.push_back(MCFixup::create(0, OffsetOp.getExpr(),
 160                                      MCFixupKind(AVR::fixup_6), MI.getLoc()));
 161   } else {
 162     llvm_unreachable("Invalid value for offset");
 163   }
 164
 165   return (RegBit << 6) | OffsetBits;
 166 }
 167
 168 unsigned AVRMCCodeEmitter::encodeComplement(const MCInst &MI, unsigned OpNo,
 169                                             SmallVectorImpl<MCFixup> &Fixups,
 170                                             const MCSubtargetInfo &STI) const {
 171   // The operand should be an immediate.
 172   assert(MI.getOperand(OpNo).isImm());
 173
 174   auto Imm = MI.getOperand(OpNo).getImm();
 175   return (~0) - Imm;
 176 }
 177
 178 template <AVR::Fixups Fixup, unsigned Offset>
 179 unsigned AVRMCCodeEmitter::encodeImm(const MCInst &MI, unsigned OpNo,
 180                                      SmallVectorImpl<MCFixup> &Fixups,
 181                                      const MCSubtargetInfo &STI) const {
 182   auto MO = MI.getOperand(OpNo);
 183
 184   if (MO.isExpr()) {
 185     if (isa<AVRMCExpr>(MO.getExpr())) {
 186       // If the expression is already an AVRMCExpr (i.e. a lo8(symbol),
 187       // we shouldn't perform any more fixups. Without this check, we would
 188       // instead create a fixup to the symbol named 'lo8(symbol)' which
 189       // is not correct.
 190       return getExprOpValue(MO.getExpr(), Fixups, STI);
 191     }
 192
 193     MCFixupKind FixupKind = static_cast<MCFixupKind>(Fixup);
 194     Fixups.push_back(
 195         MCFixup::create(Offset, MO.getExpr(), FixupKind, MI.getLoc()));
 196
 197     return 0;
 198   }
 199
 200   assert(MO.isImm());
 201   return MO.getImm();
 202 }
 203
 204 unsigned AVRMCCodeEmitter::encodeCallTarget(const MCInst &MI, unsigned OpNo,
 205                                             SmallVectorImpl<MCFixup> &Fixups,
 206                                             const MCSubtargetInfo &STI) const {
 207   auto MO = MI.getOperand(OpNo);
 208
 209   if (MO.isExpr()) {
 210     MCFixupKind FixupKind = static_cast<MCFixupKind>(AVR::fixup_call);
 211     Fixups.push_back(MCFixup::create(0, MO.getExpr(), FixupKind, MI.getLoc()));
 212     return 0;
 213   }
 214
 215   assert(MO.isImm());
 216
 217   auto Target = MO.getImm();
 218   AVR::fixups::adjustBranchTarget(Target);
 219   return Target;
 220 }
 221
 222 unsigned AVRMCCodeEmitter::getExprOpValue(const MCExpr *Expr,
 223                                           SmallVectorImpl<MCFixup> &Fixups,
 224                                           const MCSubtargetInfo &STI) const {
 225
 226   MCExpr::ExprKind Kind = Expr->getKind();
 227
 228   if (Kind == MCExpr::Binary) {
 229     Expr = static_cast<const MCBinaryExpr *>(Expr)->getLHS();
 230     Kind = Expr->getKind();
 231   }
 232
 233   if (Kind == MCExpr::Target) {
 234     AVRMCExpr const *AVRExpr = cast<AVRMCExpr>(Expr);
 235     int64_t Result;
 236     if (AVRExpr->evaluateAsConstant(Result)) {
 237       return Result;
 238     }
 239
 240     MCFixupKind FixupKind = static_cast<MCFixupKind>(AVRExpr->getFixupKind());
 241     Fixups.push_back(MCFixup::create(0, AVRExpr, FixupKind));
 242     return 0;
 243   }
 244
 245   assert(Kind == MCExpr::SymbolRef);
 246   return 0;
 247 }
 248
 249 unsigned AVRMCCodeEmitter::getMachineOpValue(const MCInst &MI,
 250                                              const MCOperand &MO,
 251                                              SmallVectorImpl<MCFixup> &Fixups,
 252                                              const MCSubtargetInfo &STI) const {
 253   if (MO.isReg())
 254     return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
 255   if (MO.isImm())
 256     return static_cast<unsigned>(MO.getImm());
 257
 258   if (MO.isDFPImm())
 259     return static_cast<unsigned>(bit_cast<double>(MO.getDFPImm()));
 260
 261   // MO must be an Expr.
 262   assert(MO.isExpr());
 263
 264   return getExprOpValue(MO.getExpr(), Fixups, STI);
 265 }
 266
 267 void AVRMCCodeEmitter::encodeInstruction(const MCInst &MI,
 268                                          SmallVectorImpl<char> &CB,
 269                                          SmallVectorImpl<MCFixup> &Fixups,
 270                                          const MCSubtargetInfo &STI) const {
 271   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
 272
 273   // Get byte count of instruction
 274   unsigned Size = Desc.getSize();
 275
 276   assert(Size > 0 && "Instruction size cannot be zero");
 277
 278   uint64_t BinaryOpCode = getBinaryCodeForInstr(MI, Fixups, STI);
 279
 280   for (int64_t i = Size / 2 - 1; i >= 0; --i) {
 281     uint16_t Word = (BinaryOpCode >> (i * 16)) & 0xFFFF;
 282     support::endian::write(CB, Word, llvm::endianness::little);
 283   }
 284 }
 285
 286 MCCodeEmitter *createAVRMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx) {
 287   return new AVRMCCodeEmitter(MCII, Ctx);
 288 }
 289
 290 #include "AVRGenMCCodeEmitter.inc"
 291
 292 } // end of namespace llvm