llvm/lib/Target/Hexagon/Hexagon.td

   1 //===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This is the top level entry point for the Hexagon target.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // Hexagon Subtarget features.
  21 //===----------------------------------------------------------------------===//
  22
  23 // Hexagon Architectures
  24 include "HexagonDepArch.td"
  25
  26 def ProcTinyCore: SubtargetFeature<"tinycore", "HexagonProcFamily",
  27       "TinyCore", "Hexagon Tiny Core">;
  28
  29 // Hexagon ISA Extensions
  30 def ExtensionZReg: SubtargetFeature<"zreg", "UseZRegOps", "true",
  31       "Hexagon ZReg extension instructions">;
  32 def ExtensionHVXQFloat: SubtargetFeature<"hvx-qfloat", "UseHVXQFloatOps",
  33       "true", "Hexagon HVX QFloating point instructions">;
  34
  35 def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion",
  36       "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
  37 def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion",
  38       "Hexagon::ArchEnum::V60", "Hexagon HVX instructions",
  39       [ExtensionHVX]>;
  40 def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion",
  41       "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
  42       [ExtensionHVX, ExtensionHVXV60]>;
  43 def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion",
  44       "Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
  45       [ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62]>;
  46 def ExtensionHVXV66: SubtargetFeature<"hvxv66", "HexagonHVXVersion",
  47       "Hexagon::ArchEnum::V66", "Hexagon HVX instructions",
  48       [ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
  49        ExtensionZReg]>;
  50 def ExtensionHVXV67: SubtargetFeature<"hvxv67", "HexagonHVXVersion",
  51       "Hexagon::ArchEnum::V67", "Hexagon HVX instructions",
  52       [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66]>;
  53 def ExtensionHVXV68: SubtargetFeature<"hvxv68", "HexagonHVXVersion",
  54       "Hexagon::ArchEnum::V68", "Hexagon HVX instructions",
  55       [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
  56        ExtensionHVXV67]>;
  57 def ExtensionHVXV69: SubtargetFeature<"hvxv69", "HexagonHVXVersion",
  58       "Hexagon::ArchEnum::V69", "Hexagon HVX instructions",
  59       [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
  60        ExtensionHVXV67, ExtensionHVXV68]>;
  61 def ExtensionHVXV71: SubtargetFeature<"hvxv71", "HexagonHVXVersion",
  62       "Hexagon::ArchEnum::V71", "Hexagon HVX instructions",
  63       [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
  64        ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69]>;
  65 def ExtensionHVXV73: SubtargetFeature<"hvxv73", "HexagonHVXVersion",
  66       "Hexagon::ArchEnum::V73", "Hexagon HVX instructions",
  67       [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
  68        ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71]>;
  69
  70 def ExtensionHVXV75: SubtargetFeature<"hvxv75", "HexagonHVXVersion",
  71       "Hexagon::ArchEnum::V75", "Hexagon HVX instructions",
  72       [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
  73        ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71,
  74        ExtensionHVXV73]>;
  75
  76 def ExtensionHVXV79: SubtargetFeature<"hvxv79", "HexagonHVXVersion",
  77       "Hexagon::ArchEnum::V79", "Hexagon HVX instructions",
  78       [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
  79        ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71,
  80        ExtensionHVXV73, ExtensionHVXV75]>;
  81
  82 def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",
  83       "true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;
  84 def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps",
  85       "true", "Hexagon HVX 128B instructions", [ExtensionHVX]>;
  86
  87 def ExtensionAudio: SubtargetFeature<"audio", "UseAudioOps", "true",
  88       "Hexagon Audio extension instructions">;
  89
  90 def ExtensionHVXIEEEFP: SubtargetFeature<"hvx-ieee-fp", "UseHVXIEEEFPOps",
  91       "true", "Hexagon HVX IEEE floating point instructions">;
  92
  93 def FeatureCompound: SubtargetFeature<"compound", "UseCompound", "true",
  94       "Use compound instructions">;
  95 def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true",
  96       "Support for instruction packets">;
  97 def FeaturePreV65: SubtargetFeature<"prev65", "HasPreV65", "true",
  98       "Support features deprecated in v65">;
  99 def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
 100       "Use constant-extended calls">;
 101 def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false",
 102       "Supports mem_noshuf feature">;
 103 def FeatureMemops: SubtargetFeature<"memops", "UseMemops", "true",
 104       "Use memop instructions">;
 105 def FeatureNVJ: SubtargetFeature<"nvj", "UseNewValueJumps", "true",
 106       "Support for new-value jumps", [FeaturePackets]>;
 107 def FeatureNVS: SubtargetFeature<"nvs", "UseNewValueStores", "true",
 108       "Support for new-value stores", [FeaturePackets]>;
 109 def FeatureSmallData: SubtargetFeature<"small-data", "UseSmallData", "true",
 110       "Allow GP-relative addressing of global variables">;
 111 def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true",
 112       "Enable generation of duplex instruction">;
 113 def FeatureUnsafeFP: SubtargetFeature<"unsafe-fp", "UseUnsafeMath", "true",
 114       "Use unsafe FP math">;
 115 def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19",
 116       "true", "Reserve register R19">;
 117 def FeatureNoreturnStackElim: SubtargetFeature<"noreturn-stack-elim",
 118       "NoreturnStackElim", "true",
 119       "Eliminate stack allocation in a noreturn function when possible">;
 120 def FeatureCabac: SubtargetFeature<"cabac", "UseCabac", "false",
 121       "Emit the CABAC instruction">;
 122
 123 //===----------------------------------------------------------------------===//
 124 // Hexagon Instruction Predicate Definitions.
 125 //===----------------------------------------------------------------------===//
 126
 127 def UseMEMOPS          : Predicate<"HST->useMemops()">;
 128 def UseHVX64B          : Predicate<"HST->useHVX64BOps()">,
 129                          AssemblerPredicate<(all_of ExtensionHVX64B)>;
 130 def UseHVX128B         : Predicate<"HST->useHVX128BOps()">,
 131                          AssemblerPredicate<(all_of ExtensionHVX128B)>;
 132 def UseHVX             : Predicate<"HST->useHVXOps()">,
 133                          AssemblerPredicate<(all_of ExtensionHVXV60)>;
 134 def UseHVXV60          : Predicate<"HST->useHVXV60Ops()">,
 135                          AssemblerPredicate<(all_of ExtensionHVXV60)>;
 136 def UseHVXV62          : Predicate<"HST->useHVXV62Ops()">,
 137                          AssemblerPredicate<(all_of ExtensionHVXV62)>;
 138 def UseHVXV65          : Predicate<"HST->useHVXV65Ops()">,
 139                          AssemblerPredicate<(all_of ExtensionHVXV65)>;
 140 def UseHVXV66          : Predicate<"HST->useHVXV66Ops()">,
 141                          AssemblerPredicate<(all_of ExtensionHVXV66)>;
 142 def UseHVXV67          : Predicate<"HST->useHVXV67Ops()">,
 143                          AssemblerPredicate<(all_of ExtensionHVXV67)>;
 144 def UseHVXV68          : Predicate<"HST->useHVXV68Ops()">,
 145                          AssemblerPredicate<(all_of ExtensionHVXV68)>;
 146 def UseHVXV69          : Predicate<"HST->useHVXV69Ops()">,
 147                          AssemblerPredicate<(all_of ExtensionHVXV69)>;
 148 def UseHVXV71          : Predicate<"HST->useHVXV71Ops()">,
 149                          AssemblerPredicate<(all_of ExtensionHVXV71)>;
 150 def UseHVXV73          : Predicate<"HST->useHVXV73Ops()">,
 151                          AssemblerPredicate<(all_of ExtensionHVXV73)>;
 152 def UseHVXV75          : Predicate<"HST->useHVXV75Ops()">,
 153                          AssemblerPredicate<(all_of ExtensionHVXV75)>;
 154 def UseHVXV79          : Predicate<"HST->useHVXV79Ops()">,
 155                          AssemblerPredicate<(all_of ExtensionHVXV79)>;
 156 def UseAudio           : Predicate<"HST->useAudioOps()">,
 157                          AssemblerPredicate<(all_of ExtensionAudio)>;
 158 def UseZReg            : Predicate<"HST->useZRegOps()">,
 159                          AssemblerPredicate<(all_of ExtensionZReg)>;
 160 def UseCompound        : Predicate<"HST->useCompound()">;
 161 def HasPreV65          : Predicate<"HST->hasPreV65()">,
 162                          AssemblerPredicate<(all_of FeaturePreV65)>;
 163 def UseHVXIEEEFP       : Predicate<"HST->useHVXIEEEFPOps()">,
 164                          AssemblerPredicate<(all_of ExtensionHVXIEEEFP)>;
 165 def UseHVXQFloat       : Predicate<"HST->useHVXQFloatOps()">,
 166                          AssemblerPredicate<(all_of ExtensionHVXQFloat)>;
 167 def UseHVXFloatingPoint: Predicate<"HST->useHVXFloatingPoint()">;
 168 def HasMemNoShuf       : Predicate<"HST->hasMemNoShuf()">,
 169                          AssemblerPredicate<(all_of FeatureMemNoShuf)>;
 170 def UseUnsafeMath      : Predicate<"HST->useUnsafeMath()">;
 171 def NotOptTinyCore     : Predicate<"!HST->isTinyCore() ||"
 172                                    "MF->getFunction().hasOptSize()"> {
 173   let RecomputePerFunction = 1;
 174 }
 175 def UseSmallData       : Predicate<"HST->useSmallData()">;
 176 def UseCabac           : Predicate<"HST->useCabac()">,
 177                          AssemblerPredicate<(any_of FeatureCabac)>;
 178
 179 def Hvx64:  HwMode<"+hvx-length64b", [UseHVX64B]>;
 180 def Hvx128: HwMode<"+hvx-length128b", [UseHVX128B]>;
 181
 182 //===----------------------------------------------------------------------===//
 183 // Classes used for relation maps.
 184 //===----------------------------------------------------------------------===//
 185
 186 // The classes below should remain in hierarchical order...
 187 class ImmRegShl;
 188 // ImmRegRel - Filter class used to relate instructions having reg-reg form
 189 // with their reg-imm counterparts.
 190 class ImmRegRel;
 191 // PredRel - Filter class used to relate non-predicated instructions with their
 192 // predicated forms.
 193 class PredRel;
 194 class PredNewRel: PredRel;
 195 // NewValueRel - Filter class used to relate regular store instructions with
 196 // their new-value store form.
 197 class NewValueRel: PredNewRel;
 198 class AddrModeRel: NewValueRel;
 199 class PostInc_BaseImm;
 200 class IntrinsicsRel;
 201 // ... through here.
 202
 203 //===----------------------------------------------------------------------===//
 204 // Generate mapping table to relate non-predicate instructions with their
 205 // predicated formats - true and false.
 206 //
 207
 208 def getPredOpcode : InstrMapping {
 209   let FilterClass = "PredRel";
 210   // Instructions with the same BaseOpcode and isNVStore values form a row.
 211   let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"];
 212   // Instructions with the same predicate sense form a column.
 213   let ColFields = ["PredSense"];
 214   // The key column is the unpredicated instructions.
 215   let KeyCol = [""];
 216   // Value columns are PredSense=true and PredSense=false
 217   let ValueCols = [["true"], ["false"]];
 218 }
 219
 220 //===----------------------------------------------------------------------===//
 221 // Generate mapping table to relate predicate-true instructions with their
 222 // predicate-false forms
 223 //
 224 def getFalsePredOpcode : InstrMapping {
 225   let FilterClass = "PredRel";
 226   let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
 227   let ColFields = ["PredSense"];
 228   let KeyCol = ["true"];
 229   let ValueCols = [["false"]];
 230 }
 231
 232 //===----------------------------------------------------------------------===//
 233 // Generate mapping table to relate predicate-false instructions with their
 234 // predicate-true forms
 235 //
 236 def getTruePredOpcode : InstrMapping {
 237   let FilterClass = "PredRel";
 238   let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
 239   let ColFields = ["PredSense"];
 240   let KeyCol = ["false"];
 241   let ValueCols = [["true"]];
 242 }
 243
 244 //===----------------------------------------------------------------------===//
 245 // Generate mapping table to relate predicated instructions with their .new
 246 // format.
 247 //
 248 def getPredNewOpcode : InstrMapping {
 249   let FilterClass = "PredNewRel";
 250   let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
 251   let ColFields = ["PNewValue"];
 252   let KeyCol = [""];
 253   let ValueCols = [["new"]];
 254 }
 255
 256 //===----------------------------------------------------------------------===//
 257 // Generate mapping table to relate .new predicated instructions with their old
 258 // format.
 259 //
 260 def getPredOldOpcode : InstrMapping {
 261   let FilterClass = "PredNewRel";
 262   let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
 263   let ColFields = ["PNewValue"];
 264   let KeyCol = ["new"];
 265   let ValueCols = [[""]];
 266 }
 267
 268 //===----------------------------------------------------------------------===//
 269 // Generate mapping table to relate store instructions with their new-value
 270 // format.
 271 //
 272 def getNewValueOpcode : InstrMapping {
 273   let FilterClass = "NewValueRel";
 274   let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
 275   let ColFields = ["NValueST"];
 276   let KeyCol = ["false"];
 277   let ValueCols = [["true"]];
 278 }
 279
 280 //===----------------------------------------------------------------------===//
 281 // Generate mapping table to relate new-value store instructions with their old
 282 // format.
 283 //
 284 def getNonNVStore : InstrMapping {
 285   let FilterClass = "NewValueRel";
 286   let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
 287   let ColFields = ["NValueST"];
 288   let KeyCol = ["true"];
 289   let ValueCols = [["false"]];
 290 }
 291
 292 def changeAddrMode_abs_io: InstrMapping {
 293   let FilterClass = "AddrModeRel";
 294   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
 295                    "isFloat"];
 296   let ColFields = ["addrMode"];
 297   let KeyCol = ["Absolute"];
 298   let ValueCols = [["BaseImmOffset"]];
 299 }
 300
 301 def changeAddrMode_io_abs: InstrMapping {
 302   let FilterClass = "AddrModeRel";
 303   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
 304                    "isFloat"];
 305   let ColFields = ["addrMode"];
 306   let KeyCol = ["BaseImmOffset"];
 307   let ValueCols = [["Absolute"]];
 308 }
 309
 310 def changeAddrMode_io_rr: InstrMapping {
 311   let FilterClass = "AddrModeRel";
 312   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
 313   let ColFields = ["addrMode"];
 314   let KeyCol = ["BaseImmOffset"];
 315   let ValueCols = [["BaseRegOffset"]];
 316 }
 317
 318 def changeAddrMode_rr_io: InstrMapping {
 319   let FilterClass = "AddrModeRel";
 320   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
 321   let ColFields = ["addrMode"];
 322   let KeyCol = ["BaseRegOffset"];
 323   let ValueCols = [["BaseImmOffset"]];
 324 }
 325
 326 def changeAddrMode_pi_io: InstrMapping {
 327   let FilterClass = "PostInc_BaseImm";
 328   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
 329   let ColFields = ["addrMode"];
 330   let KeyCol = ["PostInc"];
 331   let ValueCols = [["BaseImmOffset"]];
 332 }
 333
 334 def changeAddrMode_io_pi: InstrMapping {
 335   let FilterClass = "PostInc_BaseImm";
 336   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
 337   let ColFields = ["addrMode"];
 338   let KeyCol = ["BaseImmOffset"];
 339   let ValueCols = [["PostInc"]];
 340 }
 341
 342 def changeAddrMode_rr_ur: InstrMapping {
 343   let FilterClass = "ImmRegShl";
 344   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
 345   let ColFields = ["addrMode"];
 346   let KeyCol = ["BaseRegOffset"];
 347   let ValueCols = [["BaseLongOffset"]];
 348 }
 349
 350 def changeAddrMode_ur_rr: InstrMapping {
 351   let FilterClass = "ImmRegShl";
 352   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
 353   let ColFields = ["addrMode"];
 354   let KeyCol = ["BaseLongOffset"];
 355   let ValueCols = [["BaseRegOffset"]];
 356 }
 357
 358 def getRegForm : InstrMapping {
 359   let FilterClass = "ImmRegRel";
 360   let RowFields = ["CextOpcode", "PredSense", "PNewValue"];
 361   let ColFields = ["InputType"];
 362   let KeyCol = ["imm"];
 363   let ValueCols = [["reg"]];
 364 }
 365
 366 def notTakenBranchPrediction : InstrMapping {
 367   let FilterClass = "PredRel";
 368   let RowFields = ["BaseOpcode", "PNewValue",  "PredSense", "isBranch", "isPredicated"];
 369   let ColFields = ["isBrTaken"];
 370   let KeyCol = ["true"];
 371   let ValueCols = [["false"]];
 372 }
 373
 374 def takenBranchPrediction : InstrMapping {
 375   let FilterClass = "PredRel";
 376   let RowFields = ["BaseOpcode", "PNewValue",  "PredSense", "isBranch", "isPredicated"];
 377   let ColFields = ["isBrTaken"];
 378   let KeyCol = ["false"];
 379   let ValueCols = [["true"]];
 380 }
 381
 382 def getRealHWInstr : InstrMapping {
 383   let FilterClass = "IntrinsicsRel";
 384   let RowFields = ["BaseOpcode"];
 385   let ColFields = ["InstrType"];
 386   let KeyCol = ["Pseudo"];
 387   let ValueCols = [["Pseudo"], ["Real"]];
 388 }
 389 //===----------------------------------------------------------------------===//
 390 // Register File, Instruction Descriptions
 391 //===----------------------------------------------------------------------===//
 392 include "HexagonSchedule.td"
 393 include "HexagonRegisterInfo.td"
 394 include "HexagonOperands.td"
 395 include "HexagonDepOperands.td"
 396 include "HexagonDepITypes.td"
 397 include "HexagonInstrFormats.td"
 398 include "HexagonDepInstrFormats.td"
 399 include "HexagonDepInstrInfo.td"
 400 include "HexagonCallingConv.td"
 401 include "HexagonPseudo.td"
 402 include "HexagonPatterns.td"
 403 include "HexagonPatternsHVX.td"
 404 include "HexagonPatternsV65.td"
 405 include "HexagonDepMappings.td"
 406 include "HexagonIntrinsics.td"
 407
 408 def HexagonInstrInfo : InstrInfo;
 409
 410 //===----------------------------------------------------------------------===//
 411 // Hexagon processors supported.
 412 //===----------------------------------------------------------------------===//
 413
 414 class Proc<string Name, SchedMachineModel Model,
 415            list<SubtargetFeature> Features>
 416  : ProcessorModel<Name, Model, Features>;
 417
 418 def : Proc<"generic", HexagonModelV60,
 419            [ArchV5, ArchV55, ArchV60,
 420             FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops,
 421             FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,
 422             FeatureCabac]>;
 423 def : Proc<"hexagonv5",  HexagonModelV5,
 424            [ArchV5,
 425             FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops,
 426             FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,
 427             FeatureCabac]>;
 428 def : Proc<"hexagonv55", HexagonModelV55,
 429            [ArchV5, ArchV55,
 430             FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops,
 431             FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,
 432             FeatureCabac]>;
 433 def : Proc<"hexagonv60", HexagonModelV60,
 434            [ArchV5, ArchV55, ArchV60,
 435             FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops,
 436             FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,
 437             FeatureCabac]>;
 438 def : Proc<"hexagonv62", HexagonModelV62,
 439            [ArchV5, ArchV55, ArchV60, ArchV62,
 440             FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops,
 441             FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,
 442             FeatureCabac]>;
 443 def : Proc<"hexagonv65", HexagonModelV65,
 444            [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,
 445             FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
 446             FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,
 447             FeatureCabac]>;
 448 def : Proc<"hexagonv66", HexagonModelV66,
 449            [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66,
 450             FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
 451             FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,
 452             FeatureCabac]>;
 453 def : Proc<"hexagonv67", HexagonModelV67,
 454            [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
 455             FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
 456             FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,
 457             FeatureCabac]>;
 458 def : Proc<"hexagonv68", HexagonModelV68,
 459            [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
 460             ArchV68,
 461             FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
 462             FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,
 463             FeatureCabac]>;
 464 def : Proc<"hexagonv69", HexagonModelV69,
 465            [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
 466             ArchV68, ArchV69,
 467             FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
 468             FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,
 469             FeatureCabac]>;
 470 def : Proc<"hexagonv71", HexagonModelV71,
 471            [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
 472             ArchV68, ArchV69, ArchV71,
 473             FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
 474             FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,
 475             FeatureCabac]>;
 476 def : Proc<"hexagonv73", HexagonModelV73,
 477            [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
 478             ArchV68, ArchV69, ArchV71, ArchV73,
 479             FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
 480             FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
 481 def : Proc<"hexagonv75", HexagonModelV75,
 482            [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
 483            ArchV68, ArchV69, ArchV71, ArchV73, ArchV75, FeatureCompound,
 484            FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,
 485            FeatureNVS, FeaturePackets, FeatureSmallData]>;
 486 def : Proc<"hexagonv79", HexagonModelV79,
 487            [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
 488            ArchV68, ArchV69, ArchV71, ArchV73, ArchV75, ArchV79,
 489            FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
 490            FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
 491
 492 // Need to update the correct features for tiny core.
 493 // Disable NewValueJumps since the packetizer is unable to handle a packet with
 494 // a new value jump and another SLOT0 instruction.
 495 def : Proc<"hexagonv67t", HexagonModelV67T,
 496            [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
 497             ProcTinyCore, ExtensionAudio,
 498             FeatureCompound, FeatureMemNoShuf, FeatureMemops,
 499             FeatureNVS, FeaturePackets, FeatureSmallData]>;
 500
 501 def : Proc<"hexagonv71t", HexagonModelV71T,
 502            [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
 503             ArchV68, ArchV69, ArchV71,
 504             ProcTinyCore, ExtensionAudio,
 505             FeatureCompound, FeatureMemNoShuf, FeatureMemops,
 506             FeatureNVS, FeaturePackets, FeatureSmallData]>;
 507
 508 //===----------------------------------------------------------------------===//
 509 // Declare the target which we are implementing
 510 //===----------------------------------------------------------------------===//
 511
 512 def HexagonAsmParser : AsmParser {
 513   let ShouldEmitMatchRegisterAltName = 1;
 514   bit HasMnemonicFirst = 0;
 515 }
 516
 517 def HexagonAsmParserVariant : AsmParserVariant {
 518   int Variant = 0;
 519   string TokenizingCharacters = "#()=:.<>!+*-|^&";
 520   string BreakCharacters = "";
 521 }
 522
 523 def HexagonAsmWriter : AsmWriter {
 524   string AsmWriterClassName  = "InstPrinter";
 525   bit isMCAsmWriter = 1;
 526 }
 527
 528 def Hexagon : Target {
 529   let InstructionSet = HexagonInstrInfo;
 530   let AssemblyParsers = [HexagonAsmParser];
 531   let AssemblyParserVariants = [HexagonAsmParserVariant];
 532   let AssemblyWriters = [HexagonAsmWriter];
 533   let AllowRegisterRenaming = 1;
 534 }