llvm/lib/Target/Hexagon/HexagonInstrInfo.h

   1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
  14 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
  15
  16 #include "MCTargetDesc/HexagonBaseInfo.h"
  17 #include "llvm/ADT/ArrayRef.h"
  18 #include "llvm/ADT/SmallVector.h"
  19 #include "llvm/CodeGen/MachineBasicBlock.h"
  20 #include "llvm/CodeGen/TargetInstrInfo.h"
  21 #include "llvm/CodeGen/ValueTypes.h"
  22 #include "llvm/CodeGenTypes/MachineValueType.h"
  23 #include <cstdint>
  24 #include <vector>
  25
  26 #define GET_INSTRINFO_HEADER
  27 #include "HexagonGenInstrInfo.inc"
  28
  29 namespace llvm {
  30
  31 class HexagonSubtarget;
  32 class MachineBranchProbabilityInfo;
  33 class MachineFunction;
  34 class MachineInstr;
  35 class MachineOperand;
  36 class TargetRegisterInfo;
  37
  38 class HexagonInstrInfo : public HexagonGenInstrInfo {
  39   const HexagonSubtarget &Subtarget;
  40
  41   enum BundleAttribute {
  42     memShufDisabledMask = 0x4
  43   };
  44
  45   virtual void anchor();
  46
  47 public:
  48   explicit HexagonInstrInfo(HexagonSubtarget &ST);
  49
  50   /// TargetInstrInfo overrides.
  51
  52   /// If the specified machine instruction is a direct
  53   /// load from a stack slot, return the virtual or physical register number of
  54   /// the destination along with the FrameIndex of the loaded stack slot.  If
  55   /// not, return 0.  This predicate must return 0 if the instruction has
  56   /// any side effects other than loading from the stack slot.
  57   Register isLoadFromStackSlot(const MachineInstr &MI,
  58                                int &FrameIndex) const override;
  59
  60   /// If the specified machine instruction is a direct
  61   /// store to a stack slot, return the virtual or physical register number of
  62   /// the source reg along with the FrameIndex of the loaded stack slot.  If
  63   /// not, return 0.  This predicate must return 0 if the instruction has
  64   /// any side effects other than storing to the stack slot.
  65   Register isStoreToStackSlot(const MachineInstr &MI,
  66                               int &FrameIndex) const override;
  67
  68   /// Check if the instruction or the bundle of instructions has
  69   /// load from stack slots. Return the frameindex and machine memory operand
  70   /// if true.
  71   bool hasLoadFromStackSlot(
  72       const MachineInstr &MI,
  73       SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
  74
  75   /// Check if the instruction or the bundle of instructions has
  76   /// store to stack slots. Return the frameindex and machine memory operand
  77   /// if true.
  78   bool hasStoreToStackSlot(
  79       const MachineInstr &MI,
  80       SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
  81
  82   /// Analyze the branching code at the end of MBB, returning
  83   /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
  84   /// implemented for a target).  Upon success, this returns false and returns
  85   /// with the following information in various cases:
  86   ///
  87   /// 1. If this block ends with no branches (it just falls through to its succ)
  88   ///    just return false, leaving TBB/FBB null.
  89   /// 2. If this block ends with only an unconditional branch, it sets TBB to be
  90   ///    the destination block.
  91   /// 3. If this block ends with a conditional branch and it falls through to a
  92   ///    successor block, it sets TBB to be the branch destination block and a
  93   ///    list of operands that evaluate the condition. These operands can be
  94   ///    passed to other TargetInstrInfo methods to create new branches.
  95   /// 4. If this block ends with a conditional branch followed by an
  96   ///    unconditional branch, it returns the 'true' destination in TBB, the
  97   ///    'false' destination in FBB, and a list of operands that evaluate the
  98   ///    condition.  These operands can be passed to other TargetInstrInfo
  99   ///    methods to create new branches.
 100   ///
 101   /// Note that removeBranch and insertBranch must be implemented to support
 102   /// cases where this method returns success.
 103   ///
 104   /// If AllowModify is true, then this routine is allowed to modify the basic
 105   /// block (e.g. delete instructions after the unconditional branch).
 106   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 107                      MachineBasicBlock *&FBB,
 108                      SmallVectorImpl<MachineOperand> &Cond,
 109                      bool AllowModify) const override;
 110
 111   /// Remove the branching code at the end of the specific MBB.
 112   /// This is only invoked in cases where analyzeBranch returns success. It
 113   /// returns the number of instructions that were removed.
 114   unsigned removeBranch(MachineBasicBlock &MBB,
 115                         int *BytesRemoved = nullptr) const override;
 116
 117   /// Insert branch code into the end of the specified MachineBasicBlock.
 118   /// The operands to this method are the same as those
 119   /// returned by analyzeBranch.  This is only invoked in cases where
 120   /// analyzeBranch returns success. It returns the number of instructions
 121   /// inserted.
 122   ///
 123   /// It is also invoked by tail merging to add unconditional branches in
 124   /// cases where analyzeBranch doesn't apply because there was no original
 125   /// branch to analyze.  At least this much must be implemented, else tail
 126   /// merging needs to be disabled.
 127   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 128                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
 129                         const DebugLoc &DL,
 130                         int *BytesAdded = nullptr) const override;
 131
 132   /// Analyze loop L, which must be a single-basic-block loop, and if the
 133   /// conditions can be understood enough produce a PipelinerLoopInfo object.
 134   std::unique_ptr<PipelinerLoopInfo>
 135   analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
 136
 137   /// Return true if it's profitable to predicate
 138   /// instructions with accumulated instruction latency of "NumCycles"
 139   /// of the specified basic block, where the probability of the instructions
 140   /// being executed is given by Probability, and Confidence is a measure
 141   /// of our confidence that it will be properly predicted.
 142   bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
 143                            unsigned ExtraPredCycles,
 144                            BranchProbability Probability) const override;
 145
 146   /// Second variant of isProfitableToIfCvt. This one
 147   /// checks for the case where two basic blocks from true and false path
 148   /// of a if-then-else (diamond) are predicated on mutally exclusive
 149   /// predicates, where the probability of the true path being taken is given
 150   /// by Probability, and Confidence is a measure of our confidence that it
 151   /// will be properly predicted.
 152   bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
 153                            unsigned NumTCycles, unsigned ExtraTCycles,
 154                            MachineBasicBlock &FMBB,
 155                            unsigned NumFCycles, unsigned ExtraFCycles,
 156                            BranchProbability Probability) const override;
 157
 158   /// Return true if it's profitable for if-converter to duplicate instructions
 159   /// of specified accumulated instruction latencies in the specified MBB to
 160   /// enable if-conversion.
 161   /// The probability of the instructions being executed is given by
 162   /// Probability, and Confidence is a measure of our confidence that it
 163   /// will be properly predicted.
 164   bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
 165                                  BranchProbability Probability) const override;
 166
 167   /// Emit instructions to copy a pair of physical registers.
 168   ///
 169   /// This function should support copies within any legal register class as
 170   /// well as any cross-class copies created during instruction selection.
 171   ///
 172   /// The source and destination registers may overlap, which may require a
 173   /// careful implementation when multiple copy instructions are required for
 174   /// large registers. See for example the ARM target.
 175   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 176                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
 177                    bool KillSrc, bool RenamableDest = false,
 178                    bool RenamableSrc = false) const override;
 179
 180   /// Store the specified register of the given register class to the specified
 181   /// stack frame index. The store instruction is to be added to the given
 182   /// machine basic block before the specified machine instruction. If isKill
 183   /// is true, the register operand is the last use and must be marked kill.
 184   void storeRegToStackSlot(MachineBasicBlock &MBB,
 185                            MachineBasicBlock::iterator MBBI, Register SrcReg,
 186                            bool isKill, int FrameIndex,
 187                            const TargetRegisterClass *RC,
 188                            const TargetRegisterInfo *TRI,
 189                            Register VReg) const override;
 190
 191   /// Load the specified register of the given register class from the specified
 192   /// stack frame index. The load instruction is to be added to the given
 193   /// machine basic block before the specified machine instruction.
 194   void loadRegFromStackSlot(MachineBasicBlock &MBB,
 195                             MachineBasicBlock::iterator MBBI, Register DestReg,
 196                             int FrameIndex, const TargetRegisterClass *RC,
 197                             const TargetRegisterInfo *TRI,
 198                             Register VReg) const override;
 199
 200   /// This function is called for all pseudo instructions
 201   /// that remain after register allocation. Many pseudo instructions are
 202   /// created to help register allocation. This is the place to convert them
 203   /// into real instructions. The target can edit MI in place, or it can insert
 204   /// new instructions and erase MI. The function should return true if
 205   /// anything was changed.
 206   bool expandPostRAPseudo(MachineInstr &MI) const override;
 207
 208   /// Get the base register and byte offset of a load/store instr.
 209   bool getMemOperandsWithOffsetWidth(
 210       const MachineInstr &LdSt,
 211       SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
 212       bool &OffsetIsScalable, LocationSize &Width,
 213       const TargetRegisterInfo *TRI) const override;
 214
 215   /// Reverses the branch condition of the specified condition list,
 216   /// returning false on success and true if it cannot be reversed.
 217   bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
 218         const override;
 219
 220   /// Insert a noop into the instruction stream at the specified point.
 221   void insertNoop(MachineBasicBlock &MBB,
 222                   MachineBasicBlock::iterator MI) const override;
 223
 224   /// Returns true if the instruction is already predicated.
 225   bool isPredicated(const MachineInstr &MI) const override;
 226
 227   /// Return true for post-incremented instructions.
 228   bool isPostIncrement(const MachineInstr &MI) const override;
 229
 230   /// Convert the instruction into a predicated instruction.
 231   /// It returns true if the operation was successful.
 232   bool PredicateInstruction(MachineInstr &MI,
 233                             ArrayRef<MachineOperand> Cond) const override;
 234
 235   /// Returns true if the first specified predicate
 236   /// subsumes the second, e.g. GE subsumes GT.
 237   bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
 238                          ArrayRef<MachineOperand> Pred2) const override;
 239
 240   /// If the specified instruction defines any predicate
 241   /// or condition code register(s) used for predication, returns true as well
 242   /// as the definition predicate(s) by reference.
 243   bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
 244                          bool SkipDead) const override;
 245
 246   /// Return true if the specified instruction can be predicated.
 247   /// By default, this returns true for every instruction with a
 248   /// PredicateOperand.
 249   bool isPredicable(const MachineInstr &MI) const override;
 250
 251   /// Test if the given instruction should be considered a scheduling boundary.
 252   /// This primarily includes labels and terminators.
 253   bool isSchedulingBoundary(const MachineInstr &MI,
 254                             const MachineBasicBlock *MBB,
 255                             const MachineFunction &MF) const override;
 256
 257   /// Measure the specified inline asm to determine an approximation of its
 258   /// length.
 259   unsigned getInlineAsmLength(
 260     const char *Str,
 261     const MCAsmInfo &MAI,
 262     const TargetSubtargetInfo *STI = nullptr) const override;
 263
 264   /// Allocate and return a hazard recognizer to use for this target when
 265   /// scheduling the machine instructions after register allocation.
 266   ScheduleHazardRecognizer*
 267   CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
 268                                      const ScheduleDAG *DAG) const override;
 269
 270   /// For a comparison instruction, return the source registers
 271   /// in SrcReg and SrcReg2 if having two register operands, and the value it
 272   /// compares against in CmpValue. Return true if the comparison instruction
 273   /// can be analyzed.
 274   bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
 275                       Register &SrcReg2, int64_t &Mask,
 276                       int64_t &Value) const override;
 277
 278   /// Compute the instruction latency of a given instruction.
 279   /// If the instruction has higher cost when predicated, it's returned via
 280   /// PredCost.
 281   unsigned getInstrLatency(const InstrItineraryData *ItinData,
 282                            const MachineInstr &MI,
 283                            unsigned *PredCost = nullptr) const override;
 284
 285   /// Create machine specific model for scheduling.
 286   DFAPacketizer *
 287   CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
 288
 289   // Sometimes, it is possible for the target
 290   // to tell, even without aliasing information, that two MIs access different
 291   // memory addresses. This function returns true if two MIs access different
 292   // memory addresses and false otherwise.
 293   bool
 294   areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
 295                                   const MachineInstr &MIb) const override;
 296
 297   /// For instructions with a base and offset, return the position of the
 298   /// base register and offset operands.
 299   bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
 300                                 unsigned &OffsetPos) const override;
 301
 302   /// If the instruction is an increment of a constant value, return the amount.
 303   bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
 304
 305   /// getOperandLatency - Compute and return the use operand latency of a given
 306   /// pair of def and use.
 307   /// In most cases, the static scheduling itinerary was enough to determine the
 308   /// operand latency. But it may not be possible for instructions with variable
 309   /// number of defs / uses.
 310   ///
 311   /// This is a raw interface to the itinerary that may be directly overriden by
 312   /// a target. Use computeOperandLatency to get the best estimate of latency.
 313   std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
 314                                             const MachineInstr &DefMI,
 315                                             unsigned DefIdx,
 316                                             const MachineInstr &UseMI,
 317                                             unsigned UseIdx) const override;
 318
 319   /// Decompose the machine operand's target flags into two values - the direct
 320   /// target flag value and any of bit flags that are applied.
 321   std::pair<unsigned, unsigned>
 322   decomposeMachineOperandsTargetFlags(unsigned TF) const override;
 323
 324   /// Return an array that contains the direct target flag values and their
 325   /// names.
 326   ///
 327   /// MIR Serialization is able to serialize only the target flags that are
 328   /// defined by this method.
 329   ArrayRef<std::pair<unsigned, const char *>>
 330   getSerializableDirectMachineOperandTargetFlags() const override;
 331
 332   /// Return an array that contains the bitmask target flag values and their
 333   /// names.
 334   ///
 335   /// MIR Serialization is able to serialize only the target flags that are
 336   /// defined by this method.
 337   ArrayRef<std::pair<unsigned, const char *>>
 338   getSerializableBitmaskMachineOperandTargetFlags() const override;
 339
 340   bool isTailCall(const MachineInstr &MI) const override;
 341   bool isAsCheapAsAMove(const MachineInstr &MI) const override;
 342
 343   // Return true if the instruction should be sunk by MachineSink.
 344   // MachineSink determines on its own whether the instruction is safe to sink;
 345   // this gives the target a hook to override the default behavior with regards
 346   // to which instructions should be sunk.
 347   bool shouldSink(const MachineInstr &MI) const override;
 348
 349   /// HexagonInstrInfo specifics.
 350
 351   Register createVR(MachineFunction *MF, MVT VT) const;
 352   MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp,
 353                               MachineBasicBlock *TargetBB,
 354                               SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
 355
 356   bool isAbsoluteSet(const MachineInstr &MI) const;
 357   bool isAccumulator(const MachineInstr &MI) const;
 358   bool isAddrModeWithOffset(const MachineInstr &MI) const;
 359   bool isBaseImmOffset(const MachineInstr &MI) const;
 360   bool isComplex(const MachineInstr &MI) const;
 361   bool isCompoundBranchInstr(const MachineInstr &MI) const;
 362   bool isConstExtended(const MachineInstr &MI) const;
 363   bool isDeallocRet(const MachineInstr &MI) const;
 364   bool isDependent(const MachineInstr &ProdMI,
 365                    const MachineInstr &ConsMI) const;
 366   bool isDotCurInst(const MachineInstr &MI) const;
 367   bool isDotNewInst(const MachineInstr &MI) const;
 368   bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
 369   bool isEndLoopN(unsigned Opcode) const;
 370   bool isExpr(unsigned OpType) const;
 371   bool isExtendable(const MachineInstr &MI) const;
 372   bool isExtended(const MachineInstr &MI) const;
 373   bool isFloat(const MachineInstr &MI) const;
 374   bool isHVXMemWithAIndirect(const MachineInstr &I,
 375                              const MachineInstr &J) const;
 376   bool isIndirectCall(const MachineInstr &MI) const;
 377   bool isIndirectL4Return(const MachineInstr &MI) const;
 378   bool isJumpR(const MachineInstr &MI) const;
 379   bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const;
 380   bool isLateSourceInstr(const MachineInstr &MI) const;
 381   bool isLoopN(const MachineInstr &MI) const;
 382   bool isMemOp(const MachineInstr &MI) const;
 383   bool isNewValue(const MachineInstr &MI) const;
 384   bool isNewValue(unsigned Opcode) const;
 385   bool isNewValueInst(const MachineInstr &MI) const;
 386   bool isNewValueJump(const MachineInstr &MI) const;
 387   bool isNewValueJump(unsigned Opcode) const;
 388   bool isNewValueStore(const MachineInstr &MI) const;
 389   bool isNewValueStore(unsigned Opcode) const;
 390   bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const;
 391   bool isPredicatedNew(const MachineInstr &MI) const;
 392   bool isPredicatedNew(unsigned Opcode) const;
 393   bool isPredicatedTrue(const MachineInstr &MI) const;
 394   bool isPredicatedTrue(unsigned Opcode) const;
 395   bool isPredicated(unsigned Opcode) const;
 396   bool isPredicateLate(unsigned Opcode) const;
 397   bool isPredictedTaken(unsigned Opcode) const;
 398   bool isPureSlot0(const MachineInstr &MI) const;
 399   bool isRestrictNoSlot1Store(const MachineInstr &MI) const;
 400   bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const;
 401   bool isSignExtendingLoad(const MachineInstr &MI) const;
 402   bool isSolo(const MachineInstr &MI) const;
 403   bool isSpillPredRegOp(const MachineInstr &MI) const;
 404   bool isTC1(const MachineInstr &MI) const;
 405   bool isTC2(const MachineInstr &MI) const;
 406   bool isTC2Early(const MachineInstr &MI) const;
 407   bool isTC4x(const MachineInstr &MI) const;
 408   bool isToBeScheduledASAP(const MachineInstr &MI1,
 409                            const MachineInstr &MI2) const;
 410   bool isHVXVec(const MachineInstr &MI) const;
 411   bool isValidAutoIncImm(const EVT VT, const int Offset) const;
 412   bool isValidOffset(unsigned Opcode, int Offset,
 413                      const TargetRegisterInfo *TRI, bool Extend = true) const;
 414   bool isVecAcc(const MachineInstr &MI) const;
 415   bool isVecALU(const MachineInstr &MI) const;
 416   bool isVecUsableNextPacket(const MachineInstr &ProdMI,
 417                              const MachineInstr &ConsMI) const;
 418   bool isZeroExtendingLoad(const MachineInstr &MI) const;
 419
 420   bool addLatencyToSchedule(const MachineInstr &MI1,
 421                             const MachineInstr &MI2) const;
 422   bool canExecuteInBundle(const MachineInstr &First,
 423                           const MachineInstr &Second) const;
 424   bool doesNotReturn(const MachineInstr &CallMI) const;
 425   bool hasEHLabel(const MachineBasicBlock *B) const;
 426   bool hasNonExtEquivalent(const MachineInstr &MI) const;
 427   bool hasPseudoInstrPair(const MachineInstr &MI) const;
 428   bool hasUncondBranch(const MachineBasicBlock *B) const;
 429   bool mayBeCurLoad(const MachineInstr &MI) const;
 430   bool mayBeNewStore(const MachineInstr &MI) const;
 431   bool producesStall(const MachineInstr &ProdMI,
 432                      const MachineInstr &ConsMI) const;
 433   bool producesStall(const MachineInstr &MI,
 434                      MachineBasicBlock::const_instr_iterator MII) const;
 435   bool predCanBeUsedAsDotNew(const MachineInstr &MI, Register PredReg) const;
 436   bool PredOpcodeHasJMP_c(unsigned Opcode) const;
 437   bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
 438
 439   unsigned getAddrMode(const MachineInstr &MI) const;
 440   MachineOperand *getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
 441                                    LocationSize &AccessSize) const;
 442   SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
 443   unsigned getCExtOpNum(const MachineInstr &MI) const;
 444   HexagonII::CompoundGroup
 445   getCompoundCandidateGroup(const MachineInstr &MI) const;
 446   unsigned getCompoundOpcode(const MachineInstr &GA,
 447                              const MachineInstr &GB) const;
 448   int getDuplexOpcode(const MachineInstr &MI, bool ForBigCore = true) const;
 449   int getCondOpcode(int Opc, bool sense) const;
 450   int getDotCurOp(const MachineInstr &MI) const;
 451   int getNonDotCurOp(const MachineInstr &MI) const;
 452   int getDotNewOp(const MachineInstr &MI) const;
 453   int getDotNewPredJumpOp(const MachineInstr &MI,
 454                           const MachineBranchProbabilityInfo *MBPI) const;
 455   int getDotNewPredOp(const MachineInstr &MI,
 456                       const MachineBranchProbabilityInfo *MBPI) const;
 457   int getDotOldOp(const MachineInstr &MI) const;
 458   HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI)
 459                                                          const;
 460   short getEquivalentHWInstr(const MachineInstr &MI) const;
 461   unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
 462                                       const MachineInstr &MI) const;
 463   bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
 464   unsigned getInvertedPredicatedOpcode(const int Opc) const;
 465   int getMaxValue(const MachineInstr &MI) const;
 466   unsigned getMemAccessSize(const MachineInstr &MI) const;
 467   int getMinValue(const MachineInstr &MI) const;
 468   short getNonExtOpcode(const MachineInstr &MI) const;
 469   bool getPredReg(ArrayRef<MachineOperand> Cond, Register &PredReg,
 470                   unsigned &PredRegPos, unsigned &PredRegFlags) const;
 471   short getPseudoInstrPair(const MachineInstr &MI) const;
 472   short getRegForm(const MachineInstr &MI) const;
 473   unsigned getSize(const MachineInstr &MI) const;
 474   uint64_t getType(const MachineInstr &MI) const;
 475   InstrStage::FuncUnits getUnits(const MachineInstr &MI) const;
 476
 477   MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const;
 478
 479   /// getInstrTimingClassLatency - Compute the instruction latency of a given
 480   /// instruction using Timing Class information, if available.
 481   unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
 482   unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
 483
 484   void immediateExtend(MachineInstr &MI) const;
 485   bool invertAndChangeJumpTarget(MachineInstr &MI,
 486                                  MachineBasicBlock *NewTarget) const;
 487   void genAllInsnTimingClasses(MachineFunction &MF) const;
 488   bool reversePredSense(MachineInstr &MI) const;
 489   unsigned reversePrediction(unsigned Opcode) const;
 490   bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
 491
 492   void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const;
 493   bool getBundleNoShuf(const MachineInstr &MIB) const;
 494
 495   // When TinyCore with Duplexes is enabled, this function is used to translate
 496   // tiny-instructions to big-instructions and vice versa to get the slot
 497   // consumption.
 498   void changeDuplexOpcode(MachineBasicBlock::instr_iterator MII,
 499                           bool ToBigInstrs) const;
 500   void translateInstrsForDup(MachineFunction &MF,
 501                              bool ToBigInstrs = true) const;
 502   void translateInstrsForDup(MachineBasicBlock::instr_iterator MII,
 503                              bool ToBigInstrs) const;
 504
 505   // Addressing mode relations.
 506   short changeAddrMode_abs_io(short Opc) const;
 507   short changeAddrMode_io_abs(short Opc) const;
 508   short changeAddrMode_io_pi(short Opc) const;
 509   short changeAddrMode_io_rr(short Opc) const;
 510   short changeAddrMode_pi_io(short Opc) const;
 511   short changeAddrMode_rr_io(short Opc) const;
 512   short changeAddrMode_rr_ur(short Opc) const;
 513   short changeAddrMode_ur_rr(short Opc) const;
 514
 515   short changeAddrMode_abs_io(const MachineInstr &MI) const {
 516     return changeAddrMode_abs_io(MI.getOpcode());
 517   }
 518   short changeAddrMode_io_abs(const MachineInstr &MI) const {
 519     return changeAddrMode_io_abs(MI.getOpcode());
 520   }
 521   short changeAddrMode_io_rr(const MachineInstr &MI) const {
 522     return changeAddrMode_io_rr(MI.getOpcode());
 523   }
 524   short changeAddrMode_rr_io(const MachineInstr &MI) const {
 525     return changeAddrMode_rr_io(MI.getOpcode());
 526   }
 527   short changeAddrMode_rr_ur(const MachineInstr &MI) const {
 528     return changeAddrMode_rr_ur(MI.getOpcode());
 529   }
 530   short changeAddrMode_ur_rr(const MachineInstr &MI) const {
 531     return changeAddrMode_ur_rr(MI.getOpcode());
 532   }
 533
 534   MCInst getNop() const override;
 535 };
 536
 537 } // end namespace llvm
 538
 539 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H