llvm/lib/Target/NVPTX/NVPTXInstrInfo.h

   1 //===- NVPTXInstrInfo.h - NVPTX Instruction Information----------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the NVPTX implementation of the TargetInstrInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
  14 #define LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
  15
  16 #include "NVPTX.h"
  17 #include "NVPTXRegisterInfo.h"
  18 #include "llvm/CodeGen/TargetInstrInfo.h"
  19
  20 #define GET_INSTRINFO_HEADER
  21 #include "NVPTXGenInstrInfo.inc"
  22
  23 namespace llvm {
  24
  25 class NVPTXInstrInfo : public NVPTXGenInstrInfo {
  26   const NVPTXRegisterInfo RegInfo;
  27   virtual void anchor();
  28 public:
  29   explicit NVPTXInstrInfo();
  30
  31   const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
  32
  33   /* The following virtual functions are used in register allocation.
  34    * They are not implemented because the existing interface and the logic
  35    * at the caller side do not work for the elementized vector load and store.
  36    *
  37    * virtual Register isLoadFromStackSlot(const MachineInstr *MI,
  38    *                                  int &FrameIndex) const;
  39    * virtual Register isStoreToStackSlot(const MachineInstr *MI,
  40    *                                 int &FrameIndex) const;
  41    * virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  42    *                              MachineBasicBlock::iterator MBBI,
  43    *                             unsigned SrcReg, bool isKill, int FrameIndex,
  44    *                              const TargetRegisterClass *RC,
  45    *                              Register VReg) const;
  46    * virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  47    *                               MachineBasicBlock::iterator MBBI,
  48    *                               unsigned DestReg, int FrameIndex,
  49    *                               const TargetRegisterClass *RC,
  50    *                               const TargetRegisterInfo *TRI,
  51    *                               Register VReg) const;
  52    */
  53
  54   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
  55                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
  56                    bool KillSrc, bool RenamableDest = false,
  57                    bool RenamableSrc = false) const override;
  58
  59   // Branch analysis.
  60   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  61                      MachineBasicBlock *&FBB,
  62                      SmallVectorImpl<MachineOperand> &Cond,
  63                      bool AllowModify) const override;
  64   unsigned removeBranch(MachineBasicBlock &MBB,
  65                         int *BytesRemoved = nullptr) const override;
  66   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  67                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
  68                         const DebugLoc &DL,
  69                         int *BytesAdded = nullptr) const override;
  70   bool isSchedulingBoundary(const MachineInstr &MI,
  71                             const MachineBasicBlock *MBB,
  72                             const MachineFunction &MF) const override;
  73 };
  74
  75 } // namespace llvm
  76
  77 #endif