llvm/lib/Target/PowerPC/PPCInstrInfo.h

   1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
  14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
  15
  16 #include "MCTargetDesc/PPCMCTargetDesc.h"
  17 #include "PPC.h"
  18 #include "PPCRegisterInfo.h"
  19 #include "llvm/ADT/SmallSet.h"
  20 #include "llvm/CodeGen/LiveVariables.h"
  21 #include "llvm/CodeGen/TargetInstrInfo.h"
  22
  23 #define GET_INSTRINFO_HEADER
  24 #include "PPCGenInstrInfo.inc"
  25
  26 namespace llvm {
  27
  28 // Instructions that have an immediate form might be convertible to that
  29 // form if the correct input is a result of a load immediate. In order to
  30 // know whether the transformation is special, we might need to know some
  31 // of the details of the two forms.
  32 struct ImmInstrInfo {
  33   // Is the immediate field in the immediate form signed or unsigned?
  34   uint64_t SignedImm : 1;
  35   // Does the immediate need to be a multiple of some value?
  36   uint64_t ImmMustBeMultipleOf : 5;
  37   // Is R0/X0 treated specially by the original r+r instruction?
  38   // If so, in which operand?
  39   uint64_t ZeroIsSpecialOrig : 3;
  40   // Is R0/X0 treated specially by the new r+i instruction?
  41   // If so, in which operand?
  42   uint64_t ZeroIsSpecialNew : 3;
  43   // Is the operation commutative?
  44   uint64_t IsCommutative : 1;
  45   // The operand number to check for add-immediate def.
  46   uint64_t OpNoForForwarding : 3;
  47   // The operand number for the immediate.
  48   uint64_t ImmOpNo : 3;
  49   // The opcode of the new instruction.
  50   uint64_t ImmOpcode : 16;
  51   // The size of the immediate.
  52   uint64_t ImmWidth : 5;
  53   // The immediate should be truncated to N bits.
  54   uint64_t TruncateImmTo : 5;
  55   // Is the instruction summing the operand
  56   uint64_t IsSummingOperands : 1;
  57 };
  58
  59 // Information required to convert an instruction to just a materialized
  60 // immediate.
  61 struct LoadImmediateInfo {
  62   unsigned Imm : 16;
  63   unsigned Is64Bit : 1;
  64   unsigned SetCR : 1;
  65 };
  66
  67 // Index into the OpcodesForSpill array.
  68 enum SpillOpcodeKey {
  69   SOK_Int4Spill,
  70   SOK_Int8Spill,
  71   SOK_Float8Spill,
  72   SOK_Float4Spill,
  73   SOK_CRSpill,
  74   SOK_CRBitSpill,
  75   SOK_VRVectorSpill,
  76   SOK_VSXVectorSpill,
  77   SOK_VectorFloat8Spill,
  78   SOK_VectorFloat4Spill,
  79   SOK_SpillToVSR,
  80   SOK_PairedVecSpill,
  81   SOK_AccumulatorSpill,
  82   SOK_UAccumulatorSpill,
  83   SOK_WAccumulatorSpill,
  84   SOK_SPESpill,
  85   SOK_PairedG8Spill,
  86   SOK_LastOpcodeSpill // This must be last on the enum.
  87 };
  88
  89 // PPC MachineCombiner patterns
  90 enum PPCMachineCombinerPattern : unsigned {
  91   // These are patterns matched by the PowerPC to reassociate FMA chains.
  92   REASSOC_XY_AMM_BMM = MachineCombinerPattern::TARGET_PATTERN_START,
  93   REASSOC_XMM_AMM_BMM,
  94
  95   // These are patterns matched by the PowerPC to reassociate FMA and FSUB to
  96   // reduce register pressure.
  97   REASSOC_XY_BCA,
  98   REASSOC_XY_BAC,
  99
 100 };
 101
 102 // Define list of load and store spill opcodes.
 103 #define NoInstr PPC::INSTRUCTION_LIST_END
 104 #define Pwr8LoadOpcodes                                                        \
 105   {                                                                            \
 106     PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,                    \
 107         PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,    \
 108         PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVLDD,    \
 109         PPC::RESTORE_QUADWORD                                                  \
 110   }
 111
 112 #define Pwr9LoadOpcodes                                                        \
 113   {                                                                            \
 114     PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,                    \
 115         PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64,                \
 116         PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr,         \
 117         NoInstr, NoInstr, PPC::RESTORE_QUADWORD                                \
 118   }
 119
 120 #define Pwr10LoadOpcodes                                                       \
 121   {                                                                            \
 122     PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,                    \
 123         PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64,                \
 124         PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC,       \
 125         PPC::RESTORE_UACC, NoInstr, NoInstr, PPC::RESTORE_QUADWORD             \
 126   }
 127
 128 #define FutureLoadOpcodes                                                      \
 129   {                                                                            \
 130     PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,                    \
 131         PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64,                \
 132         PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC,       \
 133         PPC::RESTORE_UACC, PPC::RESTORE_WACC, NoInstr, PPC::RESTORE_QUADWORD   \
 134   }
 135
 136 #define Pwr8StoreOpcodes                                                       \
 137   {                                                                            \
 138     PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
 139         PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,                    \
 140         PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVSTDD,   \
 141         PPC::SPILL_QUADWORD                                                    \
 142   }
 143
 144 #define Pwr9StoreOpcodes                                                       \
 145   {                                                                            \
 146     PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
 147         PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,                \
 148         PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, NoInstr,       \
 149         PPC::SPILL_QUADWORD                                                    \
 150   }
 151
 152 #define Pwr10StoreOpcodes                                                      \
 153   {                                                                            \
 154     PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
 155         PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,                \
 156         PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC,       \
 157         NoInstr, NoInstr, PPC::SPILL_QUADWORD                                  \
 158   }
 159
 160 #define FutureStoreOpcodes                                                     \
 161   {                                                                            \
 162     PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
 163         PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,                \
 164         PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC,       \
 165         PPC::SPILL_WACC, NoInstr, PPC::SPILL_QUADWORD                          \
 166   }
 167
 168 // Initialize arrays for load and store spill opcodes on supported subtargets.
 169 #define StoreOpcodesForSpill                                                   \
 170   { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes, FutureStoreOpcodes }
 171 #define LoadOpcodesForSpill                                                    \
 172   { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes, FutureLoadOpcodes }
 173
 174 class PPCSubtarget;
 175 class PPCInstrInfo : public PPCGenInstrInfo {
 176   PPCSubtarget &Subtarget;
 177   const PPCRegisterInfo RI;
 178   const unsigned StoreSpillOpcodesArray[4][SOK_LastOpcodeSpill] =
 179       StoreOpcodesForSpill;
 180   const unsigned LoadSpillOpcodesArray[4][SOK_LastOpcodeSpill] =
 181       LoadOpcodesForSpill;
 182
 183   void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
 184                            int FrameIdx, const TargetRegisterClass *RC,
 185                            SmallVectorImpl<MachineInstr *> &NewMIs) const;
 186   void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
 187                             unsigned DestReg, int FrameIdx,
 188                             const TargetRegisterClass *RC,
 189                             SmallVectorImpl<MachineInstr *> &NewMIs) const;
 190
 191   // Replace the instruction with single LI if possible. \p DefMI must be LI or
 192   // LI8.
 193   bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
 194                     unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
 195   // If the inst is imm-form and its register operand is produced by a ADDI, put
 196   // the imm into the inst directly and remove the ADDI if possible.
 197   bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
 198                                      unsigned OpNoForForwarding) const;
 199   // If the inst is x-form and has imm-form and one of its operand is produced
 200   // by a LI, put the imm into the inst directly and remove the LI if possible.
 201   bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
 202                                  unsigned ConstantOpNo,
 203                                  MachineInstr &DefMI) const;
 204   // If the inst is x-form and has imm-form and one of its operand is produced
 205   // by an add-immediate, try to transform it when possible.
 206   bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
 207                                   unsigned ConstantOpNo, MachineInstr &DefMI,
 208                                   bool KillDefMI) const;
 209   // Try to find that, if the instruction 'MI' contains any operand that
 210   // could be forwarded from some inst that feeds it. If yes, return the
 211   // Def of that operand. And OpNoForForwarding is the operand index in
 212   // the 'MI' for that 'Def'. If we see another use of this Def between
 213   // the Def and the MI, SeenIntermediateUse becomes 'true'.
 214   MachineInstr *getForwardingDefMI(MachineInstr &MI,
 215                                    unsigned &OpNoForForwarding,
 216                                    bool &SeenIntermediateUse) const;
 217
 218   // Can the user MI have it's source at index \p OpNoForForwarding
 219   // forwarded from an add-immediate that feeds it?
 220   bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
 221                                    unsigned OpNoForForwarding) const;
 222   bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
 223                                    const ImmInstrInfo &III,
 224                                    MachineOperand *&ImmMO,
 225                                    MachineOperand *&RegMO) const;
 226   bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
 227                                  const MachineInstr &DefMI,
 228                                  const ImmInstrInfo &III,
 229                                  int64_t &Imm,
 230                                  int64_t BaseImm = 0) const;
 231   bool isRegElgibleForForwarding(const MachineOperand &RegMO,
 232                                  const MachineInstr &DefMI,
 233                                  const MachineInstr &MI, bool KillDefMI,
 234                                  bool &IsFwdFeederRegKilled,
 235                                  bool &SeenIntermediateUse) const;
 236   unsigned getSpillTarget() const;
 237   ArrayRef<unsigned> getStoreOpcodesForSpillArray() const;
 238   ArrayRef<unsigned> getLoadOpcodesForSpillArray() const;
 239   unsigned getSpillIndex(const TargetRegisterClass *RC) const;
 240   int16_t getFMAOpIdxInfo(unsigned Opcode) const;
 241   void reassociateFMA(MachineInstr &Root, unsigned Pattern,
 242                       SmallVectorImpl<MachineInstr *> &InsInstrs,
 243                       SmallVectorImpl<MachineInstr *> &DelInstrs,
 244                       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
 245   Register
 246   generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty,
 247                           SmallVectorImpl<MachineInstr *> &InsInstrs) const;
 248   virtual void anchor();
 249
 250 protected:
 251   /// Commutes the operands in the given instruction.
 252   /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
 253   ///
 254   /// Do not call this method for a non-commutable instruction or for
 255   /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
 256   /// Even though the instruction is commutable, the method may still
 257   /// fail to commute the operands, null pointer is returned in such cases.
 258   ///
 259   /// For example, we can commute rlwimi instructions, but only if the
 260   /// rotate amt is zero.  We also have to munge the immediates a bit.
 261   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
 262                                        unsigned OpIdx1,
 263                                        unsigned OpIdx2) const override;
 264
 265 public:
 266   explicit PPCInstrInfo(PPCSubtarget &STI);
 267
 268   bool isLoadFromConstantPool(MachineInstr *I) const;
 269   const Constant *getConstantFromConstantPool(MachineInstr *I) const;
 270
 271   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
 272   /// such, whenever a client has an instance of instruction info, it should
 273   /// always be able to get register info as well (through this method).
 274   ///
 275   const PPCRegisterInfo &getRegisterInfo() const { return RI; }
 276
 277   bool isXFormMemOp(unsigned Opcode) const {
 278     return get(Opcode).TSFlags & PPCII::XFormMemOp;
 279   }
 280   bool isPrefixed(unsigned Opcode) const {
 281     return get(Opcode).TSFlags & PPCII::Prefixed;
 282   }
 283   bool isSExt32To64(unsigned Opcode) const {
 284     return get(Opcode).TSFlags & PPCII::SExt32To64;
 285   }
 286   bool isZExt32To64(unsigned Opcode) const {
 287     return get(Opcode).TSFlags & PPCII::ZExt32To64;
 288   }
 289   bool isMemriOp(unsigned Opcode) const {
 290     return get(Opcode).TSFlags & PPCII::MemriOp;
 291   }
 292
 293   static bool isSameClassPhysRegCopy(unsigned Opcode) {
 294     unsigned CopyOpcodes[] = {PPC::OR,        PPC::OR8,   PPC::FMR,
 295                               PPC::VOR,       PPC::XXLOR, PPC::XXLORf,
 296                               PPC::XSCPSGNDP, PPC::MCRF,  PPC::CROR,
 297                               PPC::EVOR,      -1U};
 298     for (int i = 0; CopyOpcodes[i] != -1U; i++)
 299       if (Opcode == CopyOpcodes[i])
 300         return true;
 301     return false;
 302   }
 303
 304   static bool hasPCRelFlag(unsigned TF) {
 305     return TF == PPCII::MO_PCREL_FLAG || TF == PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
 306            TF == PPCII::MO_GOT_TLSLD_PCREL_FLAG ||
 307            TF == PPCII::MO_GOT_TPREL_PCREL_FLAG ||
 308            TF == PPCII::MO_TPREL_PCREL_FLAG || TF == PPCII::MO_TLS_PCREL_FLAG ||
 309            TF == PPCII::MO_GOT_PCREL_FLAG;
 310   }
 311
 312   static bool hasGOTFlag(unsigned TF) {
 313     return TF == PPCII::MO_GOT_FLAG || TF == PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
 314            TF == PPCII::MO_GOT_TLSLD_PCREL_FLAG ||
 315            TF == PPCII::MO_GOT_TPREL_PCREL_FLAG ||
 316            TF == PPCII::MO_GOT_PCREL_FLAG;
 317   }
 318
 319   static bool hasTLSFlag(unsigned TF) {
 320     return TF == PPCII::MO_TLSGD_FLAG || TF == PPCII::MO_TPREL_FLAG ||
 321            TF == PPCII::MO_TLSLD_FLAG || TF == PPCII::MO_TLSGDM_FLAG ||
 322            TF == PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
 323            TF == PPCII::MO_GOT_TLSLD_PCREL_FLAG ||
 324            TF == PPCII::MO_GOT_TPREL_PCREL_FLAG || TF == PPCII::MO_TPREL_LO ||
 325            TF == PPCII::MO_TPREL_HA || TF == PPCII::MO_DTPREL_LO ||
 326            TF == PPCII::MO_TLSLD_LO || TF == PPCII::MO_TLS ||
 327            TF == PPCII::MO_TPREL_PCREL_FLAG || TF == PPCII::MO_TLS_PCREL_FLAG;
 328   }
 329
 330   ScheduleHazardRecognizer *
 331   CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
 332                                const ScheduleDAG *DAG) const override;
 333   ScheduleHazardRecognizer *
 334   CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
 335                                      const ScheduleDAG *DAG) const override;
 336
 337   unsigned getInstrLatency(const InstrItineraryData *ItinData,
 338                            const MachineInstr &MI,
 339                            unsigned *PredCost = nullptr) const override;
 340
 341   std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
 342                                             const MachineInstr &DefMI,
 343                                             unsigned DefIdx,
 344                                             const MachineInstr &UseMI,
 345                                             unsigned UseIdx) const override;
 346   std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
 347                                             SDNode *DefNode, unsigned DefIdx,
 348                                             SDNode *UseNode,
 349                                             unsigned UseIdx) const override {
 350     return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
 351                                               UseNode, UseIdx);
 352   }
 353
 354   bool hasLowDefLatency(const TargetSchedModel &SchedModel,
 355                         const MachineInstr &DefMI,
 356                         unsigned DefIdx) const override {
 357     // Machine LICM should hoist all instructions in low-register-pressure
 358     // situations; none are sufficiently free to justify leaving in a loop
 359     // body.
 360     return false;
 361   }
 362
 363   bool useMachineCombiner() const override {
 364     return true;
 365   }
 366
 367   /// When getMachineCombinerPatterns() finds patterns, this function generates
 368   /// the instructions that could replace the original code sequence
 369   void genAlternativeCodeSequence(
 370       MachineInstr &Root, unsigned Pattern,
 371       SmallVectorImpl<MachineInstr *> &InsInstrs,
 372       SmallVectorImpl<MachineInstr *> &DelInstrs,
 373       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
 374
 375   /// Return true when there is potentially a faster code sequence for a fma
 376   /// chain ending in \p Root. All potential patterns are output in the \p
 377   /// P array.
 378   bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns,
 379                       bool DoRegPressureReduce) const;
 380
 381   CombinerObjective getCombinerObjective(unsigned Pattern) const override;
 382
 383   /// Return true when there is potentially a faster code sequence
 384   /// for an instruction chain ending in <Root>. All potential patterns are
 385   /// output in the <Pattern> array.
 386   bool getMachineCombinerPatterns(MachineInstr &Root,
 387                                   SmallVectorImpl<unsigned> &Patterns,
 388                                   bool DoRegPressureReduce) const override;
 389
 390   /// On PowerPC, we leverage machine combiner pass to reduce register pressure
 391   /// when the register pressure is high for one BB.
 392   /// Return true if register pressure for \p MBB is high and ABI is supported
 393   /// to reduce register pressure. Otherwise return false.
 394   bool shouldReduceRegisterPressure(
 395       const MachineBasicBlock *MBB,
 396       const RegisterClassInfo *RegClassInfo) const override;
 397
 398   /// Fixup the placeholders we put in genAlternativeCodeSequence() for
 399   /// MachineCombiner.
 400   void
 401   finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern,
 402                     SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
 403
 404   bool isAssociativeAndCommutative(const MachineInstr &Inst,
 405                                    bool Invert) const override;
 406
 407   /// On PowerPC, we try to reassociate FMA chain which will increase
 408   /// instruction size. Set extension resource length limit to 1 for edge case.
 409   /// Resource Length is calculated by scaled resource usage in getCycles().
 410   /// Because of the division in getCycles(), it returns different cycles due to
 411   /// legacy scaled resource usage. So new resource length may be same with
 412   /// legacy or 1 bigger than legacy.
 413   /// We need to execlude the 1 bigger case even the resource length is not
 414   /// perserved for more FMA chain reassociations on PowerPC.
 415   int getExtendResourceLenLimit() const override { return 1; }
 416
 417   // PowerPC specific version of setSpecialOperandAttr that copies Flags to MI
 418   // and clears nuw, nsw, and exact flags.
 419   using TargetInstrInfo::setSpecialOperandAttr;
 420   void setSpecialOperandAttr(MachineInstr &MI, uint32_t Flags) const;
 421
 422   bool isCoalescableExtInstr(const MachineInstr &MI,
 423                              Register &SrcReg, Register &DstReg,
 424                              unsigned &SubIdx) const override;
 425   Register isLoadFromStackSlot(const MachineInstr &MI,
 426                                int &FrameIndex) const override;
 427   bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
 428   Register isStoreToStackSlot(const MachineInstr &MI,
 429                               int &FrameIndex) const override;
 430
 431   bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
 432                              unsigned &SrcOpIdx2) const override;
 433
 434   void insertNoop(MachineBasicBlock &MBB,
 435                   MachineBasicBlock::iterator MI) const override;
 436
 437
 438   // Branch analysis.
 439   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 440                      MachineBasicBlock *&FBB,
 441                      SmallVectorImpl<MachineOperand> &Cond,
 442                      bool AllowModify) const override;
 443   unsigned removeBranch(MachineBasicBlock &MBB,
 444                         int *BytesRemoved = nullptr) const override;
 445   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 446                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
 447                         const DebugLoc &DL,
 448                         int *BytesAdded = nullptr) const override;
 449
 450   // Select analysis.
 451   bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
 452                        Register, Register, Register, int &, int &,
 453                        int &) const override;
 454   void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
 455                     const DebugLoc &DL, Register DstReg,
 456                     ArrayRef<MachineOperand> Cond, Register TrueReg,
 457                     Register FalseReg) const override;
 458
 459   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 460                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
 461                    bool KillSrc, bool RenamableDest = false,
 462                    bool RenamableSrc = false) const override;
 463
 464   void storeRegToStackSlot(MachineBasicBlock &MBB,
 465                            MachineBasicBlock::iterator MBBI, Register SrcReg,
 466                            bool isKill, int FrameIndex,
 467                            const TargetRegisterClass *RC,
 468                            const TargetRegisterInfo *TRI,
 469                            Register VReg) const override;
 470
 471   // Emits a register spill without updating the register class for vector
 472   // registers. This ensures that when we spill a vector register the
 473   // element order in the register is the same as it was in memory.
 474   void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB,
 475                                 MachineBasicBlock::iterator MBBI,
 476                                 unsigned SrcReg, bool isKill, int FrameIndex,
 477                                 const TargetRegisterClass *RC,
 478                                 const TargetRegisterInfo *TRI) const;
 479
 480   void loadRegFromStackSlot(MachineBasicBlock &MBB,
 481                             MachineBasicBlock::iterator MBBI, Register DestReg,
 482                             int FrameIndex, const TargetRegisterClass *RC,
 483                             const TargetRegisterInfo *TRI,
 484                             Register VReg) const override;
 485
 486   // Emits a register reload without updating the register class for vector
 487   // registers. This ensures that when we reload a vector register the
 488   // element order in the register is the same as it was in memory.
 489   void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB,
 490                                  MachineBasicBlock::iterator MBBI,
 491                                  unsigned DestReg, int FrameIndex,
 492                                  const TargetRegisterClass *RC,
 493                                  const TargetRegisterInfo *TRI) const;
 494
 495   unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const;
 496
 497   unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const;
 498
 499   bool
 500   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 501
 502   bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
 503                      MachineRegisterInfo *MRI) const override;
 504
 505   bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
 506                          Register Reg) const;
 507
 508   // If conversion by predication (only supported by some branch instructions).
 509   // All of the profitability checks always return true; it is always
 510   // profitable to use the predicated branches.
 511   bool isProfitableToIfCvt(MachineBasicBlock &MBB,
 512                           unsigned NumCycles, unsigned ExtraPredCycles,
 513                           BranchProbability Probability) const override {
 514     return true;
 515   }
 516
 517   bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
 518                            unsigned NumT, unsigned ExtraT,
 519                            MachineBasicBlock &FMBB,
 520                            unsigned NumF, unsigned ExtraF,
 521                            BranchProbability Probability) const override;
 522
 523   bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
 524                                  BranchProbability Probability) const override {
 525     return true;
 526   }
 527
 528   bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
 529                                  MachineBasicBlock &FMBB) const override {
 530     return false;
 531   }
 532
 533   // Predication support.
 534   bool isPredicated(const MachineInstr &MI) const override;
 535
 536   bool isSchedulingBoundary(const MachineInstr &MI,
 537                             const MachineBasicBlock *MBB,
 538                             const MachineFunction &MF) const override;
 539
 540   bool PredicateInstruction(MachineInstr &MI,
 541                             ArrayRef<MachineOperand> Pred) const override;
 542
 543   bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
 544                          ArrayRef<MachineOperand> Pred2) const override;
 545
 546   bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
 547                          bool SkipDead) const override;
 548
 549   // Comparison optimization.
 550
 551   bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
 552                       Register &SrcReg2, int64_t &Mask,
 553                       int64_t &Value) const override;
 554
 555   bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
 556                             Register SrcReg2, int64_t Mask, int64_t Value,
 557                             const MachineRegisterInfo *MRI) const override;
 558
 559
 560   /// Return true if get the base operand, byte offset of an instruction and
 561   /// the memory width. Width is the size of memory that is being
 562   /// loaded/stored (e.g. 1, 2, 4, 8).
 563   bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
 564                                     const MachineOperand *&BaseOp,
 565                                     int64_t &Offset, LocationSize &Width,
 566                                     const TargetRegisterInfo *TRI) const;
 567
 568   bool optimizeCmpPostRA(MachineInstr &MI) const;
 569
 570   /// Get the base operand and byte offset of an instruction that reads/writes
 571   /// memory.
 572   bool getMemOperandsWithOffsetWidth(
 573       const MachineInstr &LdSt,
 574       SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
 575       bool &OffsetIsScalable, LocationSize &Width,
 576       const TargetRegisterInfo *TRI) const override;
 577
 578   /// Returns true if the two given memory operations should be scheduled
 579   /// adjacent.
 580   bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
 581                            int64_t Offset1, bool OffsetIsScalable1,
 582                            ArrayRef<const MachineOperand *> BaseOps2,
 583                            int64_t Offset2, bool OffsetIsScalable2,
 584                            unsigned ClusterSize,
 585                            unsigned NumBytes) const override;
 586
 587   /// Return true if two MIs access different memory addresses and false
 588   /// otherwise
 589   bool
 590   areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
 591                                   const MachineInstr &MIb) const override;
 592
 593   /// GetInstSize - Return the number of bytes of code the specified
 594   /// instruction may be.  This returns the maximum number of bytes.
 595   ///
 596   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
 597
 598   MCInst getNop() const override;
 599
 600   std::pair<unsigned, unsigned>
 601   decomposeMachineOperandsTargetFlags(unsigned TF) const override;
 602
 603   ArrayRef<std::pair<unsigned, const char *>>
 604   getSerializableDirectMachineOperandTargetFlags() const override;
 605
 606   // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
 607   bool expandVSXMemPseudo(MachineInstr &MI) const;
 608
 609   // Lower pseudo instructions after register allocation.
 610   bool expandPostRAPseudo(MachineInstr &MI) const override;
 611
 612   const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
 613   static int getRecordFormOpcode(unsigned Opcode);
 614
 615   bool isTOCSaveMI(const MachineInstr &MI) const;
 616
 617   std::pair<bool, bool>
 618   isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth,
 619                        const MachineRegisterInfo *MRI) const;
 620
 621   // Return true if the register is sign-extended from 32 to 64 bits.
 622   bool isSignExtended(const unsigned Reg,
 623                       const MachineRegisterInfo *MRI) const {
 624     return isSignOrZeroExtended(Reg, 0, MRI).first;
 625   }
 626
 627   // Return true if the register is zero-extended from 32 to 64 bits.
 628   bool isZeroExtended(const unsigned Reg,
 629                       const MachineRegisterInfo *MRI) const {
 630     return isSignOrZeroExtended(Reg, 0, MRI).second;
 631   }
 632   void promoteInstr32To64ForElimEXTSW(const Register &Reg,
 633                                       MachineRegisterInfo *MRI,
 634                                       unsigned BinOpDepth,
 635                                       LiveVariables *LV) const;
 636
 637   bool convertToImmediateForm(MachineInstr &MI,
 638                               SmallSet<Register, 4> &RegsToUpdate,
 639                               MachineInstr **KilledDef = nullptr) const;
 640   bool foldFrameOffset(MachineInstr &MI) const;
 641   bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const;
 642   bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
 643   bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const;
 644   bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg,
 645                                     unsigned &XFormOpcode,
 646                                     int64_t &OffsetOfImmInstr,
 647                                     ImmInstrInfo &III) const;
 648   bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
 649                              MachineInstr *&ADDIMI, int64_t &OffsetAddi,
 650                              int64_t OffsetImm) const;
 651
 652   void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
 653   void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
 654                                   int64_t Imm) const;
 655
 656   bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
 657                        bool PostRA) const;
 658
 659   // In PostRA phase, try to find instruction defines \p Reg before \p MI.
 660   // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
 661   MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI,
 662                                bool &SeenIntermediateUse) const;
 663
 664   // Materialize immediate after RA.
 665   void materializeImmPostRA(MachineBasicBlock &MBB,
 666                             MachineBasicBlock::iterator MBBI,
 667                             const DebugLoc &DL, Register Reg,
 668                             int64_t Imm) const;
 669
 670   /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
 671   bool isBDNZ(unsigned Opcode) const;
 672
 673   /// Find the hardware loop instruction used to set-up the specified loop.
 674   /// On PPC, we have two instructions used to set-up the hardware loop
 675   /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8)
 676   /// instructions to indicate the end of a loop.
 677   MachineInstr *
 678   findLoopInstr(MachineBasicBlock &PreHeader,
 679                 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
 680
 681   /// Analyze loop L, which must be a single-basic-block loop, and if the
 682   /// conditions can be understood enough produce a PipelinerLoopInfo object.
 683   std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
 684   analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
 685 };
 686
 687 }
 688
 689 #endif