llvm/lib/Target/RISCV/CMakeLists.txt

   1 add_llvm_component_group(RISCV)
   2
   3 set(LLVM_TARGET_DEFINITIONS RISCV.td)
   4
   5 tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
   6 tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
   7 tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
   8 tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
   9 tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
  10 tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
  11 tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
  12 tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
  13 tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
  14 tablegen(LLVM RISCVGenRegisterBank.inc -gen-register-bank)
  15 tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
  16 tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)
  17 tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
  18
  19 set(LLVM_TARGET_DEFINITIONS RISCVGISel.td)
  20 tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
  21 tablegen(LLVM RISCVGenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
  22               -combiners="RISCVO0PreLegalizerCombiner")
  23 tablegen(LLVM RISCVGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
  24               -combiners="RISCVPreLegalizerCombiner")
  25 tablegen(LLVM RISCVGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
  26               -combiners="RISCVPostLegalizerCombiner")
  27
  28 add_public_tablegen_target(RISCVCommonTableGen)
  29
  30 add_llvm_target(RISCVCodeGen
  31   RISCVAsmPrinter.cpp
  32   RISCVCallingConv.cpp
  33   RISCVCodeGenPrepare.cpp
  34   RISCVConstantPoolValue.cpp
  35   RISCVDeadRegisterDefinitions.cpp
  36   RISCVMakeCompressible.cpp
  37   RISCVExpandAtomicPseudoInsts.cpp
  38   RISCVExpandPseudoInsts.cpp
  39   RISCVFrameLowering.cpp
  40   RISCVGatherScatterLowering.cpp
  41   RISCVIndirectBranchTracking.cpp
  42   RISCVInsertVSETVLI.cpp
  43   RISCVInsertReadWriteCSR.cpp
  44   RISCVInsertWriteVXRM.cpp
  45   RISCVInstrInfo.cpp
  46   RISCVISelDAGToDAG.cpp
  47   RISCVISelLowering.cpp
  48   RISCVLandingPadSetup.cpp
  49   RISCVMachineFunctionInfo.cpp
  50   RISCVMergeBaseOffset.cpp
  51   RISCVOptWInstrs.cpp
  52   RISCVPostRAExpandPseudoInsts.cpp
  53   RISCVRedundantCopyElimination.cpp
  54   RISCVMoveMerger.cpp
  55   RISCVPushPopOptimizer.cpp
  56   RISCVRegisterInfo.cpp
  57   RISCVSelectionDAGInfo.cpp
  58   RISCVSubtarget.cpp
  59   RISCVTargetMachine.cpp
  60   RISCVTargetObjectFile.cpp
  61   RISCVTargetTransformInfo.cpp
  62   RISCVVectorMaskDAGMutation.cpp
  63   RISCVVectorPeephole.cpp
  64   RISCVVLOptimizer.cpp
  65   RISCVZacasABIFix.cpp
  66   GISel/RISCVCallLowering.cpp
  67   GISel/RISCVInstructionSelector.cpp
  68   GISel/RISCVLegalizerInfo.cpp
  69   GISel/RISCVPostLegalizerCombiner.cpp
  70   GISel/RISCVO0PreLegalizerCombiner.cpp
  71   GISel/RISCVPreLegalizerCombiner.cpp
  72   GISel/RISCVRegisterBankInfo.cpp
  73
  74   LINK_COMPONENTS
  75   Analysis
  76   AsmPrinter
  77   CodeGen
  78   CodeGenTypes
  79   Core
  80   GlobalISel
  81   IPO
  82   MC
  83   RISCVDesc
  84   RISCVInfo
  85   Scalar
  86   SelectionDAG
  87   Support
  88   Target
  89   TargetParser
  90   TransformUtils
  91   Vectorize
  92
  93   ADD_TO_COMPONENT
  94   RISCV
  95   )
  96
  97 add_subdirectory(AsmParser)
  98 add_subdirectory(Disassembler)
  99 add_subdirectory(MCTargetDesc)
 100 add_subdirectory(MCA)
 101 add_subdirectory(TargetInfo)