llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

   1 //===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains small standalone enum definitions for the RISC-V target
  10 // useful for the compiler back-end and the MC libraries.
  11 //
  12 //===----------------------------------------------------------------------===//
  13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
  14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
  15
  16 #include "MCTargetDesc/RISCVMCTargetDesc.h"
  17 #include "llvm/ADT/APFloat.h"
  18 #include "llvm/ADT/APInt.h"
  19 #include "llvm/ADT/StringRef.h"
  20 #include "llvm/ADT/StringSwitch.h"
  21 #include "llvm/MC/MCInstrDesc.h"
  22 #include "llvm/TargetParser/RISCVISAInfo.h"
  23 #include "llvm/TargetParser/RISCVTargetParser.h"
  24 #include "llvm/TargetParser/SubtargetFeature.h"
  25
  26 namespace llvm {
  27
  28 // RISCVII - This namespace holds all of the target specific flags that
  29 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
  30 namespace RISCVII {
  31 enum {
  32   InstFormatPseudo = 0,
  33   InstFormatR = 1,
  34   InstFormatR4 = 2,
  35   InstFormatI = 3,
  36   InstFormatS = 4,
  37   InstFormatB = 5,
  38   InstFormatU = 6,
  39   InstFormatJ = 7,
  40   InstFormatCR = 8,
  41   InstFormatCI = 9,
  42   InstFormatCSS = 10,
  43   InstFormatCIW = 11,
  44   InstFormatCL = 12,
  45   InstFormatCS = 13,
  46   InstFormatCA = 14,
  47   InstFormatCB = 15,
  48   InstFormatCJ = 16,
  49   InstFormatCU = 17,
  50   InstFormatCLB = 18,
  51   InstFormatCLH = 19,
  52   InstFormatCSB = 20,
  53   InstFormatCSH = 21,
  54   InstFormatOther = 22,
  55
  56   InstFormatMask = 31,
  57   InstFormatShift = 0,
  58
  59   ConstraintShift = InstFormatShift + 5,
  60   VS2Constraint = 0b001 << ConstraintShift,
  61   VS1Constraint = 0b010 << ConstraintShift,
  62   VMConstraint = 0b100 << ConstraintShift,
  63   ConstraintMask = 0b111 << ConstraintShift,
  64
  65   VLMulShift = ConstraintShift + 3,
  66   VLMulMask = 0b111 << VLMulShift,
  67
  68   // Force a tail agnostic policy even this instruction has a tied destination.
  69   ForceTailAgnosticShift = VLMulShift + 3,
  70   ForceTailAgnosticMask = 1 << ForceTailAgnosticShift,
  71
  72   // Is this a _TIED vector pseudo instruction. For these instructions we
  73   // shouldn't skip the tied operand when converting to MC instructions.
  74   IsTiedPseudoShift = ForceTailAgnosticShift + 1,
  75   IsTiedPseudoMask = 1 << IsTiedPseudoShift,
  76
  77   // Does this instruction have a SEW operand. It will be the last explicit
  78   // operand unless there is a vector policy operand. Used by RVV Pseudos.
  79   HasSEWOpShift = IsTiedPseudoShift + 1,
  80   HasSEWOpMask = 1 << HasSEWOpShift,
  81
  82   // Does this instruction have a VL operand. It will be the second to last
  83   // explicit operand unless there is a vector policy operand. Used by RVV
  84   // Pseudos.
  85   HasVLOpShift = HasSEWOpShift + 1,
  86   HasVLOpMask = 1 << HasVLOpShift,
  87
  88   // Does this instruction have a vector policy operand. It will be the last
  89   // explicit operand. Used by RVV Pseudos.
  90   HasVecPolicyOpShift = HasVLOpShift + 1,
  91   HasVecPolicyOpMask = 1 << HasVecPolicyOpShift,
  92
  93   // Is this instruction a vector widening reduction instruction. Used by RVV
  94   // Pseudos.
  95   IsRVVWideningReductionShift = HasVecPolicyOpShift + 1,
  96   IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift,
  97
  98   // Does this instruction care about mask policy. If it is not, the mask policy
  99   // could be either agnostic or undisturbed. For example, unmasked, store, and
 100   // reduction operations result would not be affected by mask policy, so
 101   // compiler has free to select either one.
 102   UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,
 103   UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,
 104
 105   // Indicates that the result can be considered sign extended from bit 31. Some
 106   // instructions with this flag aren't W instructions, but are either sign
 107   // extended from a smaller size, always outputs a small integer, or put zeros
 108   // in bits 63:31. Used by the SExtWRemoval pass.
 109   IsSignExtendingOpWShift = UsesMaskPolicyShift + 1,
 110   IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift,
 111
 112   HasRoundModeOpShift = IsSignExtendingOpWShift + 1,
 113   HasRoundModeOpMask = 1 << HasRoundModeOpShift,
 114
 115   UsesVXRMShift = HasRoundModeOpShift + 1,
 116   UsesVXRMMask = 1 << UsesVXRMShift,
 117
 118   // Indicates whether these instructions can partially overlap between source
 119   // registers and destination registers according to the vector spec.
 120   // 0 -> not a vector pseudo
 121   // 1 -> default value for vector pseudos. not widening or narrowing.
 122   // 2 -> narrowing case
 123   // 3 -> widening case
 124   TargetOverlapConstraintTypeShift = UsesVXRMShift + 1,
 125   TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
 126
 127   ElementsDependOnVLShift = TargetOverlapConstraintTypeShift + 2,
 128   ElementsDependOnVLMask = 1ULL << ElementsDependOnVLShift,
 129
 130   ElementsDependOnMaskShift = ElementsDependOnVLShift + 1,
 131   ElementsDependOnMaskMask = 1ULL << ElementsDependOnMaskShift,
 132
 133   // Indicates the EEW of a vector instruction's destination operand.
 134   // 0 -> 1
 135   // 1 -> SEW
 136   // 2 -> SEW * 2
 137   // 3 -> SEW * 4
 138   DestEEWShift = ElementsDependOnMaskShift + 1,
 139   DestEEWMask = 3ULL << DestEEWShift,
 140 };
 141
 142 // Helper functions to read TSFlags.
 143 /// \returns the format of the instruction.
 144 static inline unsigned getFormat(uint64_t TSFlags) {
 145   return (TSFlags & InstFormatMask) >> InstFormatShift;
 146 }
 147 /// \returns the LMUL for the instruction.
 148 static inline VLMUL getLMul(uint64_t TSFlags) {
 149   return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
 150 }
 151 /// \returns true if tail agnostic is enforced for the instruction.
 152 static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
 153   return TSFlags & ForceTailAgnosticMask;
 154 }
 155 /// \returns true if this a _TIED pseudo.
 156 static inline bool isTiedPseudo(uint64_t TSFlags) {
 157   return TSFlags & IsTiedPseudoMask;
 158 }
 159 /// \returns true if there is a SEW operand for the instruction.
 160 static inline bool hasSEWOp(uint64_t TSFlags) {
 161   return TSFlags & HasSEWOpMask;
 162 }
 163 /// \returns true if there is a VL operand for the instruction.
 164 static inline bool hasVLOp(uint64_t TSFlags) {
 165   return TSFlags & HasVLOpMask;
 166 }
 167 /// \returns true if there is a vector policy operand for this instruction.
 168 static inline bool hasVecPolicyOp(uint64_t TSFlags) {
 169   return TSFlags & HasVecPolicyOpMask;
 170 }
 171 /// \returns true if it is a vector widening reduction instruction.
 172 static inline bool isRVVWideningReduction(uint64_t TSFlags) {
 173   return TSFlags & IsRVVWideningReductionMask;
 174 }
 175 /// \returns true if mask policy is valid for the instruction.
 176 static inline bool usesMaskPolicy(uint64_t TSFlags) {
 177   return TSFlags & UsesMaskPolicyMask;
 178 }
 179
 180 /// \returns true if there is a rounding mode operand for this instruction
 181 static inline bool hasRoundModeOp(uint64_t TSFlags) {
 182   return TSFlags & HasRoundModeOpMask;
 183 }
 184
 185 /// \returns true if this instruction uses vxrm
 186 static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
 187
 188 /// \returns true if the elements in the body are affected by VL,
 189 /// e.g. vslide1down.vx/vredsum.vs/viota.m
 190 static inline bool elementsDependOnVL(uint64_t TSFlags) {
 191   return TSFlags & ElementsDependOnVLMask;
 192 }
 193
 194 /// \returns true if the elements in the body are affected by the mask,
 195 /// e.g. vredsum.vs/viota.m
 196 static inline bool elementsDependOnMask(uint64_t TSFlags) {
 197   return TSFlags & ElementsDependOnMaskMask;
 198 }
 199
 200 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
 201   const uint64_t TSFlags = Desc.TSFlags;
 202   // This method is only called if we expect to have a VL operand, and all
 203   // instructions with VL also have SEW.
 204   assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
 205   unsigned Offset = 2;
 206   if (hasVecPolicyOp(TSFlags))
 207     Offset = 3;
 208   return Desc.getNumOperands() - Offset;
 209 }
 210
 211 static inline unsigned getTailExpandUseRegNo(const FeatureBitset &FeatureBits) {
 212   // For Zicfilp, PseudoTAIL should be expanded to a software guarded branch.
 213   // It means to use t2(x7) as rs1 of JALR to expand PseudoTAIL.
 214   return FeatureBits[RISCV::FeatureStdExtZicfilp] ? RISCV::X7 : RISCV::X6;
 215 }
 216
 217 static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
 218   const uint64_t TSFlags = Desc.TSFlags;
 219   assert(hasSEWOp(TSFlags));
 220   unsigned Offset = 1;
 221   if (hasVecPolicyOp(TSFlags))
 222     Offset = 2;
 223   return Desc.getNumOperands() - Offset;
 224 }
 225
 226 static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
 227   assert(hasVecPolicyOp(Desc.TSFlags));
 228   return Desc.getNumOperands() - 1;
 229 }
 230
 231 /// \returns  the index to the rounding mode immediate value if any, otherwise
 232 /// returns -1.
 233 static inline int getFRMOpNum(const MCInstrDesc &Desc) {
 234   const uint64_t TSFlags = Desc.TSFlags;
 235   if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
 236     return -1;
 237
 238   // The operand order
 239   // --------------------------------------
 240   // | n-1 (if any)   | n-2  | n-3 | n-4 |
 241   // | policy         | sew  | vl  | frm |
 242   // --------------------------------------
 243   return getVLOpNum(Desc) - 1;
 244 }
 245
 246 /// \returns  the index to the rounding mode immediate value if any, otherwise
 247 /// returns -1.
 248 static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
 249   const uint64_t TSFlags = Desc.TSFlags;
 250   if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
 251     return -1;
 252   // The operand order
 253   // --------------------------------------
 254   // | n-1 (if any)   | n-2  | n-3 | n-4  |
 255   // | policy         | sew  | vl  | vxrm |
 256   // --------------------------------------
 257   return getVLOpNum(Desc) - 1;
 258 }
 259
 260 // Is the first def operand tied to the first use operand. This is true for
 261 // vector pseudo instructions that have a merge operand for tail/mask
 262 // undisturbed. It's also true for vector FMA instructions where one of the
 263 // operands is also the destination register.
 264 static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
 265   return Desc.getNumDefs() < Desc.getNumOperands() &&
 266          Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0;
 267 }
 268
 269 // RISC-V Specific Machine Operand Flags
 270 enum {
 271   MO_None = 0,
 272   MO_CALL = 1,
 273   MO_LO = 3,
 274   MO_HI = 4,
 275   MO_PCREL_LO = 5,
 276   MO_PCREL_HI = 6,
 277   MO_GOT_HI = 7,
 278   MO_TPREL_LO = 8,
 279   MO_TPREL_HI = 9,
 280   MO_TPREL_ADD = 10,
 281   MO_TLS_GOT_HI = 11,
 282   MO_TLS_GD_HI = 12,
 283   MO_TLSDESC_HI = 13,
 284   MO_TLSDESC_LOAD_LO = 14,
 285   MO_TLSDESC_ADD_LO = 15,
 286   MO_TLSDESC_CALL = 16,
 287
 288   // Used to differentiate between target-specific "direct" flags and "bitmask"
 289   // flags. A machine operand can only have one "direct" flag, but can have
 290   // multiple "bitmask" flags.
 291   MO_DIRECT_FLAG_MASK = 31
 292 };
 293 } // namespace RISCVII
 294
 295 namespace RISCVOp {
 296 enum OperandType : unsigned {
 297   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
 298   OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM,
 299   OPERAND_UIMM2,
 300   OPERAND_UIMM2_LSB0,
 301   OPERAND_UIMM3,
 302   OPERAND_UIMM4,
 303   OPERAND_UIMM5,
 304   OPERAND_UIMM5_NONZERO,
 305   OPERAND_UIMM5_GT3,
 306   OPERAND_UIMM5_LSB0,
 307   OPERAND_UIMM6,
 308   OPERAND_UIMM6_LSB0,
 309   OPERAND_UIMM7,
 310   OPERAND_UIMM7_LSB00,
 311   OPERAND_UIMM8_LSB00,
 312   OPERAND_UIMM8,
 313   OPERAND_UIMM8_LSB000,
 314   OPERAND_UIMM8_GE32,
 315   OPERAND_UIMM9_LSB000,
 316   OPERAND_UIMM10_LSB00_NONZERO,
 317   OPERAND_UIMM11,
 318   OPERAND_UIMM12,
 319   OPERAND_UIMM16,
 320   OPERAND_UIMM20,
 321   OPERAND_UIMMLOG2XLEN,
 322   OPERAND_UIMMLOG2XLEN_NONZERO,
 323   OPERAND_UIMM32,
 324   OPERAND_UIMM48,
 325   OPERAND_UIMM64,
 326   OPERAND_ZERO,
 327   OPERAND_SIMM5,
 328   OPERAND_SIMM5_PLUS1,
 329   OPERAND_SIMM6,
 330   OPERAND_SIMM6_NONZERO,
 331   OPERAND_SIMM10_LSB0000_NONZERO,
 332   OPERAND_SIMM12,
 333   OPERAND_SIMM12_LSB00000,
 334   OPERAND_CLUI_IMM,
 335   OPERAND_VTYPEI10,
 336   OPERAND_VTYPEI11,
 337   OPERAND_RVKRNUM,
 338   OPERAND_RVKRNUM_0_7,
 339   OPERAND_RVKRNUM_1_10,
 340   OPERAND_RVKRNUM_2_14,
 341   OPERAND_SPIMM,
 342   // Operand is a 3-bit rounding mode, '111' indicates FRM register.
 343   // Represents 'frm' argument passing to floating-point operations.
 344   OPERAND_FRMARG,
 345   // Operand is a 3-bit rounding mode where only RTZ is valid.
 346   OPERAND_RTZARG,
 347   // Condition code used by select and short forward branch pseudos.
 348   OPERAND_COND_CODE,
 349   // Vector policy operand.
 350   OPERAND_VEC_POLICY,
 351   // Vector SEW operand. Stores in log2(SEW).
 352   OPERAND_SEW,
 353   // Special SEW for mask only instructions. Always 0.
 354   OPERAND_SEW_MASK,
 355   // Vector rounding mode for VXRM or FRM.
 356   OPERAND_VEC_RM,
 357   OPERAND_LAST_RISCV_IMM = OPERAND_VEC_RM,
 358   // Operand is either a register or uimm5, this is used by V extension pseudo
 359   // instructions to represent a value that be passed as AVL to either vsetvli
 360   // or vsetivli.
 361   OPERAND_AVL,
 362 };
 363 } // namespace RISCVOp
 364
 365 // Describes the predecessor/successor bits used in the FENCE instruction.
 366 namespace RISCVFenceField {
 367 enum FenceField {
 368   I = 8,
 369   O = 4,
 370   R = 2,
 371   W = 1
 372 };
 373 }
 374
 375 // Describes the supported floating point rounding mode encodings.
 376 namespace RISCVFPRndMode {
 377 enum RoundingMode {
 378   RNE = 0,
 379   RTZ = 1,
 380   RDN = 2,
 381   RUP = 3,
 382   RMM = 4,
 383   DYN = 7,
 384   Invalid
 385 };
 386
 387 inline static StringRef roundingModeToString(RoundingMode RndMode) {
 388   switch (RndMode) {
 389   default:
 390     llvm_unreachable("Unknown floating point rounding mode");
 391   case RISCVFPRndMode::RNE:
 392     return "rne";
 393   case RISCVFPRndMode::RTZ:
 394     return "rtz";
 395   case RISCVFPRndMode::RDN:
 396     return "rdn";
 397   case RISCVFPRndMode::RUP:
 398     return "rup";
 399   case RISCVFPRndMode::RMM:
 400     return "rmm";
 401   case RISCVFPRndMode::DYN:
 402     return "dyn";
 403   }
 404 }
 405
 406 inline static RoundingMode stringToRoundingMode(StringRef Str) {
 407   return StringSwitch<RoundingMode>(Str)
 408       .Case("rne", RISCVFPRndMode::RNE)
 409       .Case("rtz", RISCVFPRndMode::RTZ)
 410       .Case("rdn", RISCVFPRndMode::RDN)
 411       .Case("rup", RISCVFPRndMode::RUP)
 412       .Case("rmm", RISCVFPRndMode::RMM)
 413       .Case("dyn", RISCVFPRndMode::DYN)
 414       .Default(RISCVFPRndMode::Invalid);
 415 }
 416
 417 inline static bool isValidRoundingMode(unsigned Mode) {
 418   switch (Mode) {
 419   default:
 420     return false;
 421   case RISCVFPRndMode::RNE:
 422   case RISCVFPRndMode::RTZ:
 423   case RISCVFPRndMode::RDN:
 424   case RISCVFPRndMode::RUP:
 425   case RISCVFPRndMode::RMM:
 426   case RISCVFPRndMode::DYN:
 427     return true;
 428   }
 429 }
 430 } // namespace RISCVFPRndMode
 431
 432 namespace RISCVVXRndMode {
 433 enum RoundingMode {
 434   RNU = 0,
 435   RNE = 1,
 436   RDN = 2,
 437   ROD = 3,
 438 };
 439 } // namespace RISCVVXRndMode
 440
 441 //===----------------------------------------------------------------------===//
 442 // Floating-point Immediates
 443 //
 444
 445 namespace RISCVLoadFPImm {
 446 float getFPImm(unsigned Imm);
 447
 448 /// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
 449 /// immediate value. If the value cannot be represented as a 5-bit binary
 450 /// encoding, then return -1.
 451 int getLoadFPImm(APFloat FPImm);
 452 } // namespace RISCVLoadFPImm
 453
 454 namespace RISCVSysReg {
 455 struct SysReg {
 456   const char Name[32];
 457   unsigned Encoding;
 458   // FIXME: add these additional fields when needed.
 459   // Privilege Access: Read, Write, Read-Only.
 460   // unsigned ReadWrite;
 461   // Privilege Mode: User, System or Machine.
 462   // unsigned Mode;
 463   // Check field name.
 464   // unsigned Extra;
 465   // Register number without the privilege bits.
 466   // unsigned Number;
 467   FeatureBitset FeaturesRequired;
 468   bool IsRV32Only;
 469   bool IsAltName;
 470   bool IsDeprecatedName;
 471
 472   bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
 473     // Not in 32-bit mode.
 474     if (IsRV32Only && ActiveFeatures[RISCV::Feature64Bit])
 475       return false;
 476     // No required feature associated with the system register.
 477     if (FeaturesRequired.none())
 478       return true;
 479     return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
 480   }
 481 };
 482
 483 #define GET_SysRegEncodings_DECL
 484 #define GET_SysRegsList_DECL
 485 #include "RISCVGenSearchableTables.inc"
 486 } // end namespace RISCVSysReg
 487
 488 namespace RISCVInsnOpcode {
 489 struct RISCVOpcode {
 490   const char *Name;
 491   unsigned Value;
 492 };
 493
 494 #define GET_RISCVOpcodesList_DECL
 495 #include "RISCVGenSearchableTables.inc"
 496 } // end namespace RISCVInsnOpcode
 497
 498 namespace RISCVABI {
 499
 500 enum ABI {
 501   ABI_ILP32,
 502   ABI_ILP32F,
 503   ABI_ILP32D,
 504   ABI_ILP32E,
 505   ABI_LP64,
 506   ABI_LP64F,
 507   ABI_LP64D,
 508   ABI_LP64E,
 509   ABI_Unknown
 510 };
 511
 512 // Returns the target ABI, or else a StringError if the requested ABIName is
 513 // not supported for the given TT and FeatureBits combination.
 514 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
 515                      StringRef ABIName);
 516
 517 ABI getTargetABI(StringRef ABIName);
 518
 519 // Returns the register used to hold the stack pointer after realignment.
 520 MCRegister getBPReg();
 521
 522 // Returns the register holding shadow call stack pointer.
 523 MCRegister getSCSPReg();
 524
 525 } // namespace RISCVABI
 526
 527 namespace RISCVFeatures {
 528
 529 // Validates if the given combination of features are valid for the target
 530 // triple. Exits with report_fatal_error if not.
 531 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
 532
 533 llvm::Expected<std::unique_ptr<RISCVISAInfo>>
 534 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
 535
 536 } // namespace RISCVFeatures
 537
 538 namespace RISCVRVC {
 539 bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
 540 bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
 541 } // namespace RISCVRVC
 542
 543 namespace RISCVZC {
 544 enum RLISTENCODE {
 545   RA = 4,
 546   RA_S0,
 547   RA_S0_S1,
 548   RA_S0_S2,
 549   RA_S0_S3,
 550   RA_S0_S4,
 551   RA_S0_S5,
 552   RA_S0_S6,
 553   RA_S0_S7,
 554   RA_S0_S8,
 555   RA_S0_S9,
 556   // note - to include s10, s11 must also be included
 557   RA_S0_S11,
 558   INVALID_RLIST,
 559 };
 560
 561 inline unsigned encodeRlist(MCRegister EndReg, bool IsRV32E = false) {
 562   assert((!IsRV32E || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
 563   switch (EndReg) {
 564   case RISCV::X1:
 565     return RLISTENCODE::RA;
 566   case RISCV::X8:
 567     return RLISTENCODE::RA_S0;
 568   case RISCV::X9:
 569     return RLISTENCODE::RA_S0_S1;
 570   case RISCV::X18:
 571     return RLISTENCODE::RA_S0_S2;
 572   case RISCV::X19:
 573     return RLISTENCODE::RA_S0_S3;
 574   case RISCV::X20:
 575     return RLISTENCODE::RA_S0_S4;
 576   case RISCV::X21:
 577     return RLISTENCODE::RA_S0_S5;
 578   case RISCV::X22:
 579     return RLISTENCODE::RA_S0_S6;
 580   case RISCV::X23:
 581     return RLISTENCODE::RA_S0_S7;
 582   case RISCV::X24:
 583     return RLISTENCODE::RA_S0_S8;
 584   case RISCV::X25:
 585     return RLISTENCODE::RA_S0_S9;
 586   case RISCV::X26:
 587     return RLISTENCODE::INVALID_RLIST;
 588   case RISCV::X27:
 589     return RLISTENCODE::RA_S0_S11;
 590   default:
 591     llvm_unreachable("Undefined input.");
 592   }
 593 }
 594
 595 inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {
 596   assert(RlistVal != RLISTENCODE::INVALID_RLIST &&
 597          "{ra, s0-s10} is not supported, s11 must be included.");
 598   if (!IsRV64) {
 599     switch (RlistVal) {
 600     case RLISTENCODE::RA:
 601     case RLISTENCODE::RA_S0:
 602     case RLISTENCODE::RA_S0_S1:
 603     case RLISTENCODE::RA_S0_S2:
 604       return 16;
 605     case RLISTENCODE::RA_S0_S3:
 606     case RLISTENCODE::RA_S0_S4:
 607     case RLISTENCODE::RA_S0_S5:
 608     case RLISTENCODE::RA_S0_S6:
 609       return 32;
 610     case RLISTENCODE::RA_S0_S7:
 611     case RLISTENCODE::RA_S0_S8:
 612     case RLISTENCODE::RA_S0_S9:
 613       return 48;
 614     case RLISTENCODE::RA_S0_S11:
 615       return 64;
 616     }
 617   } else {
 618     switch (RlistVal) {
 619     case RLISTENCODE::RA:
 620     case RLISTENCODE::RA_S0:
 621       return 16;
 622     case RLISTENCODE::RA_S0_S1:
 623     case RLISTENCODE::RA_S0_S2:
 624       return 32;
 625     case RLISTENCODE::RA_S0_S3:
 626     case RLISTENCODE::RA_S0_S4:
 627       return 48;
 628     case RLISTENCODE::RA_S0_S5:
 629     case RLISTENCODE::RA_S0_S6:
 630       return 64;
 631     case RLISTENCODE::RA_S0_S7:
 632     case RLISTENCODE::RA_S0_S8:
 633       return 80;
 634     case RLISTENCODE::RA_S0_S9:
 635       return 96;
 636     case RLISTENCODE::RA_S0_S11:
 637       return 112;
 638     }
 639   }
 640   llvm_unreachable("Unexpected RlistVal");
 641 }
 642
 643 inline static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal,
 644                             int64_t StackAdjustment, bool IsRV64) {
 645   if (RlistVal == RLISTENCODE::INVALID_RLIST)
 646     return false;
 647   unsigned StackAdjBase = getStackAdjBase(RlistVal, IsRV64);
 648   StackAdjustment -= StackAdjBase;
 649   if (StackAdjustment % 16 != 0)
 650     return false;
 651   SpimmVal = StackAdjustment / 16;
 652   if (SpimmVal > 3)
 653     return false;
 654   return true;
 655 }
 656
 657 void printRlist(unsigned SlistEncode, raw_ostream &OS);
 658 } // namespace RISCVZC
 659
 660 } // namespace llvm
 661
 662 #endif