llvm/lib/Target/RISCV/RISCVFeatures.td

   1 //===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 //===----------------------------------------------------------------------===//
  10 // RISC-V subtarget features and instruction predicates.
  11 //===----------------------------------------------------------------------===//
  12
  13 // Subclass of SubtargetFeature to be used when the feature is also a RISC-V
  14 // extension. Extensions have a version and may be experimental.
  15 // NOTE: The extension name must start with
  16 //       - "FeatureStdExt" for standard extensions
  17 //       - "FeatureVendor" for vendor-specific extensions
  18 //
  19 // major     - Major version of extension.
  20 // minor     - Minor version of extension.
  21 // desc      - Description of extension.
  22 // implies   - Extensions or features implied by this extension.
  23 // fieldname - name of field to create in RISCVSubtarget. By default replaces
  24 //             uses the record name by replacing Feature with Has.
  25 // value     - Value to assign to the field in RISCVSubtarget when this
  26 //             extension is enabled. Usually "true", but can be changed.
  27 // IsExperimental
  28 //           - Indicates whether the extension is experimental
  29 class RISCVExtension<int major, int minor, string desc,
  30                      list<SubtargetFeature> implies = [],
  31                      string fieldname = !subst("Feature", "Has", NAME),
  32                      string value = "true", bit IsExperimental = false>
  33     : SubtargetFeature<"", fieldname, value, "", implies> {
  34   defvar extName = !subst("FeatureVendor", "", !subst("FeatureStdExt", "", NAME));
  35
  36   // Name - Name of the extension in lower case.
  37   let Name = !if(IsExperimental, "experimental-", "") # !tolower(extName);
  38
  39   // Desc - Description of extension with its name.
  40   let Desc = "'" # extName # "' (" # desc # ")";
  41
  42   // MajorVersion - The major version for this extension.
  43   int MajorVersion = major;
  44
  45   // MinorVersion - The minor version for this extension.
  46   int MinorVersion = minor;
  47
  48   // Experimental - Does extension require -menable-experimental-extensions.
  49   bit Experimental = false;
  50 }
  51
  52 // The groupID/bitmask of RISCVExtension is used to retrieve a specific bit value
  53 // from __riscv_feature_bits based on the groupID and bitmask.
  54 // groupID - groupID of extension
  55 // bitPos  - bit position of extension bitmask
  56 class RISCVExtensionBitmask<bits<3> groupID, int bitPos> {
  57     int GroupID = groupID;
  58     int BitPos = bitPos;
  59 }
  60
  61 // Version of RISCVExtension to be used for Experimental extensions. This
  62 // sets the Experimental flag and prepends experimental- to the -mattr name.
  63 class RISCVExperimentalExtension<int major, int minor, string desc,
  64                                  list<RISCVExtension> implies = [],
  65                                  string fieldname = !subst("Feature", "Has", NAME),
  66                                  string value = "true">
  67     : RISCVExtension<major, minor, desc, implies, fieldname, value, true> {
  68   let Experimental = true;
  69 }
  70
  71 // Integer Extensions
  72
  73 def FeatureStdExtI
  74     : RISCVExtension<2, 1, "Base Integer Instruction Set">,
  75       RISCVExtensionBitmask<0, 8>;
  76
  77 def FeatureStdExtE
  78     : RISCVExtension<2, 0, "Embedded Instruction Set with 16 GPRs">;
  79
  80 def FeatureStdExtZic64b
  81     : RISCVExtension<1, 0, "Cache Block Size Is 64 Bytes">;
  82
  83 def FeatureStdExtZicbom
  84     : RISCVExtension<1, 0, "Cache-Block Management Instructions">;
  85 def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
  86                       AssemblerPredicate<(all_of FeatureStdExtZicbom),
  87                           "'Zicbom' (Cache-Block Management Instructions)">;
  88
  89 def FeatureStdExtZicbop
  90     : RISCVExtension<1, 0, "Cache-Block Prefetch Instructions">;
  91 def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
  92                       AssemblerPredicate<(all_of FeatureStdExtZicbop),
  93                           "'Zicbop' (Cache-Block Prefetch Instructions)">;
  94
  95 def FeatureStdExtZicboz
  96     : RISCVExtension<1, 0, "Cache-Block Zero Instructions">,
  97       RISCVExtensionBitmask<0, 37>;
  98 def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
  99                       AssemblerPredicate<(all_of FeatureStdExtZicboz),
 100                           "'Zicboz' (Cache-Block Zero Instructions)">;
 101
 102 def FeatureStdExtZiccamoa
 103     : RISCVExtension<1, 0, "Main Memory Supports All Atomics in A">;
 104
 105 def FeatureStdExtZiccif
 106     : RISCVExtension<1, 0,
 107                      "Main Memory Supports Instruction Fetch with Atomicity Requirement">;
 108
 109 def FeatureStdExtZicclsm
 110     : RISCVExtension<1, 0, "Main Memory Supports Misaligned Loads/Stores">;
 111
 112 def FeatureStdExtZiccrse
 113     : RISCVExtension<1, 0,
 114                      "Main Memory Supports Forward Progress on LR/SC Sequences">;
 115
 116 def FeatureStdExtZicsr
 117     : RISCVExtension<2, 0, "CSRs">;
 118 def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
 119                      AssemblerPredicate<(all_of FeatureStdExtZicsr),
 120                                         "'Zicsr' (CSRs)">;
 121
 122 def FeatureStdExtZicntr
 123     : RISCVExtension<2, 0, "Base Counters and Timers",
 124                      [FeatureStdExtZicsr]>;
 125
 126 def FeatureStdExtZicond
 127     : RISCVExtension<1, 0, "Integer Conditional Operations">,
 128       RISCVExtensionBitmask<0, 38>;
 129 def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
 130                       AssemblerPredicate<(all_of FeatureStdExtZicond),
 131                           "(Integer Conditional Operations)">;
 132
 133 def FeatureStdExtZifencei
 134     : RISCVExtension<2, 0, "fence.i">;
 135 def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
 136                         AssemblerPredicate<(all_of FeatureStdExtZifencei),
 137                                            "'Zifencei' (fence.i)">;
 138
 139 def FeatureStdExtZihintpause
 140     : RISCVExtension<2, 0, "Pause Hint">,
 141       RISCVExtensionBitmask<0, 40>;
 142 def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
 143                            AssemblerPredicate<(all_of FeatureStdExtZihintpause),
 144                                               "'Zihintpause' (Pause Hint)">;
 145
 146 def FeatureStdExtZihintntl
 147     : RISCVExtension<1, 0, "Non-Temporal Locality Hints">,
 148       RISCVExtensionBitmask<0, 39>;
 149 def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
 150                          AssemblerPredicate<(all_of FeatureStdExtZihintntl),
 151                              "'Zihintntl' (Non-Temporal Locality Hints)">;
 152
 153 def FeatureStdExtZihpm
 154     : RISCVExtension<2, 0, "Hardware Performance Counters",
 155                      [FeatureStdExtZicsr]>;
 156
 157 def FeatureStdExtZimop : RISCVExtension<1, 0, "May-Be-Operations">;
 158 def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
 159                      AssemblerPredicate<(all_of FeatureStdExtZimop),
 160                                         "'Zimop' (May-Be-Operations)">;
 161
 162 def FeatureStdExtZicfilp
 163     : RISCVExperimentalExtension<1, 0, "Landing pad",
 164                                  [FeatureStdExtZicsr]>;
 165 def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
 166                        AssemblerPredicate<(all_of FeatureStdExtZicfilp),
 167                                           "'Zicfilp' (Landing pad)">;
 168 def NoStdExtZicfilp : Predicate<"!Subtarget->hasStdExtZicfilp()">,
 169                       AssemblerPredicate<(all_of (not FeatureStdExtZicfilp))>;
 170
 171 def FeatureStdExtZicfiss
 172     : RISCVExperimentalExtension<1, 0, "Shadow stack",
 173                                  [FeatureStdExtZicsr, FeatureStdExtZimop]>;
 174 def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
 175                        AssemblerPredicate<(all_of FeatureStdExtZicfiss),
 176                                           "'Zicfiss' (Shadow stack)">;
 177 def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
 178
 179 // Multiply Extensions
 180
 181 def FeatureStdExtZmmul
 182     : RISCVExtension<1, 0, "Integer Multiplication">;
 183 def HasStdExtZmmul : Predicate<"Subtarget->hasStdExtZmmul()">,
 184                      AssemblerPredicate<(all_of FeatureStdExtZmmul),
 185                      "'Zmmul' (Integer Multiplication)">;
 186
 187 def FeatureStdExtM
 188     : RISCVExtension<2, 0, "Integer Multiplication and Division",
 189                      [FeatureStdExtZmmul]>,
 190       RISCVExtensionBitmask<0, 12>;
 191 def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
 192                  AssemblerPredicate<(all_of FeatureStdExtM),
 193                      "'M' (Integer Multiplication and Division)">;
 194
 195 // Atomic Extensions
 196
 197 def FeatureStdExtZaamo
 198     : RISCVExtension<1, 0, "Atomic Memory Operations">;
 199 def HasStdExtZaamo
 200     : Predicate<"Subtarget->hasStdExtZaamo()">,
 201       AssemblerPredicate<(any_of FeatureStdExtZaamo),
 202                          "'Zaamo' (Atomic Memory Operations)">;
 203
 204 def FeatureStdExtZalrsc
 205     : RISCVExtension<1, 0, "Load-Reserved/Store-Conditional">;
 206 def HasStdExtZalrsc
 207     : Predicate<"Subtarget->hasStdExtZalrsc()">,
 208       AssemblerPredicate<(any_of FeatureStdExtZalrsc),
 209                          "'Zalrsc' (Load-Reserved/Store-Conditional)">;
 210
 211 def FeatureStdExtA
 212     : RISCVExtension<2, 1, "Atomic Instructions",
 213                      [FeatureStdExtZaamo, FeatureStdExtZalrsc]>,
 214       RISCVExtensionBitmask<0, 0>;
 215 def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
 216                  AssemblerPredicate<(all_of FeatureStdExtA),
 217                                     "'A' (Atomic Instructions)">;
 218
 219 def FeatureStdExtZtso
 220     : RISCVExtension<1, 0, "Memory Model - Total Store Order">,
 221       RISCVExtensionBitmask<0, 47>;
 222 def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
 223                     AssemblerPredicate<(all_of FeatureStdExtZtso),
 224                         "'Ztso' (Memory Model - Total Store Order)">;
 225 def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
 226
 227 def FeatureStdExtZa64rs
 228     : RISCVExtension<1, 0, "Reservation Set Size of at Most 64 Bytes">;
 229
 230 def FeatureStdExtZa128rs
 231     : RISCVExtension<1, 0, "Reservation Set Size of at Most 128 Bytes">;
 232
 233 def FeatureStdExtZabha
 234     : RISCVExtension<1, 0, "Byte and Halfword Atomic Memory Operations",
 235                      [FeatureStdExtZaamo]>;
 236 def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
 237                      AssemblerPredicate<(all_of FeatureStdExtZabha),
 238                          "'Zabha' (Byte and Halfword Atomic Memory Operations)">;
 239
 240 def FeatureStdExtZacas
 241     : RISCVExtension<1, 0, "Atomic Compare-And-Swap Instructions",
 242                      [FeatureStdExtZaamo]>,
 243       RISCVExtensionBitmask<0, 26>;
 244 def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
 245                      AssemblerPredicate<(all_of FeatureStdExtZacas),
 246                          "'Zacas' (Atomic Compare-And-Swap Instructions)">;
 247 def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
 248
 249 def FeatureStdExtZalasr
 250     : RISCVExperimentalExtension<0, 1, "Load-Acquire and Store-Release Instructions">;
 251 def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
 252                       AssemblerPredicate<(all_of FeatureStdExtZalasr),
 253                           "'Zalasr' (Load-Acquire and Store-Release Instructions)">;
 254
 255 def FeatureStdExtZama16b
 256     : RISCVExtension<1, 0, "Atomic 16-byte misaligned loads, stores and AMOs">;
 257
 258 def FeatureStdExtZawrs : RISCVExtension<1, 0, "Wait on Reservation Set">;
 259 def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
 260                      AssemblerPredicate<(all_of FeatureStdExtZawrs),
 261                                         "'Zawrs' (Wait on Reservation Set)">;
 262
 263 // Floating Point Extensions
 264
 265 def FeatureStdExtF
 266     : RISCVExtension<2, 2, "Single-Precision Floating-Point",
 267                      [FeatureStdExtZicsr]>,
 268       RISCVExtensionBitmask<0, 5>;
 269 def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
 270                  AssemblerPredicate<(all_of FeatureStdExtF),
 271                                     "'F' (Single-Precision Floating-Point)">;
 272
 273 def FeatureStdExtD
 274     : RISCVExtension<2, 2, "Double-Precision Floating-Point",
 275                      [FeatureStdExtF]>,
 276       RISCVExtensionBitmask<0, 3>;
 277 def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
 278                  AssemblerPredicate<(all_of FeatureStdExtD),
 279                                     "'D' (Double-Precision Floating-Point)">;
 280
 281 def FeatureStdExtZfhmin
 282     : RISCVExtension<1, 0, "Half-Precision Floating-Point Minimal",
 283                      [FeatureStdExtF]>,
 284       RISCVExtensionBitmask<0, 36>;
 285 def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
 286                       AssemblerPredicate<(all_of FeatureStdExtZfhmin),
 287                           "'Zfh' (Half-Precision Floating-Point) or "
 288                           "'Zfhmin' (Half-Precision Floating-Point Minimal)">;
 289
 290 def FeatureStdExtZfh
 291     : RISCVExtension<1, 0, "Half-Precision Floating-Point",
 292                      [FeatureStdExtZfhmin]>,
 293       RISCVExtensionBitmask<0, 35>;
 294 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
 295                    AssemblerPredicate<(all_of FeatureStdExtZfh),
 296                        "'Zfh' (Half-Precision Floating-Point)">;
 297 def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
 298
 299 def FeatureStdExtZfbfmin
 300     : RISCVExtension<1, 0, "Scalar BF16 Converts", [FeatureStdExtF]>;
 301 def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
 302                        AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
 303                                           "'Zfbfmin' (Scalar BF16 Converts)">;
 304
 305 def HasHalfFPLoadStoreMove
 306     : Predicate<"Subtarget->hasHalfFPLoadStoreMove()">,
 307       AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin,
 308                                  FeatureStdExtZfbfmin),
 309                          "'Zfh' (Half-Precision Floating-Point) or "
 310                                     "'Zfhmin' (Half-Precision Floating-Point Minimal) or "
 311                                     "'Zfbfmin' (Scalar BF16 Converts)">;
 312
 313 def FeatureStdExtZfa
 314     : RISCVExtension<1, 0, "Additional Floating-Point", [FeatureStdExtF]>,
 315       RISCVExtensionBitmask<0, 34>;
 316 def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
 317                    AssemblerPredicate<(all_of FeatureStdExtZfa),
 318                                       "'Zfa' (Additional Floating-Point)">;
 319 def NoStdExtZfa : Predicate<"!Subtarget->hasStdExtZfa()">;
 320
 321 def FeatureStdExtZfinx
 322     : RISCVExtension<1, 0, "Float in Integer", [FeatureStdExtZicsr]>;
 323 def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
 324                      AssemblerPredicate<(all_of FeatureStdExtZfinx),
 325                                         "'Zfinx' (Float in Integer)">;
 326 def HasStdExtFOrZfinx : Predicate<"Subtarget->hasStdExtFOrZfinx()">,
 327                         AssemblerPredicate<(any_of FeatureStdExtF,
 328                                                    FeatureStdExtZfinx),
 329                             "'F' (Single-Precision Floating-Point) or "
 330                             "'Zfinx' (Float in Integer)">;
 331
 332 def FeatureStdExtZdinx
 333     : RISCVExtension<1, 0, "Double in Integer", [FeatureStdExtZfinx]>;
 334 def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
 335                      AssemblerPredicate<(all_of FeatureStdExtZdinx),
 336                                         "'Zdinx' (Double in Integer)">;
 337
 338 def FeatureStdExtZhinxmin
 339     : RISCVExtension<1, 0, "Half Float in Integer Minimal",
 340                      [FeatureStdExtZfinx]>;
 341 def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
 342                         AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
 343                             "'Zhinx' (Half Float in Integer) or "
 344                             "'Zhinxmin' (Half Float in Integer Minimal)">;
 345
 346 def FeatureStdExtZhinx
 347     : RISCVExtension<1, 0, "Half Float in Integer", [FeatureStdExtZhinxmin]>;
 348 def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
 349                      AssemblerPredicate<(all_of FeatureStdExtZhinx),
 350                                         "'Zhinx' (Half Float in Integer)">;
 351 def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
 352
 353 // Compressed Extensions
 354
 355 def FeatureStdExtC
 356     : RISCVExtension<2, 0, "Compressed Instructions">,
 357       RISCVExtensionBitmask<0, 2>;
 358 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
 359                  AssemblerPredicate<(all_of FeatureStdExtC),
 360                                     "'C' (Compressed Instructions)">;
 361
 362 def FeatureNoRVCHints
 363     : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
 364                        "Disable RVC Hint Instructions.">;
 365 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
 366                   AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
 367                                      "RVC Hint Instructions">;
 368
 369 def FeatureStdExtZca
 370     : RISCVExtension<1, 0,
 371                      "part of the C extension, excluding compressed "
 372                      "floating point loads/stores">;
 373
 374 def HasStdExtCOrZca
 375     : Predicate<"Subtarget->hasStdExtCOrZca()">,
 376       AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZca),
 377                          "'C' (Compressed Instructions) or "
 378                          "'Zca' (part of the C extension, excluding "
 379                          "compressed floating point loads/stores)">;
 380
 381 def FeatureStdExtZcb
 382     : RISCVExtension<1, 0, "Compressed basic bit manipulation instructions",
 383                      [FeatureStdExtZca]>;
 384 def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
 385                    AssemblerPredicate<(all_of FeatureStdExtZcb),
 386                        "'Zcb' (Compressed basic bit manipulation instructions)">;
 387
 388 def FeatureStdExtZcd
 389     : RISCVExtension<1, 0,
 390                      "Compressed Double-Precision Floating-Point Instructions",
 391                      [FeatureStdExtD, FeatureStdExtZca]>;
 392
 393 def HasStdExtCOrZcd
 394     : Predicate<"Subtarget->hasStdExtCOrZcd()">,
 395       AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),
 396                          "'C' (Compressed Instructions) or "
 397                          "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
 398
 399 def FeatureStdExtZcf
 400     : RISCVExtension<1, 0,
 401                      "Compressed Single-Precision Floating-Point Instructions",
 402                      [FeatureStdExtF, FeatureStdExtZca]>;
 403
 404 def FeatureStdExtZcmp
 405     : RISCVExtension<1, 0,
 406                      "sequenced instructions for code-size reduction",
 407                      [FeatureStdExtZca]>;
 408 def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
 409                     AssemblerPredicate<(all_of FeatureStdExtZcmp),
 410                         "'Zcmp' (sequenced instructions for code-size reduction)">;
 411
 412 def FeatureStdExtZcmt
 413     : RISCVExtension<1, 0,
 414                      "table jump instructions for code-size reduction",
 415                      [FeatureStdExtZca, FeatureStdExtZicsr]>;
 416 def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
 417                            AssemblerPredicate<(all_of FeatureStdExtZcmt),
 418                            "'Zcmt' (table jump instructions for code-size reduction)">;
 419
 420 def FeatureStdExtZce
 421     : RISCVExtension<1, 0,
 422                      "Compressed extensions for microcontrollers",
 423                      [FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt]>;
 424
 425 def HasStdExtCOrZcfOrZce
 426     : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
 427                 "Subtarget->hasStdExtZce()">,
 428       AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf,
 429                                  FeatureStdExtZce),
 430                          "'C' (Compressed Instructions) or "
 431                          "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
 432
 433 def FeatureStdExtZcmop
 434     : RISCVExtension<1, 0, "Compressed May-Be-Operations",
 435                      [FeatureStdExtZca]>;
 436 def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
 437                      AssemblerPredicate<(all_of FeatureStdExtZcmop),
 438                          "'Zcmop' (Compressed May-Be-Operations)">;
 439
 440 // Bitmanip Extensions
 441
 442 def FeatureStdExtZba
 443     : RISCVExtension<1, 0, "Address Generation Instructions">,
 444       RISCVExtensionBitmask<0, 27>;
 445 def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
 446                    AssemblerPredicate<(all_of FeatureStdExtZba),
 447                                       "'Zba' (Address Generation Instructions)">;
 448 def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
 449
 450 def FeatureStdExtZbb
 451     : RISCVExtension<1, 0, "Basic Bit-Manipulation">,
 452       RISCVExtensionBitmask<0, 28>;
 453 def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
 454                    AssemblerPredicate<(all_of FeatureStdExtZbb),
 455                                       "'Zbb' (Basic Bit-Manipulation)">;
 456 def NoStdExtZbb : Predicate<"!Subtarget->hasStdExtZbb()">,
 457                   AssemblerPredicate<(all_of (not FeatureStdExtZbb))>;
 458
 459 def FeatureStdExtZbc
 460     : RISCVExtension<1, 0, "Carry-Less Multiplication">,
 461       RISCVExtensionBitmask<0, 29>;
 462 def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
 463                    AssemblerPredicate<(all_of FeatureStdExtZbc),
 464                                       "'Zbc' (Carry-Less Multiplication)">;
 465
 466 def FeatureStdExtZbs
 467     : RISCVExtension<1, 0, "Single-Bit Instructions">,
 468       RISCVExtensionBitmask<0, 33>;
 469 def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 470                    AssemblerPredicate<(all_of FeatureStdExtZbs),
 471                                       "'Zbs' (Single-Bit Instructions)">;
 472
 473 // Bitmanip Extensions for Cryptography Extensions
 474
 475 def FeatureStdExtB
 476     : RISCVExtension<1, 0, "the collection of the Zba, Zbb, Zbs extensions",
 477                      [FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>;
 478
 479 def FeatureStdExtZbkb
 480     : RISCVExtension<1, 0, "Bitmanip instructions for Cryptography">,
 481       RISCVExtensionBitmask<0, 30>;
 482 def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
 483                     AssemblerPredicate<(all_of FeatureStdExtZbkb),
 484                         "'Zbkb' (Bitmanip instructions for Cryptography)">;
 485 def NoStdExtZbkb : Predicate<"!Subtarget->hasStdExtZbkb()">,
 486                    AssemblerPredicate<(all_of (not FeatureStdExtZbkb))>;
 487
 488 def FeatureStdExtZbkx
 489     : RISCVExtension<1, 0, "Crossbar permutation instructions">,
 490       RISCVExtensionBitmask<0, 32>;
 491 def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
 492                     AssemblerPredicate<(all_of FeatureStdExtZbkx),
 493                         "'Zbkx' (Crossbar permutation instructions)">;
 494
 495 def HasStdExtZbbOrZbkb
 496     : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">,
 497       AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb),
 498                          "'Zbb' (Basic Bit-Manipulation) or "
 499                          "'Zbkb' (Bitmanip instructions for Cryptography)">;
 500
 501 // The Carry-less multiply subextension for cryptography is a subset of basic
 502 // carry-less multiply subextension. The former should be enabled if the latter
 503 // is enabled.
 504 def FeatureStdExtZbkc
 505     : RISCVExtension<1, 0,
 506                      "Carry-less multiply instructions for Cryptography">,
 507       RISCVExtensionBitmask<0, 31>;
 508 def HasStdExtZbkc
 509     : Predicate<"Subtarget->hasStdExtZbkc()">,
 510       AssemblerPredicate<(all_of FeatureStdExtZbkc),
 511           "'Zbkc' (Carry-less multiply instructions for Cryptography)">;
 512
 513 def HasStdExtZbcOrZbkc
 514     : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">,
 515       AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc),
 516                          "'Zbc' (Carry-Less Multiplication) or "
 517                          "'Zbkc' (Carry-less multiply instructions "
 518                          "for Cryptography)">;
 519
 520 // Cryptography Extensions
 521
 522 def FeatureStdExtZknd
 523     : RISCVExtension<1, 0, "NIST Suite: AES Decryption">,
 524       RISCVExtensionBitmask<0, 41>;
 525 def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
 526                     AssemblerPredicate<(all_of FeatureStdExtZknd),
 527                                        "'Zknd' (NIST Suite: AES Decryption)">;
 528
 529 def FeatureStdExtZkne
 530     : RISCVExtension<1, 0, "NIST Suite: AES Encryption">,
 531       RISCVExtensionBitmask<0, 42>;
 532 def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
 533                     AssemblerPredicate<(all_of FeatureStdExtZkne),
 534                                        "'Zkne' (NIST Suite: AES Encryption)">;
 535
 536 // Some instructions belong to both Zknd and Zkne subextensions.
 537 // They should be enabled if either has been specified.
 538 def HasStdExtZkndOrZkne
 539     : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">,
 540       AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne),
 541                          "'Zknd' (NIST Suite: AES Decryption) or "
 542                          "'Zkne' (NIST Suite: AES Encryption)">;
 543
 544 def FeatureStdExtZknh
 545     : RISCVExtension<1, 0, "NIST Suite: Hash Function Instructions">,
 546       RISCVExtensionBitmask<0, 43>;
 547 def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
 548                     AssemblerPredicate<(all_of FeatureStdExtZknh),
 549                         "'Zknh' (NIST Suite: Hash Function Instructions)">;
 550
 551 def FeatureStdExtZksed
 552     : RISCVExtension<1, 0, "ShangMi Suite: SM4 Block Cipher Instructions">,
 553       RISCVExtensionBitmask<0, 44>;
 554 def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
 555                      AssemblerPredicate<(all_of FeatureStdExtZksed),
 556                          "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
 557
 558 def FeatureStdExtZksh
 559     : RISCVExtension<1, 0, "ShangMi Suite: SM3 Hash Function Instructions">,
 560       RISCVExtensionBitmask<0, 45>;
 561 def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
 562                     AssemblerPredicate<(all_of FeatureStdExtZksh),
 563                         "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
 564
 565 def FeatureStdExtZkr
 566     : RISCVExtension<1, 0, "Entropy Source Extension">;
 567 def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
 568                    AssemblerPredicate<(all_of FeatureStdExtZkr),
 569                                       "'Zkr' (Entropy Source Extension)">;
 570
 571 def FeatureStdExtZkn
 572     : RISCVExtension<1, 0, "NIST Algorithm Suite",
 573                      [FeatureStdExtZbkb,
 574                       FeatureStdExtZbkc,
 575                       FeatureStdExtZbkx,
 576                       FeatureStdExtZkne,
 577                       FeatureStdExtZknd,
 578                       FeatureStdExtZknh]>;
 579
 580 def FeatureStdExtZks
 581     : RISCVExtension<1, 0, "ShangMi Algorithm Suite",
 582                      [FeatureStdExtZbkb,
 583                       FeatureStdExtZbkc,
 584                       FeatureStdExtZbkx,
 585                       FeatureStdExtZksed,
 586                       FeatureStdExtZksh]>;
 587
 588 def FeatureStdExtZkt
 589     : RISCVExtension<1, 0, "Data Independent Execution Latency">,
 590       RISCVExtensionBitmask<0, 46>;
 591
 592 def FeatureStdExtZk
 593     : RISCVExtension<1, 0, "Standard scalar cryptography extension",
 594                      [FeatureStdExtZkn,
 595                       FeatureStdExtZkr,
 596                       FeatureStdExtZkt]>;
 597
 598 // Vector Extensions
 599
 600 def FeatureStdExtZvl32b : RISCVExtension<1, 0,
 601                                          "Minimum Vector Length 32", [],
 602                                          "ZvlLen", "32">;
 603
 604 foreach i = { 6-16 } in {
 605   defvar I = !shl(1, i);
 606   def FeatureStdExtZvl#I#b :
 607       RISCVExtension<1, 0, "Minimum Vector Length "#I,
 608                      [!cast<RISCVExtension>("FeatureStdExtZvl"#!srl(I, 1)#"b")],
 609                      "ZvlLen", !cast<string>(I)>;
 610 }
 611
 612 def FeatureStdExtZve32x
 613     : RISCVExtension<1, 0,
 614                      "Vector Extensions for Embedded Processors "
 615                      "with maximal 32 EEW",
 616                      [FeatureStdExtZicsr, FeatureStdExtZvl32b]>;
 617
 618
 619 def FeatureStdExtZve32f
 620     : RISCVExtension<1, 0,
 621                      "Vector Extensions for Embedded Processors "
 622                      "with maximal 32 EEW and F extension",
 623                      [FeatureStdExtZve32x, FeatureStdExtF]>;
 624
 625 def FeatureStdExtZve64x
 626     : RISCVExtension<1, 0,
 627                      "Vector Extensions for Embedded Processors "
 628                      "with maximal 64 EEW",
 629                      [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
 630
 631 def FeatureStdExtZve64f
 632     : RISCVExtension<1, 0,
 633                      "Vector Extensions for Embedded Processors "
 634                      "with maximal 64 EEW and F extension",
 635                      [FeatureStdExtZve32f, FeatureStdExtZve64x]>;
 636
 637 def FeatureStdExtZve64d
 638     : RISCVExtension<1, 0,
 639                      "Vector Extensions for Embedded Processors "
 640                      "with maximal 64 EEW, F and D extension",
 641                      [FeatureStdExtZve64f, FeatureStdExtD]>;
 642
 643 def FeatureStdExtV
 644     : RISCVExtension<1, 0,
 645                      "Vector Extension for Application Processors",
 646                      [FeatureStdExtZvl128b, FeatureStdExtZve64d]>,
 647       RISCVExtensionBitmask<0, 21>;
 648
 649 def FeatureStdExtZvfbfmin
 650     : RISCVExtension<1, 0, "Vector BF16 Converts", [FeatureStdExtZve32f]>;
 651 def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
 652                         AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
 653                             "'Zvfbfmin' (Vector BF16 Converts)">;
 654
 655 def FeatureStdExtZvfbfwma
 656     : RISCVExtension<1, 0, "Vector BF16 widening mul-add",
 657                      [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>;
 658 def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
 659                         AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
 660                             "'Zvfbfwma' (Vector BF16 widening mul-add)">;
 661
 662 def FeatureStdExtZvfhmin
 663     : RISCVExtension<1, 0,
 664                      "Vector Half-Precision Floating-Point Minimal",
 665                      [FeatureStdExtZve32f]>,
 666       RISCVExtensionBitmask<0, 51>;
 667
 668 def FeatureStdExtZvfh
 669     : RISCVExtension<1, 0, "Vector Half-Precision Floating-Point",
 670                      [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>,
 671       RISCVExtensionBitmask<0, 50>;
 672
 673 def HasStdExtZfhOrZvfh
 674     : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
 675       AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZvfh),
 676                          "'Zfh' (Half-Precision Floating-Point) or "
 677                          "'Zvfh' (Vector Half-Precision Floating-Point)">;
 678
 679 // Vector Cryptography and Bitmanip Extensions
 680
 681 def FeatureStdExtZvkb
 682     : RISCVExtension<1, 0, "Vector Bit-manipulation used in Cryptography",
 683                      [FeatureStdExtZve32x]>,
 684       RISCVExtensionBitmask<0, 52>;
 685 def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
 686                     AssemblerPredicate<(all_of FeatureStdExtZvkb),
 687                         "'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
 688
 689 def FeatureStdExtZvbb
 690     : RISCVExtension<1, 0, "Vector basic bit-manipulation instructions",
 691                      [FeatureStdExtZvkb]>,
 692       RISCVExtensionBitmask<0, 48>;
 693 def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
 694                     AssemblerPredicate<(all_of FeatureStdExtZvbb),
 695                         "'Zvbb' (Vector basic bit-manipulation instructions)">;
 696
 697 def FeatureStdExtZvbc
 698     : RISCVExtension<1, 0, "Vector Carryless Multiplication",
 699                      [FeatureStdExtZve64x]>,
 700       RISCVExtensionBitmask<0, 49>;
 701 def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
 702                     AssemblerPredicate<(all_of FeatureStdExtZvbc),
 703                         "'Zvbc' (Vector Carryless Multiplication)">;
 704
 705 def FeatureStdExtZvbc32e
 706     : RISCVExperimentalExtension<0, 7,
 707                                  "Vector Carryless Multiplication with 32-bits elements",
 708                                  [FeatureStdExtZve32x]>;
 709
 710 def HasStdExtZvbcOrZvbc32e : Predicate<"Subtarget->hasStdExtZvbc() || Subtarget->hasStdExtZvbc32e()">,
 711                              AssemblerPredicate<(any_of FeatureStdExtZvbc, FeatureStdExtZvbc32e),
 712                              "'Zvbc' or 'Zvbc32e' (Vector Carryless Multiplication)">;
 713
 714 def FeatureStdExtZvkg
 715     : RISCVExtension<1, 0, "Vector GCM instructions for Cryptography",
 716                      [FeatureStdExtZve32x]>,
 717       RISCVExtensionBitmask<0, 53>;
 718 def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
 719                     AssemblerPredicate<(all_of FeatureStdExtZvkg),
 720                         "'Zvkg' (Vector GCM instructions for Cryptography)">;
 721
 722 def FeatureStdExtZvkgs
 723     : RISCVExperimentalExtension<0, 7,
 724                                  "Vector-Scalar GCM instructions for Cryptography",
 725                                  [FeatureStdExtZvkg]>;
 726 def HasStdExtZvkgs : Predicate<"Subtarget->hasStdExtZvkgs()">,
 727                      AssemblerPredicate<(all_of FeatureStdExtZvkgs),
 728                         "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)">;
 729
 730 def FeatureStdExtZvkned
 731     : RISCVExtension<1, 0,
 732                      "Vector AES Encryption & Decryption (Single Round)",
 733                      [FeatureStdExtZve32x]>,
 734       RISCVExtensionBitmask<0, 54>;
 735 def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
 736                       AssemblerPredicate<(all_of FeatureStdExtZvkned),
 737                           "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
 738
 739 def FeatureStdExtZvknha
 740     : RISCVExtension<1, 0, "Vector SHA-2 (SHA-256 only)",
 741                      [FeatureStdExtZve32x]>,
 742       RISCVExtensionBitmask<0, 55>;
 743 def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
 744                       AssemblerPredicate<(all_of FeatureStdExtZvknha),
 745                           "'Zvknha' (Vector SHA-2 (SHA-256 only))">;
 746
 747 def FeatureStdExtZvknhb
 748     : RISCVExtension<1, 0, "Vector SHA-2 (SHA-256 and SHA-512)",
 749                      [FeatureStdExtZve64x]>,
 750       RISCVExtensionBitmask<0, 56>;
 751 def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,
 752                       AssemblerPredicate<(all_of FeatureStdExtZvknhb),
 753                           "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">;
 754
 755 def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarget->hasStdExtZvknhb()">,
 756                               AssemblerPredicate<(any_of FeatureStdExtZvknha, FeatureStdExtZvknhb),
 757                                   "'Zvknha' or 'Zvknhb' (Vector SHA-2)">;
 758
 759 def FeatureStdExtZvksed
 760     : RISCVExtension<1, 0, "SM4 Block Cipher Instructions",
 761                      [FeatureStdExtZve32x]>,
 762       RISCVExtensionBitmask<0, 57>;
 763 def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
 764                       AssemblerPredicate<(all_of FeatureStdExtZvksed),
 765                           "'Zvksed' (SM4 Block Cipher Instructions)">;
 766
 767 def FeatureStdExtZvksh
 768     : RISCVExtension<1, 0, "SM3 Hash Function Instructions",
 769                      [FeatureStdExtZve32x]>,
 770       RISCVExtensionBitmask<0, 58>;
 771 def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
 772                      AssemblerPredicate<(all_of FeatureStdExtZvksh),
 773                          "'Zvksh' (SM3 Hash Function Instructions)">;
 774
 775 def FeatureStdExtZvkt
 776     : RISCVExtension<1, 0, "Vector Data-Independent Execution Latency">,
 777       RISCVExtensionBitmask<0, 59>;
 778
 779 // Zvk short-hand extensions
 780
 781 def FeatureStdExtZvkn
 782     : RISCVExtension<1, 0,
 783                      "shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt'",
 784                      [FeatureStdExtZvkned, FeatureStdExtZvknhb,
 785                       FeatureStdExtZvkb, FeatureStdExtZvkt]>;
 786
 787 def FeatureStdExtZvknc
 788     : RISCVExtension<1, 0, "shorthand for 'Zvknc' and 'Zvbc'",
 789                      [FeatureStdExtZvkn, FeatureStdExtZvbc]>;
 790
 791 def FeatureStdExtZvkng
 792     : RISCVExtension<1, 0, "shorthand for 'Zvkn' and 'Zvkg'",
 793                      [FeatureStdExtZvkn, FeatureStdExtZvkg]>;
 794
 795 def FeatureStdExtZvks
 796     : RISCVExtension<1, 0,
 797                      "shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt'",
 798                      [FeatureStdExtZvksed, FeatureStdExtZvksh,
 799                       FeatureStdExtZvkb, FeatureStdExtZvkt]>;
 800
 801 def FeatureStdExtZvksc
 802     : RISCVExtension<1, 0, "shorthand for 'Zvks' and 'Zvbc'",
 803                      [FeatureStdExtZvks, FeatureStdExtZvbc]>;
 804
 805 def FeatureStdExtZvksg
 806     : RISCVExtension<1, 0, "shorthand for 'Zvks' and 'Zvkg'",
 807                      [FeatureStdExtZvks, FeatureStdExtZvkg]>;
 808 // Vector instruction predicates
 809
 810 def HasVInstructions    : Predicate<"Subtarget->hasVInstructions()">,
 811       AssemblerPredicate<
 812           (any_of FeatureStdExtZve32x),
 813           "'V' (Vector Extension for Application Processors), 'Zve32x' "
 814           "(Vector Extensions for Embedded Processors)">;
 815 def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">,
 816       AssemblerPredicate<
 817           (any_of FeatureStdExtZve64x),
 818           "'V' (Vector Extension for Application Processors) or 'Zve64x' "
 819           "(Vector Extensions for Embedded Processors)">;
 820 def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">,
 821       AssemblerPredicate<
 822           (any_of FeatureStdExtZve32f),
 823           "'V' (Vector Extension for Application Processors), 'Zve32f' "
 824           "(Vector Extensions for Embedded Processors)">;
 825
 826 def HasVInstructionsF16Minimal : Predicate<"Subtarget->hasVInstructionsF16Minimal()">,
 827       AssemblerPredicate<(any_of FeatureStdExtZvfhmin, FeatureStdExtZvfh),
 828                          "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or "
 829                          "'Zvfh' (Vector Half-Precision Floating-Point)">;
 830
 831 def HasVInstructionsBF16Minimal : Predicate<"Subtarget->hasVInstructionsBF16Minimal()">;
 832 def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
 833 def HasVInstructionsF64 : Predicate<"Subtarget->hasVInstructionsF64()">;
 834
 835 def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMultiply()">;
 836
 837 // Hypervisor Extensions
 838
 839 def FeatureStdExtH : RISCVExtension<1, 0, "Hypervisor">;
 840
 841 def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
 842                  AssemblerPredicate<(all_of FeatureStdExtH),
 843                                     "'H' (Hypervisor)">;
 844
 845 // Supervisor extensions
 846
 847 def FeatureStdExtSdext : RISCVExperimentalExtension<1, 0, "External debugger">;
 848
 849 def FeatureStdExtSdtrig : RISCVExperimentalExtension<1, 0, "Debugger triggers">;
 850
 851 def FeatureStdExtShgatpa
 852     : RISCVExtension<1, 0,
 853                      "SvNNx4 mode supported for all modes supported by satp, as well as Bare">;
 854 def FeatureStdExtShvsatpa
 855     : RISCVExtension<1, 0,
 856                      "vsatp supports all modes supported by satp">;
 857
 858 def FeatureStdExtSmaia
 859     : RISCVExtension<1, 0,
 860                      "Advanced Interrupt Architecture Machine Level">;
 861 def FeatureStdExtSsaia
 862     : RISCVExtension<1, 0,
 863                      "Advanced Interrupt Architecture Supervisor Level">;
 864
 865 def FeatureStdExtSmcsrind
 866     : RISCVExtension<1, 0, "Indirect CSR Access Machine Level">;
 867 def FeatureStdExtSscsrind
 868     : RISCVExtension<1, 0, "Indirect CSR Access Supervisor Level">;
 869
 870 def FeatureStdExtSmdbltrp
 871     : RISCVExtension<1, 0, "Double Trap Machine Level">;
 872 def FeatureStdExtSsdbltrp
 873     : RISCVExtension<1, 0, "Double Trap Supervisor Level">;
 874
 875 def FeatureStdExtSmepmp
 876     : RISCVExtension<1, 0, "Enhanced Physical Memory Protection">;
 877
 878 def FeatureStdExtSmrnmi
 879     : RISCVExtension<1, 0, "Resumable Non-Maskable Interrupts">;
 880 def HasStdExtSmrnmi : Predicate<"Subtarget->hasStdExtSmrnmi()">,
 881                        AssemblerPredicate<(all_of FeatureStdExtSmrnmi),
 882                            "'Smrnmi' (Resumable Non-Maskable Interrupts)">;
 883
 884 def FeatureStdExtSmcdeleg
 885     : RISCVExtension<1, 0, "Counter Delegation Machine Level">;
 886 def FeatureStdExtSsccfg
 887     : RISCVExtension<1, 0, "Counter Configuration Supervisor Level">;
 888
 889 def FeatureStdExtSsccptr
 890     : RISCVExtension<1, 0, "Main memory supports page table reads">;
 891
 892 def FeatureStdExtSscofpmf
 893     : RISCVExtension<1, 0, "Count Overflow and Mode-Based Filtering">;
 894
 895 def FeatureStdExtShcounterenw
 896     : RISCVExtension<1, 0,
 897                      "Support writeable hcounteren enable "
 898                      "bit for any hpmcounter that is not read-only zero">;
 899 def FeatureStdExtSscounterenw
 900     : RISCVExtension<1, 0,
 901                      "Support writeable scounteren enable "
 902                      "bit for any hpmcounter that is not read-only zero">;
 903
 904 def FeatureStdExtSmstateen
 905     : RISCVExtension<1, 0,
 906                      "Machine-mode view of the state-enable extension">;
 907 def FeatureStdExtSsstateen
 908     : RISCVExtension<1, 0,
 909                      "Supervisor-mode view of the state-enable extension">;
 910
 911 def FeatureStdExtSsstrict
 912     : RISCVExtension<1, 0,
 913                      "No non-conforming extensions are present">;
 914
 915 def FeatureStdExtSstc
 916     : RISCVExtension<1, 0, "Supervisor-mode timer interrupts">;
 917
 918 def FeatureStdExtSsqosid
 919     : RISCVExtension<1, 0, "Quality-of-Service (QoS) Identifiers">;
 920
 921 def FeatureStdExtShtvala
 922     : RISCVExtension<1, 0, "htval provides all needed values">;
 923 def FeatureStdExtShvstvala
 924     : RISCVExtension<1, 0, "vstval provides all needed values">;
 925 def FeatureStdExtSstvala
 926     : RISCVExtension<1, 0, "stval provides all needed values">;
 927
 928 def FeatureStdExtShvstvecd
 929     : RISCVExtension<1, 0, "vstvec supports Direct mode">;
 930 def FeatureStdExtSstvecd
 931     : RISCVExtension<1, 0, "stvec supports Direct mode">;
 932
 933 def FeatureStdExtSsu64xl
 934     : RISCVExtension<1, 0, "UXLEN=64 supported">;
 935
 936 def FeatureStdExtSvade
 937     : RISCVExtension<1, 0, "Raise exceptions on improper A/D bits">;
 938
 939 def FeatureStdExtSvadu
 940     : RISCVExtension<1, 0, "Hardware A/D updates">;
 941
 942 def FeatureStdExtSvbare
 943     : RISCVExtension<1, 0, "satp mode Bare supported">;
 944
 945 def FeatureStdExtSvinval
 946     : RISCVExtension<1, 0,
 947                      "Fine-Grained Address-Translation Cache Invalidation">;
 948 def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
 949                        AssemblerPredicate<(all_of FeatureStdExtSvinval),
 950                            "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
 951
 952 def FeatureStdExtSvnapot
 953     : RISCVExtension<1, 0, "NAPOT Translation Contiguity">;
 954
 955 def FeatureStdExtSvpbmt
 956     : RISCVExtension<1, 0, "Page-Based Memory Types">;
 957
 958 def FeatureStdExtSvvptc
 959     : RISCVExtension<1, 0,
 960                      "Obviating Memory-Management Instructions after Marking PTEs Valid">;
 961
 962 def FeatureStdExtSha
 963     : RISCVExtension<1, 0, "Augmented Hypervisor",
 964                      [FeatureStdExtH, FeatureStdExtSsstateen, FeatureStdExtShcounterenw,
 965                       FeatureStdExtShvstvala, FeatureStdExtShtvala, FeatureStdExtShvstvecd,
 966                       FeatureStdExtShvsatpa, FeatureStdExtShgatpa]>;
 967
 968 def FeatureStdExtSvukte
 969     : RISCVExperimentalExtension<0, 3,
 970                                  "Address-Independent Latency of User-Mode Faults to Supervisor Addresses">;
 971
 972 // Pointer Masking extensions
 973
 974 // A supervisor-level extension that provides pointer masking for the next lower
 975 // privilege mode (U-mode), and for VS- and VU-modes if the H extension is
 976 // present.
 977 def FeatureStdExtSsnpm
 978     : RISCVExtension<1, 0,
 979                      "Supervisor-level Pointer Masking for next lower privilege mode">;
 980
 981 // A machine-level extension that provides pointer masking for the next lower
 982 // privilege mode (S/HS if S-mode is implemented, or U-mode otherwise).
 983 def FeatureStdExtSmnpm
 984     : RISCVExtension<1, 0,
 985                      "Machine-level Pointer Masking for next lower privilege mode">;
 986
 987 // A machine-level extension that provides pointer masking for M-mode.
 988 def FeatureStdExtSmmpm
 989     : RISCVExtension<1, 0,
 990                      "Machine-level Pointer Masking for M-mode">;
 991
 992 // An extension that indicates that there is pointer-masking support available
 993 // in supervisor mode, with some facility provided in the supervisor execution
 994 // environment to control pointer masking.
 995 def FeatureStdExtSspm
 996     : RISCVExtension<1, 0,
 997                      "Indicates Supervisor-mode Pointer Masking">;
 998
 999 // An extension that indicates that there is pointer-masking support available
1000 // in user mode, with some facility provided in the application execution
1001 // environment to control pointer masking.
1002 def FeatureStdExtSupm
1003     : RISCVExtension<1, 0,
1004                      "Indicates User-mode Pointer Masking">;
1005
1006 def FeatureStdExtSmctr
1007     : RISCVExperimentalExtension<1, 0,
1008                                  "Control Transfer Records Machine Level",
1009                                  [FeatureStdExtSscsrind]>;
1010 def FeatureStdExtSsctr
1011     : RISCVExperimentalExtension<1, 0,
1012                                  "Control Transfer Records Supervisor Level",
1013                                  [FeatureStdExtSscsrind]>;
1014 def HasStdExtSmctrOrSsctr : Predicate<"Subtarget->hasStdExtSmctrOrSsctr()">,
1015                             AssemblerPredicate<(any_of FeatureStdExtSmctr, FeatureStdExtSsctr),
1016                                "'Smctr' (Control Transfer Records Machine Level) or "
1017                                "'Ssctr' (Control Transfer Records Supervisor Level)">;
1018
1019 //===----------------------------------------------------------------------===//
1020 // Vendor extensions
1021 //===----------------------------------------------------------------------===//
1022
1023 // Ventana Extenions
1024
1025 def FeatureVendorXVentanaCondOps
1026     : RISCVExtension<1, 0, "Ventana Conditional Ops">;
1027 def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">,
1028                                AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps),
1029                                    "'XVentanaCondOps' (Ventana Conditional Ops)">;
1030
1031 // T-Head Extensions
1032
1033 def FeatureVendorXTHeadBa
1034     : RISCVExtension<1, 0,
1035                      "T-Head address calculation instructions">;
1036 def HasVendorXTHeadBa : Predicate<"Subtarget->hasVendorXTHeadBa()">,
1037                         AssemblerPredicate<(all_of FeatureVendorXTHeadBa),
1038                             "'XTHeadBa' (T-Head address calculation instructions)">;
1039
1040 def FeatureVendorXTHeadBb
1041     : RISCVExtension<1, 0,
1042                      "T-Head basic bit-manipulation instructions">;
1043 def HasVendorXTHeadBb : Predicate<"Subtarget->hasVendorXTHeadBb()">,
1044                         AssemblerPredicate<(all_of FeatureVendorXTHeadBb),
1045                             "'XTHeadBb' (T-Head basic bit-manipulation instructions)">;
1046
1047 def FeatureVendorXTHeadBs
1048     : RISCVExtension<1, 0,
1049                      "T-Head single-bit instructions">;
1050 def HasVendorXTHeadBs : Predicate<"Subtarget->hasVendorXTHeadBs()">,
1051                         AssemblerPredicate<(all_of FeatureVendorXTHeadBs),
1052                             "'XTHeadBs' (T-Head single-bit instructions)">;
1053
1054 def FeatureVendorXTHeadCondMov
1055     : RISCVExtension<1, 0,
1056                      "T-Head conditional move instructions">;
1057 def HasVendorXTHeadCondMov : Predicate<"Subtarget->hasVendorXTHeadCondMov()">,
1058                              AssemblerPredicate<(all_of FeatureVendorXTHeadCondMov),
1059                                  "'XTHeadCondMov' (T-Head conditional move instructions)">;
1060
1061 def FeatureVendorXTHeadCmo
1062     : RISCVExtension<1, 0,
1063                      "T-Head cache management instructions">;
1064 def HasVendorXTHeadCmo : Predicate<"Subtarget->hasVendorXTHeadCmo()">,
1065                          AssemblerPredicate<(all_of FeatureVendorXTHeadCmo),
1066                              "'XTHeadCmo' (T-Head cache management instructions)">;
1067
1068 def FeatureVendorXTHeadFMemIdx
1069     : RISCVExtension<1, 0,
1070                      "T-Head FP Indexed Memory Operations">;
1071 def HasVendorXTHeadFMemIdx : Predicate<"Subtarget->hasVendorXTHeadFMemIdx()">,
1072                              AssemblerPredicate<(all_of FeatureVendorXTHeadFMemIdx),
1073                                  "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)">;
1074
1075 def FeatureVendorXTHeadMac
1076     : RISCVExtension<1, 0,
1077                      "T-Head Multiply-Accumulate Instructions">;
1078 def HasVendorXTHeadMac : Predicate<"Subtarget->hasVendorXTHeadMac()">,
1079                          AssemblerPredicate<(all_of FeatureVendorXTHeadMac),
1080                              "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)">;
1081
1082 def FeatureVendorXTHeadMemIdx
1083     : RISCVExtension<1, 0,
1084                      "T-Head Indexed Memory Operations">;
1085 def HasVendorXTHeadMemIdx : Predicate<"Subtarget->hasVendorXTHeadMemIdx()">,
1086                             AssemblerPredicate<(all_of FeatureVendorXTHeadMemIdx),
1087                                 "'XTHeadMemIdx' (T-Head Indexed Memory Operations)">;
1088
1089 def FeatureVendorXTHeadMemPair
1090     : RISCVExtension<1, 0,
1091                      "T-Head two-GPR Memory Operations">;
1092 def HasVendorXTHeadMemPair : Predicate<"Subtarget->hasVendorXTHeadMemPair()">,
1093                              AssemblerPredicate<(all_of FeatureVendorXTHeadMemPair),
1094                                  "'XTHeadMemPair' (T-Head two-GPR Memory Operations)">;
1095
1096 def FeatureVendorXTHeadSync
1097     : RISCVExtension<1, 0,
1098                      "T-Head multicore synchronization instructions">;
1099 def HasVendorXTHeadSync : Predicate<"Subtarget->hasVendorXTHeadSync()">,
1100                           AssemblerPredicate<(all_of FeatureVendorXTHeadSync),
1101                               "'XTHeadSync' (T-Head multicore synchronization instructions)">;
1102
1103 def FeatureVendorXTHeadVdot
1104     : RISCVExtension<1, 0,
1105                      "T-Head Vector Extensions for Dot",
1106                      [FeatureStdExtV]>;
1107 def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
1108                           AssemblerPredicate<(all_of FeatureVendorXTHeadVdot),
1109                               "'XTHeadVdot' (T-Head Vector Extensions for Dot)">;
1110
1111 // SiFive Extensions
1112
1113 def FeatureVendorXSfvcp
1114     : RISCVExtension<1, 0,
1115                      "SiFive Custom Vector Coprocessor Interface Instructions",
1116                      [FeatureStdExtZve32x]>;
1117 def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">,
1118                       AssemblerPredicate<(all_of FeatureVendorXSfvcp),
1119                           "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">;
1120
1121 def FeatureVendorXSfvqmaccdod
1122     : RISCVExtension<1, 0,
1123                      "SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)",
1124                      [FeatureStdExtZve32x]>;
1125 def HasVendorXSfvqmaccdod
1126     : Predicate<"Subtarget->hasVendorXSfvqmaccdod()">,
1127       AssemblerPredicate<(all_of FeatureVendorXSfvqmaccdod),
1128                          "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))">;
1129
1130 def FeatureVendorXSfvqmaccqoq
1131     : RISCVExtension<1, 0,
1132                      "SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)",
1133                      [FeatureStdExtZve32x]>;
1134 def HasVendorXSfvqmaccqoq
1135     : Predicate<"Subtarget->hasVendorXSfvqmaccqoq()">,
1136       AssemblerPredicate<(all_of FeatureVendorXSfvqmaccqoq),
1137                          "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))">;
1138
1139 def FeatureVendorXSfvfwmaccqqq
1140     : RISCVExtension<1, 0,
1141                      "SiFive Matrix Multiply Accumulate Instruction and 4-by-4)",
1142                      [FeatureStdExtZvfbfmin]>;
1143 def HasVendorXSfvfwmaccqqq
1144     : Predicate<"Subtarget->hasVendorXSfvfwmaccqqq()">,
1145       AssemblerPredicate<(all_of FeatureVendorXSfvfwmaccqqq),
1146                          "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))">;
1147
1148 def FeatureVendorXSfvfnrclipxfqf
1149     : RISCVExtension<1, 0,
1150                      "SiFive FP32-to-int8 Ranged Clip Instructions",
1151                      [FeatureStdExtZve32f]>;
1152 def HasVendorXSfvfnrclipxfqf
1153     : Predicate<"Subtarget->hasVendorXSfvfnrclipxfqf()">,
1154       AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf),
1155                          "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">;
1156
1157 def FeatureVendorXSiFivecdiscarddlone
1158     : RISCVExtension<1, 0,
1159                      "SiFive sf.cdiscard.d.l1 Instruction", []>;
1160 def HasVendorXSiFivecdiscarddlone
1161     : Predicate<"Subtarget->hasVendorXSiFivecdiscarddlone()">,
1162       AssemblerPredicate<(all_of FeatureVendorXSiFivecdiscarddlone),
1163                          "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)">;
1164
1165 def FeatureVendorXSiFivecflushdlone
1166     : RISCVExtension<1, 0,
1167                      "SiFive sf.cflush.d.l1 Instruction", []>;
1168 def HasVendorXSiFivecflushdlone
1169     : Predicate<"Subtarget->hasVendorXSiFivecflushdlone()">,
1170       AssemblerPredicate<(all_of FeatureVendorXSiFivecflushdlone),
1171                          "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)">;
1172
1173 def FeatureVendorXSfcease
1174     : RISCVExtension<1, 0,
1175                      "SiFive sf.cease Instruction", []>;
1176 def HasVendorXSfcease
1177     : Predicate<"Subtarget->hasVendorXSfcease()">,
1178       AssemblerPredicate<(all_of FeatureVendorXSfcease),
1179                          "'XSfcease' (SiFive sf.cease Instruction)">;
1180
1181 // Core-V Extensions
1182
1183 def FeatureVendorXCVelw
1184    : RISCVExtension<1, 0, "CORE-V Event Load Word">;
1185 def HasVendorXCVelw
1186    : Predicate<"Subtarget->hasVendorXCVelw()">,
1187      AssemblerPredicate<(any_of FeatureVendorXCVelw),
1188                         "'XCVelw' (CORE-V Event Load Word)">;
1189
1190 def FeatureVendorXCVbitmanip
1191     : RISCVExtension<1, 0, "CORE-V Bit Manipulation">;
1192 def HasVendorXCVbitmanip
1193     : Predicate<"Subtarget->hasVendorXCVbitmanip()">,
1194       AssemblerPredicate<(all_of FeatureVendorXCVbitmanip),
1195                          "'XCVbitmanip' (CORE-V Bit Manipulation)">;
1196
1197 def FeatureVendorXCVmac
1198     : RISCVExtension<1, 0, "CORE-V Multiply-Accumulate">;
1199 def HasVendorXCVmac
1200     : Predicate<"Subtarget->hasVendorXCVmac()">,
1201       AssemblerPredicate<(all_of FeatureVendorXCVmac),
1202                          "'XCVmac' (CORE-V Multiply-Accumulate)">;
1203
1204 def FeatureVendorXCVmem
1205     : RISCVExtension<1, 0, "CORE-V Post-incrementing Load & Store">;
1206 def HasVendorXCVmem
1207     : Predicate<"Subtarget->hasVendorXCVmem()">,
1208       AssemblerPredicate<(any_of FeatureVendorXCVmem),
1209                          "'XCVmem' (CORE-V Post-incrementing Load & Store)">;
1210
1211 def FeatureVendorXCValu
1212     : RISCVExtension<1, 0, "CORE-V ALU Operations">;
1213 def HasVendorXCValu
1214     : Predicate<"Subtarget->hasVendorXCValu()">,
1215       AssemblerPredicate<(all_of FeatureVendorXCValu),
1216                          "'XCValu' (CORE-V ALU Operations)">;
1217
1218 def FeatureVendorXCVsimd
1219     : RISCVExtension<1, 0, "CORE-V SIMD ALU">;
1220 def HasVendorXCVsimd
1221     : Predicate<"Subtarget->hasVendorXCVsimd()">,
1222       AssemblerPredicate<(any_of FeatureVendorXCVsimd),
1223                          "'XCVsimd' (CORE-V SIMD ALU)">;
1224
1225 def FeatureVendorXCVbi
1226     : RISCVExtension<1, 0, "CORE-V Immediate Branching">;
1227 def HasVendorXCVbi
1228     : Predicate<"Subtarget->hasVendorXCVbi()">,
1229       AssemblerPredicate<(all_of FeatureVendorXCVbi),
1230                          "'XCVbi' (CORE-V Immediate Branching)">;
1231
1232 // WCH / Nanjing Qinheng Microelectronics Extension(s)
1233
1234 def FeatureVendorXwchc
1235     : RISCVExtension<2, 2,
1236                      "WCH/QingKe additional compressed opcodes">;
1237 def HasVendorXwchc
1238     : Predicate<"Subtarget->hasVendorXwchc()">,
1239       AssemblerPredicate<(all_of FeatureVendorXwchc),
1240                          "'Xwchc' (WCH/QingKe additional compressed opcodes)">;
1241
1242 // Qualcomm Extension(s)
1243
1244 def FeatureVendorXqcicsr
1245     : RISCVExperimentalExtension<0, 2, "Qualcomm uC CSR Extension">;
1246 def HasVendorXqcicsr
1247     : Predicate<"Subtarget->hasVendorXqcicsr()">,
1248       AssemblerPredicate<(all_of FeatureVendorXqcicsr),
1249                          "'Xqcicsr' (Qualcomm uC CSR Extension)">;
1250
1251 def FeatureVendorXqcisls
1252     : RISCVExperimentalExtension<0, 2,
1253                                  "Qualcomm uC Scaled Load Store Extension">;
1254 def HasVendorXqcisls
1255     : Predicate<"Subtarget->hasVendorXqcisls()">,
1256       AssemblerPredicate<(all_of FeatureVendorXqcisls),
1257                          "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)">;
1258
1259 def FeatureVendorXqcia
1260     : RISCVExperimentalExtension<0, 2, "Qualcomm uC Arithmetic Extension">;
1261 def HasVendorXqcia
1262     : Predicate<"Subtarget->hasVendorXqcia()">,
1263       AssemblerPredicate<(all_of FeatureVendorXqcia),
1264                          "'Xqcia' (Qualcomm uC Arithmetic Extension)">;
1265
1266 def FeatureVendorXqcics
1267     : RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Select Extension">;
1268 def HasVendorXqcics
1269     : Predicate<"Subtarget->hasVendorXqcics()">,
1270       AssemblerPredicate<(all_of FeatureVendorXqcics),
1271                          "'Xqcics' (Qualcomm uC Conditional Select Extension)">;
1272
1273 def FeatureVendorXqcilsm
1274     : RISCVExperimentalExtension<0, 2,
1275                                  "Qualcomm uC Load Store Multiple Extension">;
1276 def HasVendorXqcilsm
1277     : Predicate<"Subtarget->hasVendorXqcilsm()">,
1278       AssemblerPredicate<(all_of FeatureVendorXqcilsm),
1279                          "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)">;
1280
1281 def FeatureVendorXqciac
1282     : RISCVExperimentalExtension<0, 2, "Qualcomm uC Load-Store Address Calculation Extension",
1283                                  [FeatureStdExtZca]>;
1284 def HasVendorXqciac
1285     : Predicate<"Subtarget->hasVendorXqciac()">,
1286       AssemblerPredicate<(all_of FeatureVendorXqciac),
1287                          "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)">;
1288
1289 def FeatureVendorXqcicli
1290     : RISCVExperimentalExtension<0, 2,
1291                                  "Qualcomm uC Conditional Load Immediate Extension">;
1292 def HasVendorXqcicli
1293     : Predicate<"Subtarget->hasVendorXqcicli()">,
1294       AssemblerPredicate<(all_of FeatureVendorXqcicli),
1295                          "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)">;
1296
1297 def FeatureVendorXqcicm
1298     : RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Move Extension",
1299                                  [FeatureStdExtZca]>;
1300 def HasVendorXqcicm
1301     : Predicate<"Subtarget->hasVendorXqcicm()">,
1302       AssemblerPredicate<(all_of FeatureVendorXqcicm),
1303                          "'Xqcicm' (Qualcomm uC Conditional Move Extension)">;
1304
1305 //===----------------------------------------------------------------------===//
1306 // LLVM specific features and extensions
1307 //===----------------------------------------------------------------------===//
1308
1309 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
1310 // tuning CPU names.
1311 def Feature32Bit
1312     : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
1313 def Feature64Bit
1314     : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;
1315 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
1316              AssemblerPredicate<(all_of Feature64Bit),
1317                                 "RV64I Base Instruction Set">;
1318 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
1319              AssemblerPredicate<(all_of (not Feature64Bit)),
1320                                 "RV32I Base Instruction Set">;
1321
1322 defvar RV32 = DefaultMode;
1323 def RV64           : HwMode<"+64bit", [IsRV64]>;
1324
1325 def FeatureRelax
1326     : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
1327                        "Enable Linker relaxation.">;
1328
1329 foreach i = {1-31} in
1330   def FeatureReserveX#i :
1331       SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
1332                        "true", "Reserve X"#i>;
1333
1334 def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
1335                                           "true", "Enable save/restore.">;
1336
1337 def FeatureNoTrailingSeqCstFence : SubtargetFeature<"no-trailing-seq-cst-fence",
1338                                           "EnableTrailingSeqCstFence",
1339                                           "false",
1340                                           "Disable trailing fence for seq-cst store.">;
1341
1342 def FeatureUnalignedScalarMem
1343    : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",
1344                       "true", "Has reasonably performant unaligned scalar "
1345                       "loads and stores">;
1346
1347 def FeatureUnalignedVectorMem
1348    : SubtargetFeature<"unaligned-vector-mem", "EnableUnalignedVectorMem",
1349                       "true", "Has reasonably performant unaligned vector "
1350                       "loads and stores">;
1351
1352 def TunePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
1353     "UsePostRAScheduler", "true", "Schedule again after register allocation">;
1354
1355 def TuneDisableLatencySchedHeuristic
1356     : SubtargetFeature<"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
1357                        "Disable latency scheduling heuristic">;
1358
1359 def TunePredictableSelectIsExpensive
1360     : SubtargetFeature<"predictable-select-expensive", "PredictableSelectIsExpensive", "true",
1361                        "Prefer likely predicted branches over selects">;
1362
1363 def TuneOptimizedZeroStrideLoad
1364    : SubtargetFeature<"optimized-zero-stride-load", "HasOptimizedZeroStrideLoad",
1365                       "true", "Optimized (perform fewer memory operations)"
1366                       "zero-stride vector load">;
1367
1368 foreach nf = {2-8} in
1369   def TuneOptimizedNF#nf#SegmentLoadStore :
1370       SubtargetFeature<"optimized-nf"#nf#"-segment-load-store",
1371                        "HasOptimizedNF"#nf#"SegmentLoadStore",
1372                        "true", "vlseg"#nf#"eN.v and vsseg"#nf#"eN.v are"
1373                        "implemented as a wide memory op and shuffle">;
1374
1375 def Experimental
1376    : SubtargetFeature<"experimental", "HasExperimental",
1377                       "true", "Experimental intrinsics">;
1378
1379 // Some vector hardware implementations do not process all VLEN bits in parallel
1380 // and instead split over multiple cycles. DLEN refers to the datapath width
1381 // that can be done in parallel.
1382 def TuneDLenFactor2
1383    : SubtargetFeature<"dlen-factor-2", "DLenFactor2", "true",
1384                       "Vector unit DLEN(data path width) is half of VLEN">;
1385
1386 def TuneNoDefaultUnroll
1387     : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
1388                        "Disable default unroll preference.">;
1389
1390 // SiFive 7 is able to fuse integer ALU operations with a preceding branch
1391 // instruction.
1392 def TuneShortForwardBranchOpt
1393     : SubtargetFeature<"short-forward-branch-opt", "HasShortForwardBranchOpt",
1394                        "true", "Enable short forward branch optimization">;
1395 def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">;
1396 def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">;
1397
1398 // Some subtargets require a S2V transfer buffer to move scalars into vectors.
1399 // FIXME: Forming .vx/.vf/.wx/.wf can reduce register pressure.
1400 def TuneNoSinkSplatOperands
1401     : SubtargetFeature<"no-sink-splat-operands", "SinkSplatOperands",
1402                        "false", "Disable sink splat operands to enable .vx, .vf,"
1403                        ".wx, and .wf instructions">;
1404
1405 def TunePreferWInst
1406     : SubtargetFeature<"prefer-w-inst", "PreferWInst", "true",
1407                        "Prefer instructions with W suffix">;
1408
1409 def TuneConditionalCompressedMoveFusion
1410     : SubtargetFeature<"conditional-cmv-fusion", "HasConditionalCompressedMoveFusion",
1411                        "true", "Enable branch+c.mv fusion">;
1412 def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">;
1413 def NoConditionalMoveFusion  : Predicate<"!Subtarget->hasConditionalMoveFusion()">;
1414
1415 def TuneMIPSP8700
1416     : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "MIPSP8700",
1417                        "MIPS p8700 processor">;
1418
1419 def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
1420                                    "SiFive 7-Series processors">;
1421
1422 def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
1423                                          "Ventana Veyron-Series processors">;
1424
1425 def TuneVXRMPipelineFlush : SubtargetFeature<"vxrm-pipeline-flush", "HasVXRMPipelineFlush",
1426                                              "true", "VXRM writes causes pipeline flush">;
1427
1428 // Assume that lock-free native-width atomics are available, even if the target
1429 // and operating system combination would not usually provide them. The user
1430 // is responsible for providing any necessary __sync implementations. Code
1431 // built with this feature is not ABI-compatible with code built without this
1432 // feature, if atomic variables are exposed across the ABI boundary.
1433 def FeatureForcedAtomics : SubtargetFeature<
1434     "forced-atomics", "HasForcedAtomics", "true",
1435     "Assume that lock-free native-width atomics are available">;
1436 def HasAtomicLdSt
1437     : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">;
1438
1439 def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
1440     "AllowTaggedGlobals",
1441     "true", "Use an instruction sequence for taking the address of a global "
1442     "that allows a memory tag in the upper address bits">;