llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td

   1 //==- RISCVSchedSyntacoreSCR1.td - Syntacore SCR1 Scheduling Definitions --------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 //===----------------------------------------------------------------------===//
  10
  11 // SCR1: https://github.com/syntacore/scr1
  12
  13 // This model covers SYNTACORE_SCR1_CFG_RV32IMC_MAX configuration (syntacore-scr1-max).
  14 // SYNTACORE_SCR1_CFG_RV32IC_BASE (syntacore-scr1-base) configuration has essentially
  15 // same scheduling characteristics.
  16
  17 // SCR1 is single-issue in-order processor
  18 def SyntacoreSCR1Model : SchedMachineModel {
  19   let MicroOpBufferSize = 0;
  20   let IssueWidth = 1;
  21   let LoadLatency = 2;
  22   let MispredictPenalty = 3;
  23   let CompleteModel = 0;
  24   let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
  25                              HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
  26                              HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
  27                              HasVInstructions];
  28 }
  29
  30 let SchedModel = SyntacoreSCR1Model in {
  31
  32 let BufferSize = 0 in {
  33 def SCR1_ALU : ProcResource<1>;
  34 def SCR1_LSU : ProcResource<1>;
  35 def SCR1_MUL : ProcResource<1>;
  36 def SCR1_DIV : ProcResource<1>;
  37 def SCR1_CFU : ProcResource<1>;
  38 }
  39
  40 // Branching
  41 def : WriteRes<WriteJmp, [SCR1_CFU]>;
  42 def : WriteRes<WriteJal, [SCR1_CFU]>;
  43 def : WriteRes<WriteJalr, [SCR1_CFU]>;
  44
  45 // Integer arithmetic and logic
  46 def : WriteRes<WriteIALU32, [SCR1_ALU]>;
  47 def : WriteRes<WriteIALU, [SCR1_ALU]>;
  48 def : WriteRes<WriteShiftImm32, [SCR1_ALU]>;
  49 def : WriteRes<WriteShiftImm, [SCR1_ALU]>;
  50 def : WriteRes<WriteShiftReg32, [SCR1_ALU]>;
  51 def : WriteRes<WriteShiftReg, [SCR1_ALU]>;
  52
  53 // Integer multiplication: single-cycle multiplier in SCR1_CFG_RV32IMC_MAX
  54 def : WriteRes<WriteIMul, [SCR1_MUL]>;
  55 def : WriteRes<WriteIMul32, [SCR1_MUL]>;
  56
  57 // Integer division/remainder: latency 33, inverse throughput 33
  58 let Latency = 33, ReleaseAtCycles = [33] in {
  59 def : WriteRes<WriteIDiv32, [SCR1_DIV]>;
  60 def : WriteRes<WriteIDiv, [SCR1_DIV]>;
  61 def : WriteRes<WriteIRem32, [SCR1_DIV]>;
  62 def : WriteRes<WriteIRem, [SCR1_DIV]>;
  63 }
  64
  65 // Load/store instructions on SCR1 have latency 2 and inverse throughput 2
  66 // (SCR1_CFG_RV32IMC_MAX includes TCM)
  67 let Latency = 2, ReleaseAtCycles=[2] in {
  68 // Memory
  69 def : WriteRes<WriteSTB, [SCR1_LSU]>;
  70 def : WriteRes<WriteSTH, [SCR1_LSU]>;
  71 def : WriteRes<WriteSTW, [SCR1_LSU]>;
  72 def : WriteRes<WriteSTD, [SCR1_LSU]>;
  73 def : WriteRes<WriteLDB, [SCR1_LSU]>;
  74 def : WriteRes<WriteLDH, [SCR1_LSU]>;
  75 def : WriteRes<WriteLDW, [SCR1_LSU]>;
  76 def : WriteRes<WriteLDD, [SCR1_LSU]>;
  77 }
  78
  79 // Others
  80 def : WriteRes<WriteCSR, []>;
  81 def : WriteRes<WriteNop, []>;
  82
  83 def : InstRW<[WriteIALU], (instrs COPY)>;
  84
  85 //===----------------------------------------------------------------------===//
  86 // Bypasses (none)
  87 def : ReadAdvance<ReadJmp, 0>;
  88 def : ReadAdvance<ReadJalr, 0>;
  89 def : ReadAdvance<ReadCSR, 0>;
  90 def : ReadAdvance<ReadStoreData, 0>;
  91 def : ReadAdvance<ReadMemBase, 0>;
  92 def : ReadAdvance<ReadIALU, 0>;
  93 def : ReadAdvance<ReadIALU32, 0>;
  94 def : ReadAdvance<ReadShiftImm, 0>;
  95 def : ReadAdvance<ReadShiftImm32, 0>;
  96 def : ReadAdvance<ReadShiftReg, 0>;
  97 def : ReadAdvance<ReadShiftReg32, 0>;
  98 def : ReadAdvance<ReadIDiv, 0>;
  99 def : ReadAdvance<ReadIDiv32, 0>;
 100 def : ReadAdvance<ReadIRem, 0>;
 101 def : ReadAdvance<ReadIRem32, 0>;
 102 def : ReadAdvance<ReadIMul, 0>;
 103 def : ReadAdvance<ReadIMul32, 0>;
 104
 105 //===----------------------------------------------------------------------===//
 106 // Unsupported extensions
 107 defm : UnsupportedSchedA;
 108 defm : UnsupportedSchedD;
 109 defm : UnsupportedSchedF;
 110 defm : UnsupportedSchedSFB;
 111 defm : UnsupportedSchedV;
 112 defm : UnsupportedSchedZabha;
 113 defm : UnsupportedSchedZba;
 114 defm : UnsupportedSchedZbb;
 115 defm : UnsupportedSchedZbc;
 116 defm : UnsupportedSchedZbs;
 117 defm : UnsupportedSchedZbkb;
 118 defm : UnsupportedSchedZbkx;
 119 defm : UnsupportedSchedZfa;
 120 defm : UnsupportedSchedZfh;
 121 defm : UnsupportedSchedXsfvcp;
 122 defm : UnsupportedSchedZvk;
 123 }