llvm/lib/Target/RISCV/RISCVSubtarget.cpp

   1 //===-- RISCVSubtarget.cpp - RISC-V Subtarget Information -----------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the RISC-V specific subclass of TargetSubtargetInfo.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "RISCVSubtarget.h"
  14 #include "GISel/RISCVCallLowering.h"
  15 #include "GISel/RISCVLegalizerInfo.h"
  16 #include "RISCV.h"
  17 #include "RISCVFrameLowering.h"
  18 #include "RISCVSelectionDAGInfo.h"
  19 #include "RISCVTargetMachine.h"
  20 #include "llvm/CodeGen/MacroFusion.h"
  21 #include "llvm/CodeGen/ScheduleDAGMutation.h"
  22 #include "llvm/MC/TargetRegistry.h"
  23 #include "llvm/Support/ErrorHandling.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "riscv-subtarget"
  28
  29 #define GET_SUBTARGETINFO_TARGET_DESC
  30 #define GET_SUBTARGETINFO_CTOR
  31 #include "RISCVGenSubtargetInfo.inc"
  32
  33 #define GET_RISCV_MACRO_FUSION_PRED_IMPL
  34 #include "RISCVGenMacroFusion.inc"
  35
  36 namespace llvm::RISCVTuneInfoTable {
  37
  38 #define GET_RISCVTuneInfoTable_IMPL
  39 #include "RISCVGenSearchableTables.inc"
  40 } // namespace llvm::RISCVTuneInfoTable
  41
  42 static cl::opt<unsigned> RVVVectorLMULMax(
  43     "riscv-v-fixed-length-vector-lmul-max",
  44     cl::desc("The maximum LMUL value to use for fixed length vectors. "
  45              "Fractional LMUL values are not supported."),
  46     cl::init(8), cl::Hidden);
  47
  48 static cl::opt<bool> RISCVDisableUsingConstantPoolForLargeInts(
  49     "riscv-disable-using-constant-pool-for-large-ints",
  50     cl::desc("Disable using constant pool for large integers."),
  51     cl::init(false), cl::Hidden);
  52
  53 static cl::opt<unsigned> RISCVMaxBuildIntsCost(
  54     "riscv-max-build-ints-cost",
  55     cl::desc("The maximum cost used for building integers."), cl::init(0),
  56     cl::Hidden);
  57
  58 static cl::opt<bool> UseAA("riscv-use-aa", cl::init(true),
  59                            cl::desc("Enable the use of AA during codegen."));
  60
  61 static cl::opt<unsigned> RISCVMinimumJumpTableEntries(
  62     "riscv-min-jump-table-entries", cl::Hidden,
  63     cl::desc("Set minimum number of entries to use a jump table on RISCV"));
  64
  65 void RISCVSubtarget::anchor() {}
  66
  67 RISCVSubtarget &
  68 RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
  69                                                 StringRef TuneCPU, StringRef FS,
  70                                                 StringRef ABIName) {
  71   // Determine default and user-specified characteristics
  72   bool Is64Bit = TT.isArch64Bit();
  73   if (CPU.empty() || CPU == "generic")
  74     CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
  75
  76   if (TuneCPU.empty())
  77     TuneCPU = CPU;
  78
  79   TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo(TuneCPU);
  80   // If there is no TuneInfo for this CPU, we fail back to generic.
  81   if (!TuneInfo)
  82     TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo("generic");
  83   assert(TuneInfo && "TuneInfo shouldn't be nullptr!");
  84
  85   ParseSubtargetFeatures(CPU, TuneCPU, FS);
  86   TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
  87   RISCVFeatures::validate(TT, getFeatureBits());
  88   return *this;
  89 }
  90
  91 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
  92                                StringRef TuneCPU, StringRef FS,
  93                                StringRef ABIName, unsigned RVVVectorBitsMin,
  94                                unsigned RVVVectorBitsMax,
  95                                const TargetMachine &TM)
  96     : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
  97       RVVVectorBitsMin(RVVVectorBitsMin), RVVVectorBitsMax(RVVVectorBitsMax),
  98       FrameLowering(
  99           initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
 100       InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
 101   TSInfo = std::make_unique<RISCVSelectionDAGInfo>();
 102 }
 103
 104 RISCVSubtarget::~RISCVSubtarget() = default;
 105
 106 const SelectionDAGTargetInfo *RISCVSubtarget::getSelectionDAGInfo() const {
 107   return TSInfo.get();
 108 }
 109
 110 const CallLowering *RISCVSubtarget::getCallLowering() const {
 111   if (!CallLoweringInfo)
 112     CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
 113   return CallLoweringInfo.get();
 114 }
 115
 116 InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
 117   if (!InstSelector) {
 118     InstSelector.reset(createRISCVInstructionSelector(
 119         *static_cast<const RISCVTargetMachine *>(&TLInfo.getTargetMachine()),
 120         *this, *getRegBankInfo()));
 121   }
 122   return InstSelector.get();
 123 }
 124
 125 const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
 126   if (!Legalizer)
 127     Legalizer.reset(new RISCVLegalizerInfo(*this));
 128   return Legalizer.get();
 129 }
 130
 131 const RISCVRegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
 132   if (!RegBankInfo)
 133     RegBankInfo.reset(new RISCVRegisterBankInfo(getHwMode()));
 134   return RegBankInfo.get();
 135 }
 136
 137 bool RISCVSubtarget::useConstantPoolForLargeInts() const {
 138   return !RISCVDisableUsingConstantPoolForLargeInts;
 139 }
 140
 141 unsigned RISCVSubtarget::getMaxBuildIntsCost() const {
 142   // Loading integer from constant pool needs two instructions (the reason why
 143   // the minimum cost is 2): an address calculation instruction and a load
 144   // instruction. Usually, address calculation and instructions used for
 145   // building integers (addi, slli, etc.) can be done in one cycle, so here we
 146   // set the default cost to (LoadLatency + 1) if no threshold is provided.
 147   return RISCVMaxBuildIntsCost == 0
 148              ? getSchedModel().LoadLatency + 1
 149              : std::max<unsigned>(2, RISCVMaxBuildIntsCost);
 150 }
 151
 152 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
 153   assert(hasVInstructions() &&
 154          "Tried to get vector length without Zve or V extension support!");
 155
 156   // ZvlLen specifies the minimum required vlen. The upper bound provided by
 157   // riscv-v-vector-bits-max should be no less than it.
 158   if (RVVVectorBitsMax != 0 && RVVVectorBitsMax < ZvlLen)
 159     report_fatal_error("riscv-v-vector-bits-max specified is lower "
 160                        "than the Zvl*b limitation");
 161
 162   return RVVVectorBitsMax;
 163 }
 164
 165 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
 166   assert(hasVInstructions() &&
 167          "Tried to get vector length without Zve or V extension support!");
 168
 169   if (RVVVectorBitsMin == -1U)
 170     return ZvlLen;
 171
 172   // ZvlLen specifies the minimum required vlen. The lower bound provided by
 173   // riscv-v-vector-bits-min should be no less than it.
 174   if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
 175     report_fatal_error("riscv-v-vector-bits-min specified is lower "
 176                        "than the Zvl*b limitation");
 177
 178   return RVVVectorBitsMin;
 179 }
 180
 181 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
 182   assert(hasVInstructions() &&
 183          "Tried to get vector length without Zve or V extension support!");
 184   assert(RVVVectorLMULMax <= 8 &&
 185          llvm::has_single_bit<uint32_t>(RVVVectorLMULMax) &&
 186          "V extension requires a LMUL to be at most 8 and a power of 2!");
 187   return llvm::bit_floor(std::clamp<unsigned>(RVVVectorLMULMax, 1, 8));
 188 }
 189
 190 bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
 191   return hasVInstructions() &&
 192          getMinRVVVectorSizeInBits() >= RISCV::RVVBitsPerBlock;
 193 }
 194
 195 bool RISCVSubtarget::enableSubRegLiveness() const { return true; }
 196
 197 bool RISCVSubtarget::enableMachinePipeliner() const {
 198   return getSchedModel().hasInstrSchedModel();
 199 }
 200
 201   /// Enable use of alias analysis during code generation (during MI
 202   /// scheduling, DAGCombine, etc.).
 203 bool RISCVSubtarget::useAA() const { return UseAA; }
 204
 205 unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
 206   return RISCVMinimumJumpTableEntries.getNumOccurrences() > 0
 207              ? RISCVMinimumJumpTableEntries
 208              : TuneInfo->MinimumJumpTableEntries;
 209 }
 210
 211 void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
 212                                          unsigned NumRegionInstrs) const {
 213   // Do bidirectional scheduling since it provides a more balanced scheduling
 214   // leading to better performance. This will increase compile time.
 215   Policy.OnlyTopDown = false;
 216   Policy.OnlyBottomUp = false;
 217
 218   // Disabling the latency heuristic can reduce the number of spills/reloads but
 219   // will cause some regressions on some cores.
 220   Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
 221
 222   // Spilling is generally expensive on all RISC-V cores, so always enable
 223   // register-pressure tracking. This will increase compile time.
 224   Policy.ShouldTrackPressure = true;
 225 }
 226
 227 void RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
 228                                                unsigned NumRegionInstrs) const {
 229   MISched::Direction PostRASchedDirection = getPostRASchedDirection();
 230   if (PostRASchedDirection == MISched::TopDown) {
 231     Policy.OnlyTopDown = true;
 232     Policy.OnlyBottomUp = false;
 233   } else if (PostRASchedDirection == MISched::BottomUp) {
 234     Policy.OnlyTopDown = false;
 235     Policy.OnlyBottomUp = true;
 236   } else if (PostRASchedDirection == MISched::Bidirectional) {
 237     Policy.OnlyTopDown = false;
 238     Policy.OnlyBottomUp = false;
 239   }
 240 }