llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

   1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines an instruction selector for the SPARC target.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "SparcTargetMachine.h"
  14 #include "llvm/CodeGen/MachineRegisterInfo.h"
  15 #include "llvm/CodeGen/SelectionDAGISel.h"
  16 #include "llvm/Support/ErrorHandling.h"
  17 using namespace llvm;
  18
  19 #define DEBUG_TYPE "sparc-isel"
  20 #define PASS_NAME "SPARC DAG->DAG Pattern Instruction Selection"
  21
  22 //===----------------------------------------------------------------------===//
  23 // Instruction Selector Implementation
  24 //===----------------------------------------------------------------------===//
  25
  26 //===--------------------------------------------------------------------===//
  27 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
  28 /// instructions for SelectionDAG operations.
  29 ///
  30 namespace {
  31 class SparcDAGToDAGISel : public SelectionDAGISel {
  32   /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
  33   /// make the right decision when generating code for different targets.
  34   const SparcSubtarget *Subtarget = nullptr;
  35
  36 public:
  37   SparcDAGToDAGISel() = delete;
  38
  39   explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(tm) {}
  40
  41   bool runOnMachineFunction(MachineFunction &MF) override {
  42     Subtarget = &MF.getSubtarget<SparcSubtarget>();
  43     return SelectionDAGISel::runOnMachineFunction(MF);
  44   }
  45
  46   void Select(SDNode *N) override;
  47
  48   // Complex Pattern Selectors.
  49   bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
  50   bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
  51
  52   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
  53   /// inline asm expressions.
  54   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
  55                                     InlineAsm::ConstraintCode ConstraintID,
  56                                     std::vector<SDValue> &OutOps) override;
  57
  58   // Include the pieces autogenerated from the target description.
  59 #include "SparcGenDAGISel.inc"
  60
  61 private:
  62   SDNode* getGlobalBaseReg();
  63   bool tryInlineAsm(SDNode *N);
  64 };
  65
  66 class SparcDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
  67 public:
  68   static char ID;
  69   explicit SparcDAGToDAGISelLegacy(SparcTargetMachine &tm)
  70       : SelectionDAGISelLegacy(ID, std::make_unique<SparcDAGToDAGISel>(tm)) {}
  71 };
  72 }  // end anonymous namespace
  73
  74 char SparcDAGToDAGISelLegacy::ID = 0;
  75
  76 INITIALIZE_PASS(SparcDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
  77
  78 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
  79   Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
  80   return CurDAG->getRegister(GlobalBaseReg,
  81                              TLI->getPointerTy(CurDAG->getDataLayout()))
  82       .getNode();
  83 }
  84
  85 bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
  86                                      SDValue &Base, SDValue &Offset) {
  87   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
  88     Base = CurDAG->getTargetFrameIndex(
  89         FIN->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));
  90     Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
  91     return true;
  92   }
  93   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
  94       Addr.getOpcode() == ISD::TargetGlobalAddress ||
  95       Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
  96     return false;  // direct calls.
  97
  98   if (Addr.getOpcode() == ISD::ADD) {
  99     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
 100       if (isInt<13>(CN->getSExtValue())) {
 101         if (FrameIndexSDNode *FIN =
 102                 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
 103           // Constant offset from frame ref.
 104           Base = CurDAG->getTargetFrameIndex(
 105               FIN->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));
 106         } else {
 107           Base = Addr.getOperand(0);
 108         }
 109         Offset = CurDAG->getSignedTargetConstant(CN->getSExtValue(),
 110                                                  SDLoc(Addr), MVT::i32);
 111         return true;
 112       }
 113     }
 114     if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
 115       Base = Addr.getOperand(1);
 116       Offset = Addr.getOperand(0).getOperand(0);
 117       return true;
 118     }
 119     if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
 120       Base = Addr.getOperand(0);
 121       Offset = Addr.getOperand(1).getOperand(0);
 122       return true;
 123     }
 124   }
 125   Base = Addr;
 126   Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
 127   return true;
 128 }
 129
 130 bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
 131   if (Addr.getOpcode() == ISD::FrameIndex) return false;
 132   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
 133       Addr.getOpcode() == ISD::TargetGlobalAddress ||
 134       Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
 135     return false;  // direct calls.
 136
 137   if (Addr.getOpcode() == ISD::ADD) {
 138     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
 139       if (isInt<13>(CN->getSExtValue()))
 140         return false;  // Let the reg+imm pattern catch this!
 141     if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
 142         Addr.getOperand(1).getOpcode() == SPISD::Lo)
 143       return false;  // Let the reg+imm pattern catch this!
 144     R1 = Addr.getOperand(0);
 145     R2 = Addr.getOperand(1);
 146     return true;
 147   }
 148
 149   R1 = Addr;
 150   R2 = CurDAG->getRegister(SP::G0, TLI->getPointerTy(CurDAG->getDataLayout()));
 151   return true;
 152 }
 153
 154
 155 // Re-assemble i64 arguments split up in SelectionDAGBuilder's
 156 // visitInlineAsm / GetRegistersForValue functions.
 157 //
 158 // Note: This function was copied from, and is essentially identical
 159 // to ARMISelDAGToDAG::SelectInlineAsm. It is very unfortunate that
 160 // such hacking-up is necessary; a rethink of how inline asm operands
 161 // are handled may be in order to make doing this more sane.
 162 //
 163 // TODO: fix inline asm support so I can simply tell it that 'i64'
 164 // inputs to asm need to be allocated to the IntPair register type,
 165 // and have that work. Then, delete this function.
 166 bool SparcDAGToDAGISel::tryInlineAsm(SDNode *N){
 167   std::vector<SDValue> AsmNodeOperands;
 168   InlineAsm::Flag Flag;
 169   bool Changed = false;
 170   unsigned NumOps = N->getNumOperands();
 171
 172   // Normally, i64 data is bounded to two arbitrary GPRs for "%r"
 173   // constraint.  However, some instructions (e.g. ldd/std) require
 174   // (even/even+1) GPRs.
 175
 176   // So, here, we check for this case, and mutate the inlineasm to use
 177   // a single IntPair register instead, which guarantees such even/odd
 178   // placement.
 179
 180   SDLoc dl(N);
 181   SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps - 1) : SDValue();
 182
 183   SmallVector<bool, 8> OpChanged;
 184   // Glue node will be appended late.
 185   for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
 186     SDValue op = N->getOperand(i);
 187     AsmNodeOperands.push_back(op);
 188
 189     if (i < InlineAsm::Op_FirstOperand)
 190       continue;
 191
 192     if (const auto *C = dyn_cast<ConstantSDNode>(N->getOperand(i)))
 193       Flag = InlineAsm::Flag(C->getZExtValue());
 194     else
 195       continue;
 196
 197     // Immediate operands to inline asm in the SelectionDAG are modeled with
 198     // two operands. The first is a constant of value InlineAsm::Kind::Imm, and
 199     // the second is a constant with the value of the immediate. If we get here
 200     // and we have a Kind::Imm, skip the next operand, and continue.
 201     if (Flag.isImmKind()) {
 202       SDValue op = N->getOperand(++i);
 203       AsmNodeOperands.push_back(op);
 204       continue;
 205     }
 206
 207     const unsigned NumRegs = Flag.getNumOperandRegisters();
 208     if (NumRegs)
 209       OpChanged.push_back(false);
 210
 211     unsigned DefIdx = 0;
 212     bool IsTiedToChangedOp = false;
 213     // If it's a use that is tied with a previous def, it has no
 214     // reg class constraint.
 215     if (Changed && Flag.isUseOperandTiedToDef(DefIdx))
 216       IsTiedToChangedOp = OpChanged[DefIdx];
 217
 218     if (!Flag.isRegUseKind() && !Flag.isRegDefKind() &&
 219         !Flag.isRegDefEarlyClobberKind())
 220       continue;
 221
 222     unsigned RC;
 223     const bool HasRC = Flag.hasRegClassConstraint(RC);
 224     if ((!IsTiedToChangedOp && (!HasRC || RC != SP::IntRegsRegClassID))
 225         || NumRegs != 2)
 226       continue;
 227
 228     assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
 229     SDValue V0 = N->getOperand(i+1);
 230     SDValue V1 = N->getOperand(i+2);
 231     Register Reg0 = cast<RegisterSDNode>(V0)->getReg();
 232     Register Reg1 = cast<RegisterSDNode>(V1)->getReg();
 233     SDValue PairedReg;
 234     MachineRegisterInfo &MRI = MF->getRegInfo();
 235
 236     if (Flag.isRegDefKind() || Flag.isRegDefEarlyClobberKind()) {
 237       // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
 238       // the original GPRs.
 239
 240       Register GPVR = MRI.createVirtualRegister(&SP::IntPairRegClass);
 241       PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);
 242       SDValue Chain = SDValue(N,0);
 243
 244       SDNode *GU = N->getGluedUser();
 245       SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::v2i32,
 246                                                Chain.getValue(1));
 247
 248       // Extract values from a GPRPair reg and copy to the original GPR reg.
 249       SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl, MVT::i32,
 250                                                     RegCopy);
 251       SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32,
 252                                                     RegCopy);
 253       SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
 254                                         RegCopy.getValue(1));
 255       SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
 256
 257       // Update the original glue user.
 258       std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
 259       Ops.push_back(T1.getValue(1));
 260       CurDAG->UpdateNodeOperands(GU, Ops);
 261     } else {
 262       // For Kind  == InlineAsm::Kind::RegUse, we first copy two GPRs into a
 263       // GPRPair and then pass the GPRPair to the inline asm.
 264       SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
 265
 266       // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
 267       SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
 268                                           Chain.getValue(1));
 269       SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
 270                                           T0.getValue(1));
 271       SDValue Pair = SDValue(
 272           CurDAG->getMachineNode(
 273               TargetOpcode::REG_SEQUENCE, dl, MVT::v2i32,
 274               {
 275                   CurDAG->getTargetConstant(SP::IntPairRegClassID, dl,
 276                                             MVT::i32),
 277                   T0,
 278                   CurDAG->getTargetConstant(SP::sub_even, dl, MVT::i32),
 279                   T1,
 280                   CurDAG->getTargetConstant(SP::sub_odd, dl, MVT::i32),
 281               }),
 282           0);
 283
 284       // Copy REG_SEQ into a GPRPair-typed VR and replace the original two
 285       // i32 VRs of inline asm with it.
 286       Register GPVR = MRI.createVirtualRegister(&SP::IntPairRegClass);
 287       PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);
 288       Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair, T1.getValue(1));
 289
 290       AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
 291       Glue = Chain.getValue(1);
 292     }
 293
 294     Changed = true;
 295
 296     if(PairedReg.getNode()) {
 297       OpChanged[OpChanged.size() -1 ] = true;
 298       Flag = InlineAsm::Flag(Flag.getKind(), 1 /* RegNum*/);
 299       if (IsTiedToChangedOp)
 300         Flag.setMatchingOp(DefIdx);
 301       else
 302         Flag.setRegClass(SP::IntPairRegClassID);
 303       // Replace the current flag.
 304       AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
 305           Flag, dl, MVT::i32);
 306       // Add the new register node and skip the original two GPRs.
 307       AsmNodeOperands.push_back(PairedReg);
 308       // Skip the next two GPRs.
 309       i += 2;
 310     }
 311   }
 312
 313   if (Glue.getNode())
 314     AsmNodeOperands.push_back(Glue);
 315   if (!Changed)
 316     return false;
 317
 318   SelectInlineAsmMemoryOperands(AsmNodeOperands, SDLoc(N));
 319
 320   SDValue New = CurDAG->getNode(N->getOpcode(), SDLoc(N),
 321       CurDAG->getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
 322   New->setNodeId(-1);
 323   ReplaceNode(N, New.getNode());
 324   return true;
 325 }
 326
 327 void SparcDAGToDAGISel::Select(SDNode *N) {
 328   SDLoc dl(N);
 329   if (N->isMachineOpcode()) {
 330     N->setNodeId(-1);
 331     return;   // Already selected.
 332   }
 333
 334   switch (N->getOpcode()) {
 335   default: break;
 336   case ISD::INLINEASM:
 337   case ISD::INLINEASM_BR: {
 338     if (tryInlineAsm(N))
 339       return;
 340     break;
 341   }
 342   case SPISD::GLOBAL_BASE_REG:
 343     ReplaceNode(N, getGlobalBaseReg());
 344     return;
 345
 346   case ISD::SDIV:
 347   case ISD::UDIV: {
 348     // sdivx / udivx handle 64-bit divides.
 349     if (N->getValueType(0) == MVT::i64)
 350       break;
 351     // FIXME: should use a custom expander to expose the SRA to the dag.
 352     SDValue DivLHS = N->getOperand(0);
 353     SDValue DivRHS = N->getOperand(1);
 354
 355     // Set the Y register to the high-part.
 356     SDValue TopPart;
 357     if (N->getOpcode() == ISD::SDIV) {
 358       TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
 359                                    CurDAG->getTargetConstant(31, dl, MVT::i32)),
 360                         0);
 361     } else {
 362       TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
 363     }
 364     TopPart = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SP::Y, TopPart,
 365                                    SDValue())
 366                   .getValue(1);
 367
 368     // FIXME: Handle div by immediate.
 369     unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
 370     CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
 371     return;
 372   }
 373   }
 374
 375   SelectCode(N);
 376 }
 377
 378
 379 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
 380 /// inline asm expressions.
 381 bool SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(
 382     const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
 383     std::vector<SDValue> &OutOps) {
 384   SDValue Op0, Op1;
 385   switch (ConstraintID) {
 386   default: return true;
 387   case InlineAsm::ConstraintCode::o:
 388   case InlineAsm::ConstraintCode::m: // memory
 389     if (!SelectADDRrr(Op, Op0, Op1))
 390       SelectADDRri(Op, Op0, Op1);
 391     break;
 392   }
 393
 394   OutOps.push_back(Op0);
 395   OutOps.push_back(Op1);
 396   return false;
 397 }
 398
 399 /// createSparcISelDag - This pass converts a legalized DAG into a
 400 /// SPARC-specific DAG, ready for instruction scheduling.
 401 ///
 402 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
 403   return new SparcDAGToDAGISelLegacy(TM);
 404 }