llvm/lib/Target/Sparc/SparcTargetMachine.cpp

   1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 #include "SparcTargetMachine.h"
  13 #include "LeonPasses.h"
  14 #include "Sparc.h"
  15 #include "SparcMachineFunctionInfo.h"
  16 #include "SparcTargetObjectFile.h"
  17 #include "TargetInfo/SparcTargetInfo.h"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/CodeGen/TargetPassConfig.h"
  20 #include "llvm/MC/TargetRegistry.h"
  21 #include <optional>
  22 using namespace llvm;
  23
  24 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget() {
  25   // Register the target.
  26   RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget());
  27   RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target());
  28   RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget());
  29
  30   PassRegistry &PR = *PassRegistry::getPassRegistry();
  31   initializeSparcDAGToDAGISelLegacyPass(PR);
  32   initializeErrataWorkaroundPass(PR);
  33 }
  34
  35 static cl::opt<bool>
  36     BranchRelaxation("sparc-enable-branch-relax", cl::Hidden, cl::init(true),
  37                      cl::desc("Relax out of range conditional branches"));
  38
  39 static std::string computeDataLayout(const Triple &T, bool is64Bit) {
  40   // Sparc is typically big endian, but some are little.
  41   std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
  42   Ret += "-m:e";
  43
  44   // Some ABIs have 32bit pointers.
  45   if (!is64Bit)
  46     Ret += "-p:32:32";
  47
  48   // Alignments for 64 bit integers.
  49   Ret += "-i64:64";
  50
  51   // Alignments for 128 bit integers.
  52   // This is not specified in the ABI document but is the de facto standard.
  53   Ret += "-i128:128";
  54
  55   // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
  56   // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
  57   if (is64Bit)
  58     Ret += "-n32:64";
  59   else
  60     Ret += "-f128:64-n32";
  61
  62   if (is64Bit)
  63     Ret += "-S128";
  64   else
  65     Ret += "-S64";
  66
  67   return Ret;
  68 }
  69
  70 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
  71   return RM.value_or(Reloc::Static);
  72 }
  73
  74 // Code models. Some only make sense for 64-bit code.
  75 //
  76 // SunCC  Reloc   CodeModel  Constraints
  77 // abs32  Static  Small      text+data+bss linked below 2^32 bytes
  78 // abs44  Static  Medium     text+data+bss linked below 2^44 bytes
  79 // abs64  Static  Large      text smaller than 2^31 bytes
  80 // pic13  PIC_    Small      GOT < 2^13 bytes
  81 // pic32  PIC_    Medium     GOT < 2^32 bytes
  82 //
  83 // All code models require that the text segment is smaller than 2GB.
  84 static CodeModel::Model
  85 getEffectiveSparcCodeModel(std::optional<CodeModel::Model> CM, Reloc::Model RM,
  86                            bool Is64Bit, bool JIT) {
  87   if (CM) {
  88     if (*CM == CodeModel::Tiny)
  89       report_fatal_error("Target does not support the tiny CodeModel", false);
  90     if (*CM == CodeModel::Kernel)
  91       report_fatal_error("Target does not support the kernel CodeModel", false);
  92     return *CM;
  93   }
  94   if (Is64Bit) {
  95     if (JIT)
  96       return CodeModel::Large;
  97     return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
  98   }
  99   return CodeModel::Small;
 100 }
 101
 102 /// Create an ILP32 architecture model
 103 SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
 104                                        StringRef CPU, StringRef FS,
 105                                        const TargetOptions &Options,
 106                                        std::optional<Reloc::Model> RM,
 107                                        std::optional<CodeModel::Model> CM,
 108                                        CodeGenOptLevel OL, bool JIT,
 109                                        bool is64bit)
 110     : CodeGenTargetMachineImpl(
 111           T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
 112           getEffectiveRelocModel(RM),
 113           getEffectiveSparcCodeModel(CM, getEffectiveRelocModel(RM), is64bit,
 114                                      JIT),
 115           OL),
 116       TLOF(std::make_unique<SparcELFTargetObjectFile>()), is64Bit(is64bit) {
 117   initAsmInfo();
 118 }
 119
 120 SparcTargetMachine::~SparcTargetMachine() = default;
 121
 122 const SparcSubtarget *
 123 SparcTargetMachine::getSubtargetImpl(const Function &F) const {
 124   Attribute CPUAttr = F.getFnAttribute("target-cpu");
 125   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
 126   Attribute FSAttr = F.getFnAttribute("target-features");
 127
 128   std::string CPU =
 129       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
 130   std::string TuneCPU =
 131       TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
 132   std::string FS =
 133       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
 134
 135   // FIXME: This is related to the code below to reset the target options,
 136   // we need to know whether or not the soft float flag is set on the
 137   // function, so we can enable it as a subtarget feature.
 138   bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
 139
 140   if (softFloat)
 141     FS += FS.empty() ? "+soft-float" : ",+soft-float";
 142
 143   auto &I = SubtargetMap[CPU + FS];
 144   if (!I) {
 145     // This needs to be done before we create a new subtarget since any
 146     // creation will depend on the TM and the code generation flags on the
 147     // function that reside in TargetOptions.
 148     resetTargetOptions(F);
 149     I = std::make_unique<SparcSubtarget>(CPU, TuneCPU, FS, *this,
 150                                          this->is64Bit);
 151   }
 152   return I.get();
 153 }
 154
 155 MachineFunctionInfo *SparcTargetMachine::createMachineFunctionInfo(
 156     BumpPtrAllocator &Allocator, const Function &F,
 157     const TargetSubtargetInfo *STI) const {
 158   return SparcMachineFunctionInfo::create<SparcMachineFunctionInfo>(Allocator,
 159                                                                     F, STI);
 160 }
 161
 162 namespace {
 163 /// Sparc Code Generator Pass Configuration Options.
 164 class SparcPassConfig : public TargetPassConfig {
 165 public:
 166   SparcPassConfig(SparcTargetMachine &TM, PassManagerBase &PM)
 167     : TargetPassConfig(TM, PM) {}
 168
 169   SparcTargetMachine &getSparcTargetMachine() const {
 170     return getTM<SparcTargetMachine>();
 171   }
 172
 173   void addIRPasses() override;
 174   bool addInstSelector() override;
 175   void addPreEmitPass() override;
 176 };
 177 } // namespace
 178
 179 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
 180   return new SparcPassConfig(*this, PM);
 181 }
 182
 183 void SparcPassConfig::addIRPasses() {
 184   addPass(createAtomicExpandLegacyPass());
 185
 186   TargetPassConfig::addIRPasses();
 187 }
 188
 189 bool SparcPassConfig::addInstSelector() {
 190   addPass(createSparcISelDag(getSparcTargetMachine()));
 191   return false;
 192 }
 193
 194 void SparcPassConfig::addPreEmitPass(){
 195   if (BranchRelaxation)
 196     addPass(&BranchRelaxationPassID);
 197
 198   addPass(createSparcDelaySlotFillerPass());
 199   addPass(new InsertNOPLoad());
 200   addPass(new DetectRoundChange());
 201   addPass(new FixAllFDIVSQRT());
 202   addPass(new ErrataWorkaround());
 203 }
 204
 205 void SparcV8TargetMachine::anchor() { }
 206
 207 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
 208                                            StringRef CPU, StringRef FS,
 209                                            const TargetOptions &Options,
 210                                            std::optional<Reloc::Model> RM,
 211                                            std::optional<CodeModel::Model> CM,
 212                                            CodeGenOptLevel OL, bool JIT)
 213     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
 214
 215 void SparcV9TargetMachine::anchor() { }
 216
 217 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
 218                                            StringRef CPU, StringRef FS,
 219                                            const TargetOptions &Options,
 220                                            std::optional<Reloc::Model> RM,
 221                                            std::optional<CodeModel::Model> CM,
 222                                            CodeGenOptLevel OL, bool JIT)
 223     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
 224
 225 void SparcelTargetMachine::anchor() {}
 226
 227 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
 228                                            StringRef CPU, StringRef FS,
 229                                            const TargetOptions &Options,
 230                                            std::optional<Reloc::Model> RM,
 231                                            std::optional<CodeModel::Model> CM,
 232                                            CodeGenOptLevel OL, bool JIT)
 233     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}