llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp

   1 //===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "SystemZMCTargetDesc.h"
  10 #include "SystemZGNUInstPrinter.h"
  11 #include "SystemZHLASMInstPrinter.h"
  12 #include "SystemZMCAsmInfo.h"
  13 #include "SystemZTargetStreamer.h"
  14 #include "TargetInfo/SystemZTargetInfo.h"
  15 #include "llvm/MC/MCContext.h"
  16 #include "llvm/MC/MCDwarf.h"
  17 #include "llvm/MC/MCInst.h"
  18 #include "llvm/MC/MCInstrAnalysis.h"
  19 #include "llvm/MC/MCInstrInfo.h"
  20 #include "llvm/MC/MCRegisterInfo.h"
  21 #include "llvm/MC/MCStreamer.h"
  22 #include "llvm/MC/MCSubtargetInfo.h"
  23 #include "llvm/MC/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define GET_INSTRINFO_MC_DESC
  28 #define ENABLE_INSTR_PREDICATE_VERIFIER
  29 #include "SystemZGenInstrInfo.inc"
  30
  31 #define GET_SUBTARGETINFO_MC_DESC
  32 #include "SystemZGenSubtargetInfo.inc"
  33
  34 #define GET_REGINFO_MC_DESC
  35 #include "SystemZGenRegisterInfo.inc"
  36
  37 const unsigned SystemZMC::GR32Regs[16] = {
  38   SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
  39   SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L,
  40   SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L,
  41   SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L
  42 };
  43
  44 const unsigned SystemZMC::GRH32Regs[16] = {
  45   SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H,
  46   SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H,
  47   SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H,
  48   SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H
  49 };
  50
  51 const unsigned SystemZMC::GR64Regs[16] = {
  52   SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D,
  53   SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D,
  54   SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D,
  55   SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D
  56 };
  57
  58 const unsigned SystemZMC::GR128Regs[16] = {
  59   SystemZ::R0Q, 0, SystemZ::R2Q, 0,
  60   SystemZ::R4Q, 0, SystemZ::R6Q, 0,
  61   SystemZ::R8Q, 0, SystemZ::R10Q, 0,
  62   SystemZ::R12Q, 0, SystemZ::R14Q, 0
  63 };
  64
  65 const unsigned SystemZMC::FP32Regs[16] = {
  66   SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
  67   SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
  68   SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
  69   SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S
  70 };
  71
  72 const unsigned SystemZMC::FP64Regs[16] = {
  73   SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
  74   SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
  75   SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
  76   SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D
  77 };
  78
  79 const unsigned SystemZMC::FP128Regs[16] = {
  80   SystemZ::F0Q, SystemZ::F1Q, 0, 0,
  81   SystemZ::F4Q, SystemZ::F5Q, 0, 0,
  82   SystemZ::F8Q, SystemZ::F9Q, 0, 0,
  83   SystemZ::F12Q, SystemZ::F13Q, 0, 0
  84 };
  85
  86 const unsigned SystemZMC::VR32Regs[32] = {
  87   SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
  88   SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
  89   SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
  90   SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
  91   SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S,
  92   SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S,
  93   SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S,
  94   SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S
  95 };
  96
  97 const unsigned SystemZMC::VR64Regs[32] = {
  98   SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
  99   SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
 100   SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
 101   SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
 102   SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D,
 103   SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D,
 104   SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D,
 105   SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D
 106 };
 107
 108 const unsigned SystemZMC::VR128Regs[32] = {
 109   SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3,
 110   SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7,
 111   SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
 112   SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
 113   SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19,
 114   SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23,
 115   SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27,
 116   SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31
 117 };
 118
 119 const unsigned SystemZMC::AR32Regs[16] = {
 120   SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3,
 121   SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7,
 122   SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11,
 123   SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15
 124 };
 125
 126 const unsigned SystemZMC::CR64Regs[16] = {
 127   SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3,
 128   SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7,
 129   SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11,
 130   SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15
 131 };
 132
 133 unsigned SystemZMC::getFirstReg(unsigned Reg) {
 134   static unsigned Map[SystemZ::NUM_TARGET_REGS];
 135   static bool Initialized = false;
 136   if (!Initialized) {
 137     for (unsigned I = 0; I < 16; ++I) {
 138       Map[GR32Regs[I]] = I;
 139       Map[GRH32Regs[I]] = I;
 140       Map[GR64Regs[I]] = I;
 141       Map[GR128Regs[I]] = I;
 142       Map[FP128Regs[I]] = I;
 143       Map[AR32Regs[I]] = I;
 144     }
 145     for (unsigned I = 0; I < 32; ++I) {
 146       Map[VR32Regs[I]] = I;
 147       Map[VR64Regs[I]] = I;
 148       Map[VR128Regs[I]] = I;
 149     }
 150   }
 151   assert(Reg < SystemZ::NUM_TARGET_REGS);
 152   return Map[Reg];
 153 }
 154
 155 static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI,
 156                                          const Triple &TT,
 157                                          const MCTargetOptions &Options) {
 158   if (TT.isOSzOS())
 159     return new SystemZMCAsmInfoGOFF(TT);
 160
 161   MCAsmInfo *MAI = new SystemZMCAsmInfoELF(TT);
 162   MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
 163       nullptr, MRI.getDwarfRegNum(SystemZ::R15D, true),
 164       SystemZMC::ELFCFAOffsetFromInitialSP);
 165   MAI->addInitialFrameState(Inst);
 166   return MAI;
 167 }
 168
 169 static MCInstrInfo *createSystemZMCInstrInfo() {
 170   MCInstrInfo *X = new MCInstrInfo();
 171   InitSystemZMCInstrInfo(X);
 172   return X;
 173 }
 174
 175 static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) {
 176   MCRegisterInfo *X = new MCRegisterInfo();
 177   InitSystemZMCRegisterInfo(X, SystemZ::R14D);
 178   return X;
 179 }
 180
 181 static MCSubtargetInfo *
 182 createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
 183   return createSystemZMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
 184 }
 185
 186 static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
 187                                                  unsigned SyntaxVariant,
 188                                                  const MCAsmInfo &MAI,
 189                                                  const MCInstrInfo &MII,
 190                                                  const MCRegisterInfo &MRI) {
 191   if (SyntaxVariant == AD_HLASM)
 192     return new SystemZHLASMInstPrinter(MAI, MII, MRI);
 193
 194   return new SystemZGNUInstPrinter(MAI, MII, MRI);
 195 }
 196
 197 void SystemZTargetStreamer::emitConstantPools() {
 198   // Emit EXRL target instructions.
 199   if (EXRLTargets2Sym.empty())
 200     return;
 201   // Switch to the .text section.
 202   const MCObjectFileInfo &OFI = *Streamer.getContext().getObjectFileInfo();
 203   Streamer.switchSection(OFI.getTextSection());
 204   for (auto &I : EXRLTargets2Sym) {
 205     Streamer.emitLabel(I.second);
 206     const MCInstSTIPair &MCI_STI = I.first;
 207     Streamer.emitInstruction(MCI_STI.first, *MCI_STI.second);
 208   }
 209   EXRLTargets2Sym.clear();
 210 }
 211
 212 namespace {
 213 class SystemZTargetAsmStreamer : public SystemZTargetStreamer {
 214   formatted_raw_ostream &OS;
 215
 216 public:
 217   SystemZTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
 218       : SystemZTargetStreamer(S), OS(OS) {}
 219   void emitMachine(StringRef CPU) override {
 220     OS << "\t.machine " << CPU << "\n";
 221   }
 222 };
 223
 224 class SystemZTargetELFStreamer : public SystemZTargetStreamer {
 225 public:
 226   SystemZTargetELFStreamer(MCStreamer &S) : SystemZTargetStreamer(S) {}
 227   void emitMachine(StringRef CPU) override {}
 228 };
 229 } // end namespace
 230
 231 static MCTargetStreamer *createAsmTargetStreamer(MCStreamer &S,
 232                                                  formatted_raw_ostream &OS,
 233                                                  MCInstPrinter *InstPrint) {
 234   return new SystemZTargetAsmStreamer(S, OS);
 235 }
 236
 237 static MCTargetStreamer *
 238 createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
 239   return new SystemZTargetELFStreamer(S);
 240 }
 241
 242 static MCTargetStreamer *
 243 createNullTargetStreamer(MCStreamer &S) {
 244   return new SystemZTargetStreamer(S);
 245 }
 246
 247 static MCInstrAnalysis *createSystemZMCInstrAnalysis(const MCInstrInfo *Info) {
 248   return new MCInstrAnalysis(Info);
 249 }
 250
 251 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTargetMC() {
 252   // Register the MCAsmInfo.
 253   TargetRegistry::RegisterMCAsmInfo(getTheSystemZTarget(),
 254                                     createSystemZMCAsmInfo);
 255
 256   // Register the MCCodeEmitter.
 257   TargetRegistry::RegisterMCCodeEmitter(getTheSystemZTarget(),
 258                                         createSystemZMCCodeEmitter);
 259
 260   // Register the MCInstrInfo.
 261   TargetRegistry::RegisterMCInstrInfo(getTheSystemZTarget(),
 262                                       createSystemZMCInstrInfo);
 263
 264   // Register the MCRegisterInfo.
 265   TargetRegistry::RegisterMCRegInfo(getTheSystemZTarget(),
 266                                     createSystemZMCRegisterInfo);
 267
 268   // Register the MCSubtargetInfo.
 269   TargetRegistry::RegisterMCSubtargetInfo(getTheSystemZTarget(),
 270                                           createSystemZMCSubtargetInfo);
 271
 272   // Register the MCAsmBackend.
 273   TargetRegistry::RegisterMCAsmBackend(getTheSystemZTarget(),
 274                                        createSystemZMCAsmBackend);
 275
 276   // Register the MCInstPrinter.
 277   TargetRegistry::RegisterMCInstPrinter(getTheSystemZTarget(),
 278                                         createSystemZMCInstPrinter);
 279
 280   // Register the asm streamer.
 281   TargetRegistry::RegisterAsmTargetStreamer(getTheSystemZTarget(),
 282                                             createAsmTargetStreamer);
 283
 284   // Register the obj streamer
 285   TargetRegistry::RegisterObjectTargetStreamer(getTheSystemZTarget(),
 286                                                createObjectTargetStreamer);
 287
 288   // Register the null streamer
 289   TargetRegistry::RegisterNullTargetStreamer(getTheSystemZTarget(),
 290                                              createNullTargetStreamer);
 291
 292   // Register the MCInstrAnalysis.
 293   TargetRegistry::RegisterMCInstrAnalysis(getTheSystemZTarget(),
 294                                           createSystemZMCInstrAnalysis);
 295 }