llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h

   1 //===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
  10 #define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
  11
  12 #include "llvm/Support/DataTypes.h"
  13
  14 #include <memory>
  15
  16 namespace llvm {
  17
  18 class MCAsmBackend;
  19 class MCCodeEmitter;
  20 class MCContext;
  21 class MCInstrInfo;
  22 class MCObjectTargetWriter;
  23 class MCRegisterInfo;
  24 class MCSubtargetInfo;
  25 class MCTargetOptions;
  26 class Target;
  27
  28 namespace SystemZMC {
  29 // How many bytes are in the ABI-defined, caller-allocated part of
  30 // a stack frame.
  31 const int64_t ELFCallFrameSize = 160;
  32
  33 // The offset of the DWARF CFA from the incoming stack pointer.
  34 const int64_t ELFCFAOffsetFromInitialSP = ELFCallFrameSize;
  35
  36 // Maps of asm register numbers to LLVM register numbers, with 0 indicating
  37 // an invalid register.  In principle we could use 32-bit and 64-bit register
  38 // classes directly, provided that we relegated the GPR allocation order
  39 // in SystemZRegisterInfo.td to an AltOrder and left the default order
  40 // as %r0-%r15.  It seems better to provide the same interface for
  41 // all classes though.
  42 extern const unsigned GR32Regs[16];
  43 extern const unsigned GRH32Regs[16];
  44 extern const unsigned GR64Regs[16];
  45 extern const unsigned GR128Regs[16];
  46 extern const unsigned FP32Regs[16];
  47 extern const unsigned FP64Regs[16];
  48 extern const unsigned FP128Regs[16];
  49 extern const unsigned VR32Regs[32];
  50 extern const unsigned VR64Regs[32];
  51 extern const unsigned VR128Regs[32];
  52 extern const unsigned AR32Regs[16];
  53 extern const unsigned CR64Regs[16];
  54
  55 // Return the 0-based number of the first architectural register that
  56 // contains the given LLVM register.   E.g. R1D -> 1.
  57 unsigned getFirstReg(unsigned Reg);
  58
  59 // Return the given register as a GR64.
  60 inline unsigned getRegAsGR64(unsigned Reg) {
  61   return GR64Regs[getFirstReg(Reg)];
  62 }
  63
  64 // Return the given register as a low GR32.
  65 inline unsigned getRegAsGR32(unsigned Reg) {
  66   return GR32Regs[getFirstReg(Reg)];
  67 }
  68
  69 // Return the given register as a high GR32.
  70 inline unsigned getRegAsGRH32(unsigned Reg) {
  71   return GRH32Regs[getFirstReg(Reg)];
  72 }
  73
  74 // Return the given register as a VR128.
  75 inline unsigned getRegAsVR128(unsigned Reg) {
  76   return VR128Regs[getFirstReg(Reg)];
  77 }
  78 } // end namespace SystemZMC
  79
  80 MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
  81                                           MCContext &Ctx);
  82
  83 MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
  84                                         const MCSubtargetInfo &STI,
  85                                         const MCRegisterInfo &MRI,
  86                                         const MCTargetOptions &Options);
  87
  88 std::unique_ptr<MCObjectTargetWriter>
  89 createSystemZELFObjectWriter(uint8_t OSABI);
  90 std::unique_ptr<MCObjectTargetWriter> createSystemZGOFFObjectWriter();
  91 } // end namespace llvm
  92
  93 // Defines symbolic names for SystemZ registers.
  94 // This defines a mapping from register name to register number.
  95 #define GET_REGINFO_ENUM
  96 #include "SystemZGenRegisterInfo.inc"
  97
  98 // Defines symbolic names for the SystemZ instructions.
  99 #define GET_INSTRINFO_ENUM
 100 #define GET_INSTRINFO_MC_HELPER_DECLS
 101 #include "SystemZGenInstrInfo.inc"
 102
 103 #define GET_SUBTARGETINFO_ENUM
 104 #include "SystemZGenSubtargetInfo.inc"
 105
 106 #endif