1 //===-- SystemZ.td - Describe the SystemZ target machine -----*- tblgen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 // Target-independent interfaces which we are implementing
11 //===----------------------------------------------------------------------===//
13 include "llvm/Target/Target.td"
15 //===----------------------------------------------------------------------===//
16 // SystemZ subtarget features
17 //===----------------------------------------------------------------------===//
19 include "SystemZFeatures.td"
21 //===----------------------------------------------------------------------===//
22 // SystemZ subtarget scheduling models
23 //===----------------------------------------------------------------------===//
25 include "SystemZSchedule.td"
27 //===----------------------------------------------------------------------===//
28 // SystemZ supported processors
29 //===----------------------------------------------------------------------===//
31 include "SystemZProcessors.td"
33 //===----------------------------------------------------------------------===//
34 // Register file description
35 //===----------------------------------------------------------------------===//
37 include "SystemZRegisterInfo.td"
39 //===----------------------------------------------------------------------===//
40 // Calling convention description
41 //===----------------------------------------------------------------------===//
43 include "SystemZCallingConv.td"
45 //===----------------------------------------------------------------------===//
46 // Instruction descriptions
47 //===----------------------------------------------------------------------===//
49 include "SystemZOperators.td"
50 include "SystemZOperands.td"
51 include "SystemZPatterns.td"
52 include "SystemZInstrFormats.td"
53 include "SystemZInstrInfo.td"
54 include "SystemZInstrVector.td"
55 include "SystemZInstrFP.td"
56 include "SystemZInstrHFP.td"
57 include "SystemZInstrDFP.td"
58 include "SystemZInstrSystem.td"
60 def SystemZInstrInfo : InstrInfo { let guessInstructionProperties = 0; }
62 //===----------------------------------------------------------------------===//
64 //===----------------------------------------------------------------------===//
66 def SystemZAsmParser : AsmParser {
67 let ShouldEmitMatchRegisterName = 0;
70 def GNUAsmParserVariant : AsmParserVariant {
77 def HLASMAsmParserVariant : AsmParserVariant {
81 string Name = "hlasm";
84 //===----------------------------------------------------------------------===//
86 //===----------------------------------------------------------------------===//
88 // The SystemZ target supports two different syntaxes for emitting machine code.
89 def GNUAsmWriter : AsmWriter {
90 string AsmWriterClassName = "GNUInstPrinter";
93 def HLASMAsmWriter : AsmWriter {
94 string AsmWriterClassName = "HLASMInstPrinter";
98 //===----------------------------------------------------------------------===//
99 // Top-level target declaration
100 //===----------------------------------------------------------------------===//
102 def SystemZ : Target {
103 let InstructionSet = SystemZInstrInfo;
104 let AssemblyParsers = [SystemZAsmParser];
105 let AssemblyParserVariants = [GNUAsmParserVariant, HLASMAsmParserVariant];
106 let AssemblyWriters = [GNUAsmWriter, HLASMAsmWriter];
107 let AllowRegisterRenaming = 1;