llvm/lib/Target/SystemZ/SystemZShortenInst.cpp

   1 //===-- SystemZShortenInst.cpp - Instruction-shortening pass --------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This pass tries to replace instructions with shorter forms.  For example,
  10 // IILF can be replaced with LLILL or LLILH if the constant fits and if the
  11 // other 32 bits of the GR64 destination are not live.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "SystemZTargetMachine.h"
  16 #include "llvm/CodeGen/LiveRegUnits.h"
  17 #include "llvm/CodeGen/MachineFunctionPass.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19 #include "llvm/CodeGen/TargetRegisterInfo.h"
  20
  21 using namespace llvm;
  22
  23 #define DEBUG_TYPE "systemz-shorten-inst"
  24
  25 namespace {
  26 class SystemZShortenInst : public MachineFunctionPass {
  27 public:
  28   static char ID;
  29   SystemZShortenInst();
  30
  31   bool processBlock(MachineBasicBlock &MBB);
  32   bool runOnMachineFunction(MachineFunction &F) override;
  33   MachineFunctionProperties getRequiredProperties() const override {
  34     return MachineFunctionProperties().set(
  35         MachineFunctionProperties::Property::NoVRegs);
  36   }
  37
  38 private:
  39   bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
  40   bool shortenOn0(MachineInstr &MI, unsigned Opcode);
  41   bool shortenOn01(MachineInstr &MI, unsigned Opcode);
  42   bool shortenOn001(MachineInstr &MI, unsigned Opcode);
  43   bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
  44   bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
  45   bool shortenFusedFPOp(MachineInstr &MI, unsigned Opcode);
  46
  47   const SystemZInstrInfo *TII;
  48   const TargetRegisterInfo *TRI;
  49   LiveRegUnits LiveRegs;
  50 };
  51
  52 char SystemZShortenInst::ID = 0;
  53 } // end anonymous namespace
  54
  55 INITIALIZE_PASS(SystemZShortenInst, DEBUG_TYPE,
  56                 "SystemZ Instruction Shortening", false, false)
  57
  58 FunctionPass *llvm::createSystemZShortenInstPass(SystemZTargetMachine &TM) {
  59   return new SystemZShortenInst();
  60 }
  61
  62 SystemZShortenInst::SystemZShortenInst()
  63     : MachineFunctionPass(ID), TII(nullptr) {
  64   initializeSystemZShortenInstPass(*PassRegistry::getPassRegistry());
  65 }
  66
  67 // Tie operands if MI has become a two-address instruction.
  68 static void tieOpsIfNeeded(MachineInstr &MI) {
  69   if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 &&
  70       !MI.getOperand(0).isTied())
  71     MI.tieOperands(0, 1);
  72 }
  73
  74 // MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH
  75 // are the halfword immediate loads for the same word.  Try to use one of them
  76 // instead of IIxF.
  77 bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned LLIxL,
  78                                     unsigned LLIxH) {
  79   Register Reg = MI.getOperand(0).getReg();
  80   // The new opcode will clear the other half of the GR64 reg, so
  81   // cancel if that is live.
  82   unsigned thisSubRegIdx =
  83       (SystemZ::GRH32BitRegClass.contains(Reg) ? SystemZ::subreg_h32
  84                                                : SystemZ::subreg_l32);
  85   unsigned otherSubRegIdx =
  86       (thisSubRegIdx == SystemZ::subreg_l32 ? SystemZ::subreg_h32
  87                                             : SystemZ::subreg_l32);
  88   unsigned GR64BitReg =
  89       TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass);
  90   Register OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx);
  91   if (!LiveRegs.available(OtherReg))
  92     return false;
  93
  94   uint64_t Imm = MI.getOperand(1).getImm();
  95   if (SystemZ::isImmLL(Imm)) {
  96     MI.setDesc(TII->get(LLIxL));
  97     MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
  98     return true;
  99   }
 100   if (SystemZ::isImmLH(Imm)) {
 101     MI.setDesc(TII->get(LLIxH));
 102     MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
 103     MI.getOperand(1).setImm(Imm >> 16);
 104     return true;
 105   }
 106   return false;
 107 }
 108
 109 // Change MI's opcode to Opcode if register operand 0 has a 4-bit encoding.
 110 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) {
 111   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) {
 112     MI.setDesc(TII->get(Opcode));
 113     return true;
 114   }
 115   return false;
 116 }
 117
 118 // Change MI's opcode to Opcode if register operands 0 and 1 have a
 119 // 4-bit encoding.
 120 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) {
 121   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
 122       SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
 123     MI.setDesc(TII->get(Opcode));
 124     return true;
 125   }
 126   return false;
 127 }
 128
 129 // Change MI's opcode to Opcode if register operands 0, 1 and 2 have a
 130 // 4-bit encoding and if operands 0 and 1 are tied. Also ties op 0
 131 // with op 1, if MI becomes 2-address.
 132 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
 133   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
 134       MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
 135       SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
 136     MI.setDesc(TII->get(Opcode));
 137     tieOpsIfNeeded(MI);
 138     return true;
 139   }
 140   return false;
 141 }
 142
 143 // Calls shortenOn001 if CCLive is false. CC def operand is added in
 144 // case of success.
 145 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) {
 146   if (LiveRegs.available(SystemZ::CC) && shortenOn001(MI, Opcode)) {
 147     MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
 148       .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
 149     return true;
 150   }
 151   return false;
 152 }
 153
 154 // MI is a vector-style conversion instruction with the operand order:
 155 // destination, source, exact-suppress, rounding-mode.  If both registers
 156 // have a 4-bit encoding then change it to Opcode, which has operand order:
 157 // destination, rouding-mode, source, exact-suppress.
 158 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) {
 159   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
 160       SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
 161     MachineOperand Dest(MI.getOperand(0));
 162     MachineOperand Src(MI.getOperand(1));
 163     MachineOperand Suppress(MI.getOperand(2));
 164     MachineOperand Mode(MI.getOperand(3));
 165     MI.removeOperand(3);
 166     MI.removeOperand(2);
 167     MI.removeOperand(1);
 168     MI.removeOperand(0);
 169     MI.setDesc(TII->get(Opcode));
 170     MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
 171         .add(Dest)
 172         .add(Mode)
 173         .add(Src)
 174         .add(Suppress);
 175     return true;
 176   }
 177   return false;
 178 }
 179
 180 bool SystemZShortenInst::shortenFusedFPOp(MachineInstr &MI, unsigned Opcode) {
 181   MachineOperand &DstMO = MI.getOperand(0);
 182   MachineOperand &LHSMO = MI.getOperand(1);
 183   MachineOperand &RHSMO = MI.getOperand(2);
 184   MachineOperand &AccMO = MI.getOperand(3);
 185   if (SystemZMC::getFirstReg(DstMO.getReg()) < 16 &&
 186       SystemZMC::getFirstReg(LHSMO.getReg()) < 16 &&
 187       SystemZMC::getFirstReg(RHSMO.getReg()) < 16 &&
 188       SystemZMC::getFirstReg(AccMO.getReg()) < 16 &&
 189       DstMO.getReg() == AccMO.getReg()) {
 190     MachineOperand Lhs(LHSMO);
 191     MachineOperand Rhs(RHSMO);
 192     MachineOperand Src(AccMO);
 193     MI.removeOperand(3);
 194     MI.removeOperand(2);
 195     MI.removeOperand(1);
 196     MI.setDesc(TII->get(Opcode));
 197     MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
 198         .add(Src)
 199         .add(Lhs)
 200         .add(Rhs);
 201     return true;
 202   }
 203   return false;
 204 }
 205
 206 // Process all instructions in MBB.  Return true if something changed.
 207 bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {
 208   bool Changed = false;
 209
 210   // Set up the set of live registers at the end of MBB (live out)
 211   LiveRegs.clear();
 212   LiveRegs.addLiveOuts(MBB);
 213
 214   // Iterate backwards through the block looking for instructions to change.
 215   for (MachineInstr &MI : llvm::reverse(MBB)) {
 216     switch (MI.getOpcode()) {
 217     case SystemZ::IILF:
 218       Changed |= shortenIIF(MI, SystemZ::LLILL, SystemZ::LLILH);
 219       break;
 220
 221     case SystemZ::IIHF:
 222       Changed |= shortenIIF(MI, SystemZ::LLIHL, SystemZ::LLIHH);
 223       break;
 224
 225     case SystemZ::WFADB:
 226       Changed |= shortenOn001AddCC(MI, SystemZ::ADBR);
 227       break;
 228
 229     case SystemZ::WFASB:
 230       Changed |= shortenOn001AddCC(MI, SystemZ::AEBR);
 231       break;
 232
 233     case SystemZ::WFDDB:
 234       Changed |= shortenOn001(MI, SystemZ::DDBR);
 235       break;
 236
 237     case SystemZ::WFDSB:
 238       Changed |= shortenOn001(MI, SystemZ::DEBR);
 239       break;
 240
 241     case SystemZ::WFIDB:
 242       Changed |= shortenFPConv(MI, SystemZ::FIDBRA);
 243       break;
 244
 245     case SystemZ::WFISB:
 246       Changed |= shortenFPConv(MI, SystemZ::FIEBRA);
 247       break;
 248
 249     case SystemZ::WLDEB:
 250       Changed |= shortenOn01(MI, SystemZ::LDEBR);
 251       break;
 252
 253     case SystemZ::WLEDB:
 254       Changed |= shortenFPConv(MI, SystemZ::LEDBRA);
 255       break;
 256
 257     case SystemZ::WFMDB:
 258       Changed |= shortenOn001(MI, SystemZ::MDBR);
 259       break;
 260
 261     case SystemZ::WFMSB:
 262       Changed |= shortenOn001(MI, SystemZ::MEEBR);
 263       break;
 264
 265     case SystemZ::WFMADB:
 266       Changed |= shortenFusedFPOp(MI, SystemZ::MADBR);
 267       break;
 268
 269     case SystemZ::WFMASB:
 270       Changed |= shortenFusedFPOp(MI, SystemZ::MAEBR);
 271       break;
 272
 273     case SystemZ::WFMSDB:
 274       Changed |= shortenFusedFPOp(MI, SystemZ::MSDBR);
 275       break;
 276
 277     case SystemZ::WFMSSB:
 278       Changed |= shortenFusedFPOp(MI, SystemZ::MSEBR);
 279       break;
 280
 281     case SystemZ::WFLCDB:
 282       Changed |= shortenOn01(MI, SystemZ::LCDFR);
 283       break;
 284
 285     case SystemZ::WFLCSB:
 286       Changed |= shortenOn01(MI, SystemZ::LCDFR_32);
 287       break;
 288
 289     case SystemZ::WFLNDB:
 290       Changed |= shortenOn01(MI, SystemZ::LNDFR);
 291       break;
 292
 293     case SystemZ::WFLNSB:
 294       Changed |= shortenOn01(MI, SystemZ::LNDFR_32);
 295       break;
 296
 297     case SystemZ::WFLPDB:
 298       Changed |= shortenOn01(MI, SystemZ::LPDFR);
 299       break;
 300
 301     case SystemZ::WFLPSB:
 302       Changed |= shortenOn01(MI, SystemZ::LPDFR_32);
 303       break;
 304
 305     case SystemZ::WFSQDB:
 306       Changed |= shortenOn01(MI, SystemZ::SQDBR);
 307       break;
 308
 309     case SystemZ::WFSQSB:
 310       Changed |= shortenOn01(MI, SystemZ::SQEBR);
 311       break;
 312
 313     case SystemZ::WFSDB:
 314       Changed |= shortenOn001AddCC(MI, SystemZ::SDBR);
 315       break;
 316
 317     case SystemZ::WFSSB:
 318       Changed |= shortenOn001AddCC(MI, SystemZ::SEBR);
 319       break;
 320
 321     case SystemZ::WFCDB:
 322       Changed |= shortenOn01(MI, SystemZ::CDBR);
 323       break;
 324
 325     case SystemZ::WFCSB:
 326       Changed |= shortenOn01(MI, SystemZ::CEBR);
 327       break;
 328
 329     case SystemZ::WFKDB:
 330       Changed |= shortenOn01(MI, SystemZ::KDBR);
 331       break;
 332
 333     case SystemZ::WFKSB:
 334       Changed |= shortenOn01(MI, SystemZ::KEBR);
 335       break;
 336
 337     case SystemZ::VL32:
 338       // For z13 we prefer LDE over LE to avoid partial register dependencies.
 339       Changed |= shortenOn0(MI, SystemZ::LDE32);
 340       break;
 341
 342     case SystemZ::VST32:
 343       Changed |= shortenOn0(MI, SystemZ::STE);
 344       break;
 345
 346     case SystemZ::VL64:
 347       Changed |= shortenOn0(MI, SystemZ::LD);
 348       break;
 349
 350     case SystemZ::VST64:
 351       Changed |= shortenOn0(MI, SystemZ::STD);
 352       break;
 353
 354     default: {
 355       int TwoOperandOpcode = SystemZ::getTwoOperandOpcode(MI.getOpcode());
 356       if (TwoOperandOpcode == -1)
 357         break;
 358
 359       if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) &&
 360           (!MI.isCommutable() ||
 361            MI.getOperand(0).getReg() != MI.getOperand(2).getReg() ||
 362            !TII->commuteInstruction(MI, false, 1, 2)))
 363           break;
 364
 365       MI.setDesc(TII->get(TwoOperandOpcode));
 366       MI.tieOperands(0, 1);
 367       if (TwoOperandOpcode == SystemZ::SLL ||
 368           TwoOperandOpcode == SystemZ::SLA ||
 369           TwoOperandOpcode == SystemZ::SRL ||
 370           TwoOperandOpcode == SystemZ::SRA) {
 371         // These shifts only use the low 6 bits of the shift count.
 372         MachineOperand &ImmMO = MI.getOperand(3);
 373         ImmMO.setImm(ImmMO.getImm() & 0xfff);
 374       }
 375       Changed = true;
 376       break;
 377     }
 378     }
 379
 380     LiveRegs.stepBackward(MI);
 381   }
 382
 383   return Changed;
 384 }
 385
 386 bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) {
 387   if (skipFunction(F.getFunction()))
 388     return false;
 389
 390   const SystemZSubtarget &ST = F.getSubtarget<SystemZSubtarget>();
 391   TII = ST.getInstrInfo();
 392   TRI = ST.getRegisterInfo();
 393   LiveRegs.init(*TRI);
 394
 395   bool Changed = false;
 396   for (auto &MBB : F)
 397     Changed |= processBlock(MBB);
 398
 399   return Changed;
 400 }