llvm/lib/Target/VE/VEInstrInfo.h

   1 //===-- VEInstrInfo.h - VE Instruction Information --------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the VE implementation of the TargetInstrInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_VE_VEINSTRINFO_H
  14 #define LLVM_LIB_TARGET_VE_VEINSTRINFO_H
  15
  16 #include "VERegisterInfo.h"
  17 #include "llvm/CodeGen/TargetInstrInfo.h"
  18
  19 #define GET_INSTRINFO_HEADER
  20 #include "VEGenInstrInfo.inc"
  21
  22 namespace llvm {
  23
  24 class VESubtarget;
  25
  26 /// VEII - This namespace holds all of the Aurora VE target-specific
  27 /// per-instruction flags.  These must match the corresponding definitions in
  28 /// VEInstrFormats.td.
  29 namespace VEII {
  30 enum {
  31   // Aurora VE Instruction Flags.  These flags describe the characteristics of
  32   // the Aurora VE instructions for vector handling.
  33
  34   /// VE_Vector - This instruction is Vector Instruction.
  35   VE_Vector = 0x1,
  36
  37   /// VE_VLInUse - This instruction has a vector register in its operands.
  38   VE_VLInUse = 0x2,
  39
  40   /// VE_VLMask/Shift - This is a bitmask that selects the index number where
  41   /// an instruction holds vector length informatio (0 to 6, 7 means undef).n
  42   VE_VLShift = 2,
  43   VE_VLMask = 0x07 << VE_VLShift,
  44 };
  45
  46 #define HAS_VLINDEX(TSF) ((TSF)&VEII::VE_VLInUse)
  47 #define GET_VLINDEX(TSF)                                                       \
  48   (HAS_VLINDEX(TSF) ? (int)(((TSF)&VEII::VE_VLMask) >> VEII::VE_VLShift) : -1)
  49 } // end namespace VEII
  50
  51 class VEInstrInfo : public VEGenInstrInfo {
  52   const VERegisterInfo RI;
  53   virtual void anchor();
  54
  55 public:
  56   explicit VEInstrInfo(VESubtarget &ST);
  57
  58   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  59   /// such, whenever a client has an instance of instruction info, it should
  60   /// always be able to get register info as well (through this method).
  61   ///
  62   const VERegisterInfo &getRegisterInfo() const { return RI; }
  63
  64   /// Branch Analysis & Modification {
  65   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  66                      MachineBasicBlock *&FBB,
  67                      SmallVectorImpl<MachineOperand> &Cond,
  68                      bool AllowModify = false) const override;
  69
  70   unsigned removeBranch(MachineBasicBlock &MBB,
  71                         int *BytesRemoved = nullptr) const override;
  72
  73   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  74                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
  75                         const DebugLoc &DL,
  76                         int *BytesAdded = nullptr) const override;
  77
  78   bool
  79   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
  80   /// } Branch Analysis & Modification
  81
  82   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
  83                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
  84                    bool KillSrc, bool RenamableDest = false,
  85                    bool RenamableSrc = false) const override;
  86
  87   /// Stack Spill & Reload {
  88   Register isLoadFromStackSlot(const MachineInstr &MI,
  89                                int &FrameIndex) const override;
  90   Register isStoreToStackSlot(const MachineInstr &MI,
  91                               int &FrameIndex) const override;
  92   void storeRegToStackSlot(MachineBasicBlock &MBB,
  93                            MachineBasicBlock::iterator MBBI, Register SrcReg,
  94                            bool isKill, int FrameIndex,
  95                            const TargetRegisterClass *RC,
  96                            const TargetRegisterInfo *TRI,
  97                            Register VReg) const override;
  98
  99   void loadRegFromStackSlot(MachineBasicBlock &MBB,
 100                             MachineBasicBlock::iterator MBBI, Register DestReg,
 101                             int FrameIndex, const TargetRegisterClass *RC,
 102                             const TargetRegisterInfo *TRI,
 103                             Register VReg) const override;
 104   /// } Stack Spill & Reload
 105
 106   /// Optimization {
 107
 108   bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
 109                      MachineRegisterInfo *MRI) const override;
 110
 111   /// } Optimization
 112
 113   Register getGlobalBaseReg(MachineFunction *MF) const;
 114
 115   // Lower pseudo instructions after register allocation.
 116   bool expandPostRAPseudo(MachineInstr &MI) const override;
 117
 118   bool expandExtendStackPseudo(MachineInstr &MI) const;
 119   bool expandGetStackTopPseudo(MachineInstr &MI) const;
 120 };
 121
 122 } // namespace llvm
 123
 124 #endif