llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h

   1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains small standalone helper functions and enum definitions for
  10 // the X86 target useful for the compiler back-end and the MC libraries.
  11 // As such, it deliberately does not include references to LLVM core
  12 // code gen types, passes, etc..
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
  17 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
  18
  19 #include "X86MCTargetDesc.h"
  20 #include "llvm/MC/MCInstrDesc.h"
  21 #include "llvm/Support/DataTypes.h"
  22 #include "llvm/Support/ErrorHandling.h"
  23
  24 namespace llvm {
  25 namespace X86 {
  26 // Enums for memory operand decoding. Each memory operand is represented with
  27 // a 5 operand sequence in the form: [Base, Scale, Index, Disp, Segment]
  28 enum {
  29   AddrBaseReg = 0,
  30   AddrScaleAmt = 1,
  31   AddrIndexReg = 2,
  32   AddrDisp = 3,
  33   // The operand # of the segment in the memory operand.
  34   AddrSegmentReg = 4,
  35   // Total number of operands in a memory reference.
  36   AddrNumOperands = 5
  37 };
  38
  39 /// AVX512 static rounding constants. These need to match the values in
  40 /// avx512fintrin.h.
  41 enum STATIC_ROUNDING {
  42   TO_NEAREST_INT = 0,
  43   TO_NEG_INF = 1,
  44   TO_POS_INF = 2,
  45   TO_ZERO = 3,
  46   CUR_DIRECTION = 4,
  47   NO_EXC = 8
  48 };
  49
  50 /// The constants to describe instr prefixes if there are
  51 enum IPREFIXES {
  52   IP_NO_PREFIX = 0,
  53   IP_HAS_OP_SIZE = 1U << 0,
  54   IP_HAS_AD_SIZE = 1U << 1,
  55   IP_HAS_REPEAT_NE = 1U << 2,
  56   IP_HAS_REPEAT = 1U << 3,
  57   IP_HAS_LOCK = 1U << 4,
  58   IP_HAS_NOTRACK = 1U << 5,
  59   IP_USE_REX = 1U << 6,
  60   IP_USE_REX2 = 1U << 7,
  61   IP_USE_VEX = 1U << 8,
  62   IP_USE_VEX2 = 1U << 9,
  63   IP_USE_VEX3 = 1U << 10,
  64   IP_USE_EVEX = 1U << 11,
  65   IP_USE_DISP8 = 1U << 12,
  66   IP_USE_DISP32 = 1U << 13,
  67 };
  68
  69 enum OperandType : unsigned {
  70   // AVX512 embedded rounding control. This should only have values 0-3.
  71   OPERAND_ROUNDING_CONTROL = MCOI::OPERAND_FIRST_TARGET,
  72   OPERAND_COND_CODE,
  73 };
  74
  75 // X86 specific condition code. These correspond to X86_*_COND in
  76 // X86InstrInfo.td. They must be kept in synch.
  77 enum CondCode {
  78   COND_O = 0,
  79   COND_NO = 1,
  80   COND_B = 2,
  81   COND_AE = 3,
  82   COND_E = 4,
  83   COND_NE = 5,
  84   COND_BE = 6,
  85   COND_A = 7,
  86   COND_S = 8,
  87   COND_NS = 9,
  88   COND_P = 10,
  89   COND_NP = 11,
  90   COND_L = 12,
  91   COND_GE = 13,
  92   COND_LE = 14,
  93   COND_G = 15,
  94   LAST_VALID_COND = COND_G,
  95   // Artificial condition codes. These are used by analyzeBranch
  96   // to indicate a block terminated with two conditional branches that together
  97   // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
  98   // which can't be represented on x86 with a single condition. These
  99   // are never used in MachineInstrs and are inverses of one another.
 100   COND_NE_OR_P,
 101   COND_E_AND_NP,
 102   COND_INVALID
 103 };
 104
 105 // The classification for the first instruction in macro fusion.
 106 // FIXME: Zen 3 support branch fusion for OR/XOR.
 107 enum class FirstMacroFusionInstKind {
 108   Test,   // TEST
 109   Cmp,    // CMP
 110   And,    // AND
 111   AddSub, // ADD, SUB
 112   IncDec, // INC, DEC
 113   Invalid // Not valid as a first macro fusion instruction
 114 };
 115
 116 enum class SecondMacroFusionInstKind {
 117   AB,      // JA, JB and variants
 118   ELG,     // JE, JL, JG and variants
 119   SPO,     // JS, JP, JO and variants
 120   Invalid, // Not a fusible jump.
 121 };
 122
 123 /// \returns the type of the first instruction in macro-fusion.
 124 // FIXME: Zen 3 support branch fusion for OR/XOR.
 125 inline FirstMacroFusionInstKind
 126 classifyFirstOpcodeInMacroFusion(unsigned Opcode) {
 127   switch (Opcode) {
 128   default:
 129     return FirstMacroFusionInstKind::Invalid;
 130   // TEST
 131   case X86::TEST16i16:
 132   case X86::TEST16mr:
 133   case X86::TEST16ri:
 134   case X86::TEST16rr:
 135   case X86::TEST32i32:
 136   case X86::TEST32mr:
 137   case X86::TEST32ri:
 138   case X86::TEST32rr:
 139   case X86::TEST64i32:
 140   case X86::TEST64mr:
 141   case X86::TEST64ri32:
 142   case X86::TEST64rr:
 143   case X86::TEST8i8:
 144   case X86::TEST8mr:
 145   case X86::TEST8ri:
 146   case X86::TEST8rr:
 147     return FirstMacroFusionInstKind::Test;
 148   case X86::AND16i16:
 149   case X86::AND16ri:
 150   case X86::AND16ri8:
 151   case X86::AND16rm:
 152   case X86::AND16rr:
 153   case X86::AND32i32:
 154   case X86::AND32ri:
 155   case X86::AND32ri8:
 156   case X86::AND32rm:
 157   case X86::AND32rr:
 158   case X86::AND64i32:
 159   case X86::AND64ri32:
 160   case X86::AND64ri8:
 161   case X86::AND64rm:
 162   case X86::AND64rr:
 163   case X86::AND8i8:
 164   case X86::AND8ri:
 165   case X86::AND8ri8:
 166   case X86::AND8rm:
 167   case X86::AND8rr:
 168     return FirstMacroFusionInstKind::And;
 169   // CMP
 170   case X86::CMP16i16:
 171   case X86::CMP16mr:
 172   case X86::CMP16ri:
 173   case X86::CMP16ri8:
 174   case X86::CMP16rm:
 175   case X86::CMP16rr:
 176   case X86::CMP32i32:
 177   case X86::CMP32mr:
 178   case X86::CMP32ri:
 179   case X86::CMP32ri8:
 180   case X86::CMP32rm:
 181   case X86::CMP32rr:
 182   case X86::CMP64i32:
 183   case X86::CMP64mr:
 184   case X86::CMP64ri32:
 185   case X86::CMP64ri8:
 186   case X86::CMP64rm:
 187   case X86::CMP64rr:
 188   case X86::CMP8i8:
 189   case X86::CMP8mr:
 190   case X86::CMP8ri:
 191   case X86::CMP8ri8:
 192   case X86::CMP8rm:
 193   case X86::CMP8rr:
 194     return FirstMacroFusionInstKind::Cmp;
 195   // ADD
 196   case X86::ADD16i16:
 197   case X86::ADD16ri:
 198   case X86::ADD16ri8:
 199   case X86::ADD16rm:
 200   case X86::ADD16rr:
 201   case X86::ADD32i32:
 202   case X86::ADD32ri:
 203   case X86::ADD32ri8:
 204   case X86::ADD32rm:
 205   case X86::ADD32rr:
 206   case X86::ADD64i32:
 207   case X86::ADD64ri32:
 208   case X86::ADD64ri8:
 209   case X86::ADD64rm:
 210   case X86::ADD64rr:
 211   case X86::ADD8i8:
 212   case X86::ADD8ri:
 213   case X86::ADD8ri8:
 214   case X86::ADD8rm:
 215   case X86::ADD8rr:
 216   // SUB
 217   case X86::SUB16i16:
 218   case X86::SUB16ri:
 219   case X86::SUB16ri8:
 220   case X86::SUB16rm:
 221   case X86::SUB16rr:
 222   case X86::SUB32i32:
 223   case X86::SUB32ri:
 224   case X86::SUB32ri8:
 225   case X86::SUB32rm:
 226   case X86::SUB32rr:
 227   case X86::SUB64i32:
 228   case X86::SUB64ri32:
 229   case X86::SUB64ri8:
 230   case X86::SUB64rm:
 231   case X86::SUB64rr:
 232   case X86::SUB8i8:
 233   case X86::SUB8ri:
 234   case X86::SUB8ri8:
 235   case X86::SUB8rm:
 236   case X86::SUB8rr:
 237     return FirstMacroFusionInstKind::AddSub;
 238   // INC
 239   case X86::INC16r:
 240   case X86::INC16r_alt:
 241   case X86::INC32r:
 242   case X86::INC32r_alt:
 243   case X86::INC64r:
 244   case X86::INC8r:
 245   // DEC
 246   case X86::DEC16r:
 247   case X86::DEC16r_alt:
 248   case X86::DEC32r:
 249   case X86::DEC32r_alt:
 250   case X86::DEC64r:
 251   case X86::DEC8r:
 252     return FirstMacroFusionInstKind::IncDec;
 253   }
 254 }
 255
 256 /// \returns the type of the second instruction in macro-fusion.
 257 inline SecondMacroFusionInstKind
 258 classifySecondCondCodeInMacroFusion(X86::CondCode CC) {
 259   if (CC == X86::COND_INVALID)
 260     return SecondMacroFusionInstKind::Invalid;
 261   switch (CC) {
 262   default:
 263     return SecondMacroFusionInstKind::Invalid;
 264   case X86::COND_E:  // JE,JZ
 265   case X86::COND_NE: // JNE,JNZ
 266   case X86::COND_L:  // JL,JNGE
 267   case X86::COND_LE: // JLE,JNG
 268   case X86::COND_G:  // JG,JNLE
 269   case X86::COND_GE: // JGE,JNL
 270     return SecondMacroFusionInstKind::ELG;
 271   case X86::COND_B:  // JB,JC
 272   case X86::COND_BE: // JNA,JBE
 273   case X86::COND_A:  // JA,JNBE
 274   case X86::COND_AE: // JAE,JNC,JNB
 275     return SecondMacroFusionInstKind::AB;
 276   case X86::COND_S:  // JS
 277   case X86::COND_NS: // JNS
 278   case X86::COND_P:  // JP,JPE
 279   case X86::COND_NP: // JNP,JPO
 280   case X86::COND_O:  // JO
 281   case X86::COND_NO: // JNO
 282     return SecondMacroFusionInstKind::SPO;
 283   }
 284 }
 285
 286 /// \param FirstKind kind of the first instruction in macro fusion.
 287 /// \param SecondKind kind of the second instruction in macro fusion.
 288 ///
 289 /// \returns true if the two instruction can be macro fused.
 290 inline bool isMacroFused(FirstMacroFusionInstKind FirstKind,
 291                          SecondMacroFusionInstKind SecondKind) {
 292   switch (FirstKind) {
 293   case X86::FirstMacroFusionInstKind::Test:
 294   case X86::FirstMacroFusionInstKind::And:
 295     return true;
 296   case X86::FirstMacroFusionInstKind::Cmp:
 297   case X86::FirstMacroFusionInstKind::AddSub:
 298     return SecondKind == X86::SecondMacroFusionInstKind::AB ||
 299            SecondKind == X86::SecondMacroFusionInstKind::ELG;
 300   case X86::FirstMacroFusionInstKind::IncDec:
 301     return SecondKind == X86::SecondMacroFusionInstKind::ELG;
 302   case X86::FirstMacroFusionInstKind::Invalid:
 303     return false;
 304   }
 305   llvm_unreachable("unknown fusion type");
 306 }
 307
 308 /// Defines the possible values of the branch boundary alignment mask.
 309 enum AlignBranchBoundaryKind : uint8_t {
 310   AlignBranchNone = 0,
 311   AlignBranchFused = 1U << 0,
 312   AlignBranchJcc = 1U << 1,
 313   AlignBranchJmp = 1U << 2,
 314   AlignBranchCall = 1U << 3,
 315   AlignBranchRet = 1U << 4,
 316   AlignBranchIndirect = 1U << 5
 317 };
 318
 319 /// Defines the encoding values for segment override prefix.
 320 enum EncodingOfSegmentOverridePrefix : uint8_t {
 321   CS_Encoding = 0x2E,
 322   DS_Encoding = 0x3E,
 323   ES_Encoding = 0x26,
 324   FS_Encoding = 0x64,
 325   GS_Encoding = 0x65,
 326   SS_Encoding = 0x36
 327 };
 328
 329 /// Given a segment register, return the encoding of the segment override
 330 /// prefix for it.
 331 inline EncodingOfSegmentOverridePrefix
 332 getSegmentOverridePrefixForReg(MCRegister Reg) {
 333   switch (Reg.id()) {
 334   default:
 335     llvm_unreachable("Unknown segment register!");
 336   case X86::CS:
 337     return CS_Encoding;
 338   case X86::DS:
 339     return DS_Encoding;
 340   case X86::ES:
 341     return ES_Encoding;
 342   case X86::FS:
 343     return FS_Encoding;
 344   case X86::GS:
 345     return GS_Encoding;
 346   case X86::SS:
 347     return SS_Encoding;
 348   }
 349 }
 350
 351 } // namespace X86
 352
 353 /// X86II - This namespace holds all of the target specific flags that
 354 /// instruction info tracks.
 355 ///
 356 namespace X86II {
 357 /// Target Operand Flag enum.
 358 enum TOF {
 359   //===------------------------------------------------------------------===//
 360   // X86 Specific MachineOperand flags.
 361   //
 362   /// MO_NO_FLAG - No flag for the operand
 363   MO_NO_FLAG,
 364   /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
 365   /// relocation of:
 366   ///    SYMBOL_LABEL + [. - PICBASELABEL]
 367   MO_GOT_ABSOLUTE_ADDRESS,
 368   /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
 369   /// immediate should get the value of the symbol minus the PIC base label:
 370   ///    SYMBOL_LABEL - PICBASELABEL
 371   MO_PIC_BASE_OFFSET,
 372   /// MO_GOT - On a symbol operand this indicates that the immediate is the
 373   /// offset to the GOT entry for the symbol name from the base of the GOT.
 374   /// See the X86-64 ELF ABI supplement for more details.
 375   ///    SYMBOL_LABEL @GOT
 376   MO_GOT,
 377   /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
 378   /// the offset to the location of the symbol name from the base of the GOT.
 379   /// See the X86-64 ELF ABI supplement for more details.
 380   ///    SYMBOL_LABEL @GOTOFF
 381   MO_GOTOFF,
 382   /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
 383   /// offset to the GOT entry for the symbol name from the current code
 384   /// location.
 385   /// See the X86-64 ELF ABI supplement for more details.
 386   ///    SYMBOL_LABEL @GOTPCREL
 387   MO_GOTPCREL,
 388   /// MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL
 389   /// relocations are guaranteed to be emitted by the integrated assembler
 390   /// instead of the relaxable R_X86_64[_REX]_GOTPCRELX relocations.
 391   MO_GOTPCREL_NORELAX,
 392   /// MO_PLT - On a symbol operand this indicates that the immediate is
 393   /// offset to the PLT entry of symbol name from the current code location.
 394   /// See the X86-64 ELF ABI supplement for more details.
 395   ///    SYMBOL_LABEL @PLT
 396   MO_PLT,
 397   /// MO_TLSGD - On a symbol operand this indicates that the immediate is
 398   /// the offset of the GOT entry with the TLS index structure that contains
 399   /// the module number and variable offset for the symbol. Used in the
 400   /// general dynamic TLS access model.
 401   /// See 'ELF Handling for Thread-Local Storage' for more details.
 402   ///    SYMBOL_LABEL @TLSGD
 403   MO_TLSGD,
 404   /// MO_TLSLD - On a symbol operand this indicates that the immediate is
 405   /// the offset of the GOT entry with the TLS index for the module that
 406   /// contains the symbol. When this index is passed to a call to
 407   /// __tls_get_addr, the function will return the base address of the TLS
 408   /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
 409   /// See 'ELF Handling for Thread-Local Storage' for more details.
 410   ///    SYMBOL_LABEL @TLSLD
 411   MO_TLSLD,
 412   /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
 413   /// the offset of the GOT entry with the TLS index for the module that
 414   /// contains the symbol. When this index is passed to a call to
 415   /// ___tls_get_addr, the function will return the base address of the TLS
 416   /// block for the symbol. Used in the IA32 local dynamic TLS access model.
 417   /// See 'ELF Handling for Thread-Local Storage' for more details.
 418   ///    SYMBOL_LABEL @TLSLDM
 419   MO_TLSLDM,
 420   /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
 421   /// the offset of the GOT entry with the thread-pointer offset for the
 422   /// symbol. Used in the x86-64 initial exec TLS access model.
 423   /// See 'ELF Handling for Thread-Local Storage' for more details.
 424   ///    SYMBOL_LABEL @GOTTPOFF
 425   MO_GOTTPOFF,
 426   /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
 427   /// the absolute address of the GOT entry with the negative thread-pointer
 428   /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
 429   /// model.
 430   /// See 'ELF Handling for Thread-Local Storage' for more details.
 431   ///    SYMBOL_LABEL @INDNTPOFF
 432   MO_INDNTPOFF,
 433   /// MO_TPOFF - On a symbol operand this indicates that the immediate is
 434   /// the thread-pointer offset for the symbol. Used in the x86-64 local
 435   /// exec TLS access model.
 436   /// See 'ELF Handling for Thread-Local Storage' for more details.
 437   ///    SYMBOL_LABEL @TPOFF
 438   MO_TPOFF,
 439   /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
 440   /// the offset of the GOT entry with the TLS offset of the symbol. Used
 441   /// in the local dynamic TLS access model.
 442   /// See 'ELF Handling for Thread-Local Storage' for more details.
 443   ///    SYMBOL_LABEL @DTPOFF
 444   MO_DTPOFF,
 445   /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
 446   /// the negative thread-pointer offset for the symbol. Used in the IA32
 447   /// local exec TLS access model.
 448   /// See 'ELF Handling for Thread-Local Storage' for more details.
 449   ///    SYMBOL_LABEL @NTPOFF
 450   MO_NTPOFF,
 451   /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
 452   /// the offset of the GOT entry with the negative thread-pointer offset for
 453   /// the symbol. Used in the PIC IA32 initial exec TLS access model.
 454   /// See 'ELF Handling for Thread-Local Storage' for more details.
 455   ///    SYMBOL_LABEL @GOTNTPOFF
 456   MO_GOTNTPOFF,
 457   /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
 458   /// reference is actually to the "__imp_FOO" symbol.  This is used for
 459   /// dllimport linkage on windows.
 460   MO_DLLIMPORT,
 461   /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
 462   /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
 463   /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
 464   MO_DARWIN_NONLAZY,
 465   /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
 466   /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
 467   /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
 468   MO_DARWIN_NONLAZY_PIC_BASE,
 469   /// MO_TLVP - On a symbol operand this indicates that the immediate is
 470   /// some TLS offset.
 471   /// This is the TLS offset for the Darwin TLS mechanism.
 472   MO_TLVP,
 473   /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
 474   /// is some TLS offset from the picbase.
 475   /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
 476   MO_TLVP_PIC_BASE,
 477   /// MO_SECREL - On a symbol operand this indicates that the immediate is
 478   /// the offset from beginning of section.
 479   /// This is the TLS offset for the COFF/Windows TLS mechanism.
 480   MO_SECREL,
 481   /// MO_ABS8 - On a symbol operand this indicates that the symbol is known
 482   /// to be an absolute symbol in range [0,128), so we can use the @ABS8
 483   /// symbol modifier.
 484   MO_ABS8,
 485   /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
 486   /// reference is actually to the ".refptr.FOO" symbol.  This is used for
 487   /// stub symbols on windows.
 488   MO_COFFSTUB,
 489 };
 490
 491 enum : uint64_t {
 492   //===------------------------------------------------------------------===//
 493   // Instruction encodings.  These are the standard/most common forms for X86
 494   // instructions.
 495   //
 496   /// PseudoFrm - This represents an instruction that is a pseudo instruction
 497   /// or one that has not been implemented yet.  It is illegal to code generate
 498   /// it, but tolerated for intermediate implementation stages.
 499   Pseudo = 0,
 500   /// Raw - This form is for instructions that don't have any operands, so
 501   /// they are just a fixed opcode value, like 'leave'.
 502   RawFrm = 1,
 503   /// AddRegFrm - This form is used for instructions like 'push r32' that have
 504   /// their one register operand added to their opcode.
 505   AddRegFrm = 2,
 506   /// RawFrmMemOffs - This form is for instructions that store an absolute
 507   /// memory offset as an immediate with a possible segment override.
 508   RawFrmMemOffs = 3,
 509   /// RawFrmSrc - This form is for instructions that use the source index
 510   /// register SI/ESI/RSI with a possible segment override.
 511   RawFrmSrc = 4,
 512   /// RawFrmDst - This form is for instructions that use the destination index
 513   /// register DI/EDI/RDI.
 514   RawFrmDst = 5,
 515   /// RawFrmDstSrc - This form is for instructions that use the source index
 516   /// register SI/ESI/RSI with a possible segment override, and also the
 517   /// destination index register DI/EDI/RDI.
 518   RawFrmDstSrc = 6,
 519   /// RawFrmImm8 - This is used for the ENTER instruction, which has two
 520   /// immediates, the first of which is a 16-bit immediate (specified by
 521   /// the imm encoding) and the second is a 8-bit fixed value.
 522   RawFrmImm8 = 7,
 523   /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
 524   /// immediates, the first of which is a 16 or 32-bit immediate (specified by
 525   /// the imm encoding) and the second is a 16-bit fixed value.  In the AMD
 526   /// manual, this operand is described as pntr16:32 and pntr16:16
 527   RawFrmImm16 = 8,
 528   /// AddCCFrm - This form is used for Jcc that encode the condition code
 529   /// in the lower 4 bits of the opcode.
 530   AddCCFrm = 9,
 531   /// PrefixByte - This form is used for instructions that represent a prefix
 532   /// byte like data16 or rep.
 533   PrefixByte = 10,
 534   /// MRMDestRegCC - This form is used for the cfcmov instructions, which use
 535   /// the Mod/RM byte to specify the operands reg(r/m) and reg(reg) and also
 536   /// encodes a condition code.
 537   MRMDestRegCC = 18,
 538   /// MRMDestMemCC - This form is used for the cfcmov instructions, which use
 539   /// the Mod/RM byte to specify the operands mem(r/m) and reg(reg) and also
 540   /// encodes a condition code.
 541   MRMDestMemCC = 19,
 542   /// MRMDestMem4VOp3CC - This form is used for instructions that use the Mod/RM
 543   /// byte to specify a destination which in this case is memory and operand 3
 544   /// with VEX.VVVV, and also encodes a condition code.
 545   MRMDestMem4VOp3CC = 20,
 546   /// Instructions operate on a register Reg/Opcode operand not the r/m field.
 547   MRMr0 = 21,
 548   /// MRMSrcMem - But force to use the SIB field.
 549   MRMSrcMemFSIB = 22,
 550   /// MRMDestMem - But force to use the SIB field.
 551   MRMDestMemFSIB = 23,
 552   /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
 553   /// to specify a destination, which in this case is memory.
 554   MRMDestMem = 24,
 555   /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
 556   /// to specify a source, which in this case is memory.
 557   MRMSrcMem = 25,
 558   /// MRMSrcMem4VOp3 - This form is used for instructions that encode
 559   /// operand 3 with VEX.VVVV and load from memory.
 560   MRMSrcMem4VOp3 = 26,
 561   /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
 562   /// byte to specify the fourth source, which in this case is memory.
 563   MRMSrcMemOp4 = 27,
 564   /// MRMSrcMemCC - This form is used for instructions that use the Mod/RM
 565   /// byte to specify the operands and also encodes a condition code.
 566   MRMSrcMemCC = 28,
 567   /// MRMXm - This form is used for instructions that use the Mod/RM byte
 568   /// to specify a memory source, but doesn't use the middle field. And has
 569   /// a condition code.
 570   MRMXmCC = 30,
 571   /// MRMXm - This form is used for instructions that use the Mod/RM byte
 572   /// to specify a memory source, but doesn't use the middle field.
 573   MRMXm = 31,
 574   /// MRM0m-MRM7m - Instructions that operate on a memory r/m operand and use
 575   /// reg field to hold extended opcode, which is represented as /0, /1, ...
 576   MRM0m = 32, // Format /0
 577   MRM1m = 33, // Format /1
 578   MRM2m = 34, // Format /2
 579   MRM3m = 35, // Format /3
 580   MRM4m = 36, // Format /4
 581   MRM5m = 37, // Format /5
 582   MRM6m = 38, // Format /6
 583   MRM7m = 39, // Format /7
 584   /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
 585   /// to specify a destination, which in this case is a register.
 586   MRMDestReg = 40,
 587   /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
 588   /// to specify a source, which in this case is a register.
 589   MRMSrcReg = 41,
 590   /// MRMSrcReg4VOp3 - This form is used for instructions that encode
 591   /// operand 3 with VEX.VVVV and do not load from memory.
 592   MRMSrcReg4VOp3 = 42,
 593   /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
 594   /// byte to specify the fourth source, which in this case is a register.
 595   MRMSrcRegOp4 = 43,
 596   /// MRMSrcRegCC - This form is used for instructions that use the Mod/RM
 597   /// byte to specify the operands and also encodes a condition code
 598   MRMSrcRegCC = 44,
 599   /// MRMXCCr - This form is used for instructions that use the Mod/RM byte
 600   /// to specify a register source, but doesn't use the middle field. And has
 601   /// a condition code.
 602   MRMXrCC = 46,
 603   /// MRMXr - This form is used for instructions that use the Mod/RM byte
 604   /// to specify a register source, but doesn't use the middle field.
 605   MRMXr = 47,
 606   /// MRM0r-MRM7r - Instructions that operate on a register r/m operand and use
 607   /// reg field to hold extended opcode, which is represented as /0, /1, ...
 608   MRM0r = 48, // Format /0
 609   MRM1r = 49, // Format /1
 610   MRM2r = 50, // Format /2
 611   MRM3r = 51, // Format /3
 612   MRM4r = 52, // Format /4
 613   MRM5r = 53, // Format /5
 614   MRM6r = 54, // Format /6
 615   MRM7r = 55, // Format /7
 616   /// MRM0X-MRM7X - Instructions that operate that have mod=11 and an opcode but
 617   /// ignore r/m.
 618   MRM0X = 56, // Format /0
 619   MRM1X = 57, // Format /1
 620   MRM2X = 58, // Format /2
 621   MRM3X = 59, // Format /3
 622   MRM4X = 60, // Format /4
 623   MRM5X = 61, // Format /5
 624   MRM6X = 62, // Format /6
 625   MRM7X = 63, // Format /7
 626   /// MRM_XX (XX: C0-FF)- A mod/rm byte of exactly 0xXX.
 627   MRM_C0 = 64,
 628   MRM_C1 = 65,
 629   MRM_C2 = 66,
 630   MRM_C3 = 67,
 631   MRM_C4 = 68,
 632   MRM_C5 = 69,
 633   MRM_C6 = 70,
 634   MRM_C7 = 71,
 635   MRM_C8 = 72,
 636   MRM_C9 = 73,
 637   MRM_CA = 74,
 638   MRM_CB = 75,
 639   MRM_CC = 76,
 640   MRM_CD = 77,
 641   MRM_CE = 78,
 642   MRM_CF = 79,
 643   MRM_D0 = 80,
 644   MRM_D1 = 81,
 645   MRM_D2 = 82,
 646   MRM_D3 = 83,
 647   MRM_D4 = 84,
 648   MRM_D5 = 85,
 649   MRM_D6 = 86,
 650   MRM_D7 = 87,
 651   MRM_D8 = 88,
 652   MRM_D9 = 89,
 653   MRM_DA = 90,
 654   MRM_DB = 91,
 655   MRM_DC = 92,
 656   MRM_DD = 93,
 657   MRM_DE = 94,
 658   MRM_DF = 95,
 659   MRM_E0 = 96,
 660   MRM_E1 = 97,
 661   MRM_E2 = 98,
 662   MRM_E3 = 99,
 663   MRM_E4 = 100,
 664   MRM_E5 = 101,
 665   MRM_E6 = 102,
 666   MRM_E7 = 103,
 667   MRM_E8 = 104,
 668   MRM_E9 = 105,
 669   MRM_EA = 106,
 670   MRM_EB = 107,
 671   MRM_EC = 108,
 672   MRM_ED = 109,
 673   MRM_EE = 110,
 674   MRM_EF = 111,
 675   MRM_F0 = 112,
 676   MRM_F1 = 113,
 677   MRM_F2 = 114,
 678   MRM_F3 = 115,
 679   MRM_F4 = 116,
 680   MRM_F5 = 117,
 681   MRM_F6 = 118,
 682   MRM_F7 = 119,
 683   MRM_F8 = 120,
 684   MRM_F9 = 121,
 685   MRM_FA = 122,
 686   MRM_FB = 123,
 687   MRM_FC = 124,
 688   MRM_FD = 125,
 689   MRM_FE = 126,
 690   MRM_FF = 127,
 691   FormMask = 127,
 692   //===------------------------------------------------------------------===//
 693   // Actual flags...
 694   /// OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
 695   /// OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
 696   /// 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
 697   /// prefix in 16-bit mode.
 698   OpSizeShift = 7,
 699   OpSizeMask = 0x3 << OpSizeShift,
 700   OpSizeFixed = 0 << OpSizeShift,
 701   OpSize16 = 1 << OpSizeShift,
 702   OpSize32 = 2 << OpSizeShift,
 703   /// AsSize - AdSizeX implies this instruction determines its need of 0x67
 704   /// prefix from a normal ModRM memory operand. The other types indicate that
 705   /// an operand is encoded with a specific width and a prefix is needed if
 706   /// it differs from the current mode.
 707   AdSizeShift = OpSizeShift + 2,
 708   AdSizeMask = 0x3 << AdSizeShift,
 709   AdSizeX = 0 << AdSizeShift,
 710   AdSize16 = 1 << AdSizeShift,
 711   AdSize32 = 2 << AdSizeShift,
 712   AdSize64 = 3 << AdSizeShift,
 713   //===------------------------------------------------------------------===//
 714   /// OpPrefix - There are several prefix bytes that are used as opcode
 715   /// extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
 716   /// no prefix.
 717   OpPrefixShift = AdSizeShift + 2,
 718   OpPrefixMask = 0x3 << OpPrefixShift,
 719   /// PD - Prefix code for packed double precision vector floating point
 720   /// operations performed in the SSE registers.
 721   PD = 1 << OpPrefixShift,
 722   /// XS, XD - These prefix codes are for single and double precision scalar
 723   /// floating point operations performed in the SSE registers.
 724   XS = 2 << OpPrefixShift,
 725   XD = 3 << OpPrefixShift,
 726   //===------------------------------------------------------------------===//
 727   /// OpMap - This field determines which opcode map this instruction
 728   /// belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
 729   OpMapShift = OpPrefixShift + 2,
 730   OpMapMask = 0xF << OpMapShift,
 731   /// OB - OneByte - Set if this instruction has a one byte opcode.
 732   OB = 0 << OpMapShift,
 733   /// TB - TwoByte - Set if this instruction has a two byte opcode, which
 734   /// starts with a 0x0F byte before the real opcode.
 735   TB = 1 << OpMapShift,
 736   /// T8, TA - Prefix after the 0x0F prefix.
 737   T8 = 2 << OpMapShift,
 738   TA = 3 << OpMapShift,
 739   /// XOP8 - Prefix to include use of imm byte.
 740   XOP8 = 4 << OpMapShift,
 741   /// XOP9 - Prefix to exclude use of imm byte.
 742   XOP9 = 5 << OpMapShift,
 743   /// XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
 744   XOPA = 6 << OpMapShift,
 745   /// ThreeDNow - This indicates that the instruction uses the
 746   /// wacky 0x0F 0x0F prefix for 3DNow! instructions.  The manual documents
 747   /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
 748   /// storing a classifier in the imm8 field.  To simplify our implementation,
 749   /// we handle this by storeing the classifier in the opcode field and using
 750   /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
 751   ThreeDNow = 7 << OpMapShift,
 752   /// MAP4, MAP5, MAP6, MAP7 - Prefix after the 0x0F prefix.
 753   T_MAP4 = 8 << OpMapShift,
 754   T_MAP5 = 9 << OpMapShift,
 755   T_MAP6 = 10 << OpMapShift,
 756   T_MAP7 = 11 << OpMapShift,
 757   //===------------------------------------------------------------------===//
 758   /// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
 759   /// They are used to specify GPRs and SSE registers, 64-bit operand size,
 760   /// etc. We only cares about REX.W and REX.R bits and only the former is
 761   /// statically determined.
 762   REXShift = OpMapShift + 4,
 763   REX_W = 1 << REXShift,
 764   //===------------------------------------------------------------------===//
 765   // This 4-bit field describes the size of an immediate operand. Zero is
 766   // unused so that we can tell if we forgot to set a value.
 767   ImmShift = REXShift + 1,
 768   Imm8 = 1 << ImmShift,
 769   Imm8PCRel = 2 << ImmShift,
 770   Imm8Reg = 3 << ImmShift,
 771   Imm16 = 4 << ImmShift,
 772   Imm16PCRel = 5 << ImmShift,
 773   Imm32 = 6 << ImmShift,
 774   Imm32PCRel = 7 << ImmShift,
 775   Imm32S = 8 << ImmShift,
 776   Imm64 = 9 << ImmShift,
 777   ImmMask = 15 << ImmShift,
 778   //===------------------------------------------------------------------===//
 779   /// FP Instruction Classification...  Zero is non-fp instruction.
 780   /// FPTypeMask - Mask for all of the FP types...
 781   FPTypeShift = ImmShift + 4,
 782   FPTypeMask = 7 << FPTypeShift,
 783   /// NotFP - The default, set for instructions that do not use FP registers.
 784   NotFP = 0 << FPTypeShift,
 785   /// ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
 786   ZeroArgFP = 1 << FPTypeShift,
 787   /// OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
 788   OneArgFP = 2 << FPTypeShift,
 789   /// OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
 790   /// result back to ST(0).  For example, fcos, fsqrt, etc.
 791   OneArgFPRW = 3 << FPTypeShift,
 792   /// TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
 793   /// explicit argument, storing the result to either ST(0) or the implicit
 794   /// argument.  For example: fadd, fsub, fmul, etc...
 795   TwoArgFP = 4 << FPTypeShift,
 796   /// CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
 797   /// explicit argument, but have no destination.  Example: fucom, fucomi, ...
 798   CompareFP = 5 << FPTypeShift,
 799   /// CondMovFP - "2 operand" floating point conditional move instructions.
 800   CondMovFP = 6 << FPTypeShift,
 801   /// SpecialFP - Special instruction forms.  Dispatch by opcode explicitly.
 802   SpecialFP = 7 << FPTypeShift,
 803   /// Lock prefix
 804   LOCKShift = FPTypeShift + 3,
 805   LOCK = 1 << LOCKShift,
 806   /// REP prefix
 807   REPShift = LOCKShift + 1,
 808   REP = 1 << REPShift,
 809   /// Execution domain for SSE instructions.
 810   /// 0 means normal, non-SSE instruction.
 811   SSEDomainShift = REPShift + 1,
 812   /// Encoding
 813   EncodingShift = SSEDomainShift + 2,
 814   EncodingMask = 0x3 << EncodingShift,
 815   /// LEGACY - encoding using REX/REX2 or w/o opcode prefix.
 816   LEGACY = 0 << EncodingShift,
 817   /// VEX - encoding using 0xC4/0xC5
 818   VEX = 1 << EncodingShift,
 819   /// XOP - Opcode prefix used by XOP instructions.
 820   XOP = 2 << EncodingShift,
 821   /// EVEX - Specifies that this instruction use EVEX form which provides
 822   /// syntax support up to 32 512-bit register operands and up to 7 16-bit
 823   /// mask operands as well as source operand data swizzling/memory operand
 824   /// conversion, eviction hint, and rounding mode.
 825   EVEX = 3 << EncodingShift,
 826   /// Opcode
 827   OpcodeShift = EncodingShift + 2,
 828   /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
 829   /// address instructions in SSE are represented as 3 address ones in AVX
 830   /// and the additional register is encoded in VEX_VVVV prefix.
 831   VEX_4VShift = OpcodeShift + 8,
 832   VEX_4V = 1ULL << VEX_4VShift,
 833   /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
 834   /// instruction uses 256-bit wide registers. This is usually auto detected
 835   /// if a VR256 register is used, but some AVX instructions also have this
 836   /// field marked when using a f256 memory references.
 837   VEX_LShift = VEX_4VShift + 1,
 838   VEX_L = 1ULL << VEX_LShift,
 839   /// EVEX_K - Set if this instruction requires masking
 840   EVEX_KShift = VEX_LShift + 1,
 841   EVEX_K = 1ULL << EVEX_KShift,
 842   /// EVEX_Z - Set if this instruction has EVEX.Z field set.
 843   EVEX_ZShift = EVEX_KShift + 1,
 844   EVEX_Z = 1ULL << EVEX_ZShift,
 845   /// EVEX_L2 - Set if this instruction has EVEX.L' field set.
 846   EVEX_L2Shift = EVEX_ZShift + 1,
 847   EVEX_L2 = 1ULL << EVEX_L2Shift,
 848   /// EVEX_B - Set if this instruction has EVEX.B field set.
 849   EVEX_BShift = EVEX_L2Shift + 1,
 850   EVEX_B = 1ULL << EVEX_BShift,
 851   /// The scaling factor for the AVX512's 8-bit compressed displacement.
 852   CD8_Scale_Shift = EVEX_BShift + 1,
 853   CD8_Scale_Mask = 7ULL << CD8_Scale_Shift,
 854   /// Explicitly specified rounding control
 855   EVEX_RCShift = CD8_Scale_Shift + 3,
 856   EVEX_RC = 1ULL << EVEX_RCShift,
 857   /// NOTRACK prefix
 858   NoTrackShift = EVEX_RCShift + 1,
 859   NOTRACK = 1ULL << NoTrackShift,
 860   /// Force REX2/VEX/EVEX encoding
 861   ExplicitOpPrefixShift = NoTrackShift + 1,
 862   /// For instructions that require REX2 prefix even if EGPR is not used.
 863   ExplicitREX2Prefix = 1ULL << ExplicitOpPrefixShift,
 864   /// For instructions that use VEX encoding only when {vex}, {vex2} or {vex3}
 865   /// is present.
 866   ExplicitVEXPrefix = 2ULL << ExplicitOpPrefixShift,
 867   /// For instructions that are promoted to EVEX space for EGPR.
 868   ExplicitEVEXPrefix = 3ULL << ExplicitOpPrefixShift,
 869   ExplicitOpPrefixMask = 3ULL << ExplicitOpPrefixShift,
 870   /// EVEX_NF - Set if this instruction has EVEX.NF field set.
 871   EVEX_NFShift = ExplicitOpPrefixShift + 2,
 872   EVEX_NF = 1ULL << EVEX_NFShift,
 873   // TwoConditionalOps - Set if this instruction has two conditional operands
 874   TwoConditionalOps_Shift = EVEX_NFShift + 1,
 875   TwoConditionalOps = 1ULL << TwoConditionalOps_Shift,
 876   // EVEX_U - Set if this instruction has EVEX.U field set.
 877   EVEX_UShift = TwoConditionalOps_Shift + 1,
 878   EVEX_U = 1ULL << EVEX_UShift
 879 };
 880
 881 /// \returns true if the instruction with given opcode is a prefix.
 882 inline bool isPrefix(uint64_t TSFlags) {
 883   return (TSFlags & X86II::FormMask) == PrefixByte;
 884 }
 885
 886 /// \returns true if the instruction with given opcode is a pseudo.
 887 inline bool isPseudo(uint64_t TSFlags) {
 888   return (TSFlags & X86II::FormMask) == Pseudo;
 889 }
 890
 891 /// \returns the "base" X86 opcode for the specified machine
 892 /// instruction.
 893 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) {
 894   return TSFlags >> X86II::OpcodeShift;
 895 }
 896
 897 inline bool hasImm(uint64_t TSFlags) { return (TSFlags & X86II::ImmMask) != 0; }
 898
 899 /// Decode the "size of immediate" field from the TSFlags field of the
 900 /// specified instruction.
 901 inline unsigned getSizeOfImm(uint64_t TSFlags) {
 902   switch (TSFlags & X86II::ImmMask) {
 903   default:
 904     llvm_unreachable("Unknown immediate size");
 905   case X86II::Imm8:
 906   case X86II::Imm8PCRel:
 907   case X86II::Imm8Reg:
 908     return 1;
 909   case X86II::Imm16:
 910   case X86II::Imm16PCRel:
 911     return 2;
 912   case X86II::Imm32:
 913   case X86II::Imm32S:
 914   case X86II::Imm32PCRel:
 915     return 4;
 916   case X86II::Imm64:
 917     return 8;
 918   }
 919 }
 920
 921 /// \returns true if the immediate of the specified instruction's TSFlags
 922 /// indicates that it is pc relative.
 923 inline bool isImmPCRel(uint64_t TSFlags) {
 924   switch (TSFlags & X86II::ImmMask) {
 925   default:
 926     llvm_unreachable("Unknown immediate size");
 927   case X86II::Imm8PCRel:
 928   case X86II::Imm16PCRel:
 929   case X86II::Imm32PCRel:
 930     return true;
 931   case X86II::Imm8:
 932   case X86II::Imm8Reg:
 933   case X86II::Imm16:
 934   case X86II::Imm32:
 935   case X86II::Imm32S:
 936   case X86II::Imm64:
 937     return false;
 938   }
 939 }
 940
 941 /// \returns true if the immediate of the specified instruction's
 942 /// TSFlags indicates that it is signed.
 943 inline bool isImmSigned(uint64_t TSFlags) {
 944   switch (TSFlags & X86II::ImmMask) {
 945   default:
 946     llvm_unreachable("Unknown immediate signedness");
 947   case X86II::Imm32S:
 948     return true;
 949   case X86II::Imm8:
 950   case X86II::Imm8PCRel:
 951   case X86II::Imm8Reg:
 952   case X86II::Imm16:
 953   case X86II::Imm16PCRel:
 954   case X86II::Imm32:
 955   case X86II::Imm32PCRel:
 956   case X86II::Imm64:
 957     return false;
 958   }
 959 }
 960
 961 /// Compute whether all of the def operands are repeated in the uses and
 962 /// therefore should be skipped.
 963 /// This determines the start of the unique operand list. We need to determine
 964 /// if all of the defs have a corresponding tied operand in the uses.
 965 /// Unfortunately, the tied operand information is encoded in the uses not
 966 /// the defs so we have to use some heuristics to find which operands to
 967 /// query.
 968 inline unsigned getOperandBias(const MCInstrDesc &Desc) {
 969   unsigned NumDefs = Desc.getNumDefs();
 970   unsigned NumOps = Desc.getNumOperands();
 971   switch (NumDefs) {
 972   default:
 973     llvm_unreachable("Unexpected number of defs");
 974   case 0:
 975     return 0;
 976   case 1:
 977     // Common two addr case.
 978     if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
 979       return 1;
 980     // Check for AVX-512 scatter which has a TIED_TO in the second to last
 981     // operand.
 982     if (NumOps == 8 && Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0)
 983       return 1;
 984     return 0;
 985   case 2:
 986     // XCHG/XADD have two destinations and two sources.
 987     if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
 988         Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
 989       return 2;
 990     // Check for gather. AVX-512 has the second tied operand early. AVX2
 991     // has it as the last op.
 992     if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
 993         (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 ||
 994          Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1))
 995       return 2;
 996     return 0;
 997   }
 998 }
 999
1000 /// \returns true if the instruction has a NDD (new data destination).
1001 inline bool hasNewDataDest(uint64_t TSFlags) {
1002   return (TSFlags & X86II::OpMapMask) == X86II::T_MAP4 &&
1003          (TSFlags & X86II::EVEX_B) && (TSFlags & X86II::VEX_4V);
1004 }
1005
1006 /// \returns operand # for the first field of the memory operand or -1 if no
1007 /// memory operands.
1008 /// NOTE: This ignores tied operands.  If there is a tied register which is
1009 /// duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only counted
1010 /// as one operand.
1011 inline int getMemoryOperandNo(uint64_t TSFlags) {
1012   bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1013   bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1014
1015   switch (TSFlags & X86II::FormMask) {
1016   default:
1017     llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
1018   case X86II::Pseudo:
1019   case X86II::RawFrm:
1020   case X86II::AddRegFrm:
1021   case X86II::RawFrmImm8:
1022   case X86II::RawFrmImm16:
1023   case X86II::RawFrmMemOffs:
1024   case X86II::RawFrmSrc:
1025   case X86II::RawFrmDst:
1026   case X86II::RawFrmDstSrc:
1027   case X86II::AddCCFrm:
1028   case X86II::PrefixByte:
1029     return -1;
1030   case X86II::MRMDestMem:
1031   case X86II::MRMDestMemFSIB:
1032   case X86II::MRMDestMemCC:
1033     return hasNewDataDest(TSFlags);
1034   case X86II::MRMSrcMem:
1035   case X86II::MRMSrcMemFSIB:
1036     // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
1037     // mask register.
1038     return 1 + HasVEX_4V + HasEVEX_K;
1039   case X86II::MRMSrcMem4VOp3:
1040     // Skip registers encoded in reg.
1041     return 1 + HasEVEX_K;
1042   case X86II::MRMSrcMemOp4:
1043     // Skip registers encoded in reg, VEX_VVVV, and I8IMM.
1044     return 3;
1045   case X86II::MRMSrcMemCC:
1046     return 1 + hasNewDataDest(TSFlags);
1047   case X86II::MRMDestMem4VOp3CC:
1048     // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
1049     // mask register.
1050     return 1;
1051   case X86II::MRMDestReg:
1052   case X86II::MRMDestRegCC:
1053   case X86II::MRMSrcReg:
1054   case X86II::MRMSrcReg4VOp3:
1055   case X86II::MRMSrcRegOp4:
1056   case X86II::MRMSrcRegCC:
1057   case X86II::MRMXrCC:
1058   case X86II::MRMr0:
1059   case X86II::MRMXr:
1060   case X86II::MRM0r:
1061   case X86II::MRM1r:
1062   case X86II::MRM2r:
1063   case X86II::MRM3r:
1064   case X86II::MRM4r:
1065   case X86II::MRM5r:
1066   case X86II::MRM6r:
1067   case X86II::MRM7r:
1068     return -1;
1069   case X86II::MRM0X:
1070   case X86II::MRM1X:
1071   case X86II::MRM2X:
1072   case X86II::MRM3X:
1073   case X86II::MRM4X:
1074   case X86II::MRM5X:
1075   case X86II::MRM6X:
1076   case X86II::MRM7X:
1077     return -1;
1078   case X86II::MRMXmCC:
1079   case X86II::MRMXm:
1080   case X86II::MRM0m:
1081   case X86II::MRM1m:
1082   case X86II::MRM2m:
1083   case X86II::MRM3m:
1084   case X86II::MRM4m:
1085   case X86II::MRM5m:
1086   case X86II::MRM6m:
1087   case X86II::MRM7m:
1088     // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
1089     return 0 + HasVEX_4V + HasEVEX_K;
1090   case X86II::MRM_C0:
1091   case X86II::MRM_C1:
1092   case X86II::MRM_C2:
1093   case X86II::MRM_C3:
1094   case X86II::MRM_C4:
1095   case X86II::MRM_C5:
1096   case X86II::MRM_C6:
1097   case X86II::MRM_C7:
1098   case X86II::MRM_C8:
1099   case X86II::MRM_C9:
1100   case X86II::MRM_CA:
1101   case X86II::MRM_CB:
1102   case X86II::MRM_CC:
1103   case X86II::MRM_CD:
1104   case X86II::MRM_CE:
1105   case X86II::MRM_CF:
1106   case X86II::MRM_D0:
1107   case X86II::MRM_D1:
1108   case X86II::MRM_D2:
1109   case X86II::MRM_D3:
1110   case X86II::MRM_D4:
1111   case X86II::MRM_D5:
1112   case X86II::MRM_D6:
1113   case X86II::MRM_D7:
1114   case X86II::MRM_D8:
1115   case X86II::MRM_D9:
1116   case X86II::MRM_DA:
1117   case X86II::MRM_DB:
1118   case X86II::MRM_DC:
1119   case X86II::MRM_DD:
1120   case X86II::MRM_DE:
1121   case X86II::MRM_DF:
1122   case X86II::MRM_E0:
1123   case X86II::MRM_E1:
1124   case X86II::MRM_E2:
1125   case X86II::MRM_E3:
1126   case X86II::MRM_E4:
1127   case X86II::MRM_E5:
1128   case X86II::MRM_E6:
1129   case X86II::MRM_E7:
1130   case X86II::MRM_E8:
1131   case X86II::MRM_E9:
1132   case X86II::MRM_EA:
1133   case X86II::MRM_EB:
1134   case X86II::MRM_EC:
1135   case X86II::MRM_ED:
1136   case X86II::MRM_EE:
1137   case X86II::MRM_EF:
1138   case X86II::MRM_F0:
1139   case X86II::MRM_F1:
1140   case X86II::MRM_F2:
1141   case X86II::MRM_F3:
1142   case X86II::MRM_F4:
1143   case X86II::MRM_F5:
1144   case X86II::MRM_F6:
1145   case X86II::MRM_F7:
1146   case X86II::MRM_F8:
1147   case X86II::MRM_F9:
1148   case X86II::MRM_FA:
1149   case X86II::MRM_FB:
1150   case X86II::MRM_FC:
1151   case X86II::MRM_FD:
1152   case X86II::MRM_FE:
1153   case X86II::MRM_FF:
1154     return -1;
1155   }
1156 }
1157
1158 /// \returns true if the register is a XMM.
1159 inline bool isXMMReg(MCRegister Reg) {
1160   static_assert(X86::XMM15 - X86::XMM0 == 15,
1161                 "XMM0-15 registers are not continuous");
1162   static_assert(X86::XMM31 - X86::XMM16 == 15,
1163                 "XMM16-31 registers are not continuous");
1164   return (Reg >= X86::XMM0 && Reg <= X86::XMM15) ||
1165          (Reg >= X86::XMM16 && Reg <= X86::XMM31);
1166 }
1167
1168 /// \returns true if the register is a YMM.
1169 inline bool isYMMReg(MCRegister Reg) {
1170   static_assert(X86::YMM15 - X86::YMM0 == 15,
1171                 "YMM0-15 registers are not continuous");
1172   static_assert(X86::YMM31 - X86::YMM16 == 15,
1173                 "YMM16-31 registers are not continuous");
1174   return (Reg >= X86::YMM0 && Reg <= X86::YMM15) ||
1175          (Reg >= X86::YMM16 && Reg <= X86::YMM31);
1176 }
1177
1178 /// \returns true if the register is a ZMM.
1179 inline bool isZMMReg(MCRegister Reg) {
1180   static_assert(X86::ZMM31 - X86::ZMM0 == 31,
1181                 "ZMM registers are not continuous");
1182   return Reg >= X86::ZMM0 && Reg <= X86::ZMM31;
1183 }
1184
1185 /// \returns true if \p Reg is an apx extended register.
1186 inline bool isApxExtendedReg(MCRegister Reg) {
1187   static_assert(X86::R31WH - X86::R16 == 95, "EGPRs are not continuous");
1188   return Reg >= X86::R16 && Reg <= X86::R31WH;
1189 }
1190
1191 /// \returns true if the MachineOperand is a x86-64 extended (r8 or
1192 /// higher) register,  e.g. r8, xmm8, xmm13, etc.
1193 inline bool isX86_64ExtendedReg(MCRegister Reg) {
1194   if ((Reg >= X86::XMM8 && Reg <= X86::XMM15) ||
1195       (Reg >= X86::XMM16 && Reg <= X86::XMM31) ||
1196       (Reg >= X86::YMM8 && Reg <= X86::YMM15) ||
1197       (Reg >= X86::YMM16 && Reg <= X86::YMM31) ||
1198       (Reg >= X86::ZMM8 && Reg <= X86::ZMM31))
1199     return true;
1200
1201   if (isApxExtendedReg(Reg))
1202     return true;
1203
1204   switch (Reg.id()) {
1205   default:
1206     break;
1207   case X86::R8:
1208   case X86::R9:
1209   case X86::R10:
1210   case X86::R11:
1211   case X86::R12:
1212   case X86::R13:
1213   case X86::R14:
1214   case X86::R15:
1215   case X86::R8D:
1216   case X86::R9D:
1217   case X86::R10D:
1218   case X86::R11D:
1219   case X86::R12D:
1220   case X86::R13D:
1221   case X86::R14D:
1222   case X86::R15D:
1223   case X86::R8W:
1224   case X86::R9W:
1225   case X86::R10W:
1226   case X86::R11W:
1227   case X86::R12W:
1228   case X86::R13W:
1229   case X86::R14W:
1230   case X86::R15W:
1231   case X86::R8B:
1232   case X86::R9B:
1233   case X86::R10B:
1234   case X86::R11B:
1235   case X86::R12B:
1236   case X86::R13B:
1237   case X86::R14B:
1238   case X86::R15B:
1239   case X86::CR8:
1240   case X86::CR9:
1241   case X86::CR10:
1242   case X86::CR11:
1243   case X86::CR12:
1244   case X86::CR13:
1245   case X86::CR14:
1246   case X86::CR15:
1247   case X86::DR8:
1248   case X86::DR9:
1249   case X86::DR10:
1250   case X86::DR11:
1251   case X86::DR12:
1252   case X86::DR13:
1253   case X86::DR14:
1254   case X86::DR15:
1255     return true;
1256   }
1257   return false;
1258 }
1259
1260 inline bool canUseApxExtendedReg(const MCInstrDesc &Desc) {
1261   uint64_t TSFlags = Desc.TSFlags;
1262   uint64_t Encoding = TSFlags & EncodingMask;
1263   // EVEX can always use egpr.
1264   if (Encoding == X86II::EVEX)
1265     return true;
1266
1267   unsigned Opcode = Desc.Opcode;
1268   // MOV32r0 is always expanded to XOR32rr
1269   if (Opcode == X86::MOV32r0)
1270     return true;
1271   // To be conservative, egpr is not used for all pseudo instructions
1272   // because we are not sure what instruction it will become.
1273   // FIXME: Could we improve it in X86ExpandPseudo?
1274   if (isPseudo(TSFlags))
1275     return false;
1276
1277   // MAP OB/TB in legacy encoding space can always use egpr except
1278   // XSAVE*/XRSTOR*.
1279   switch (Opcode) {
1280   default:
1281     break;
1282   case X86::XSAVE:
1283   case X86::XSAVE64:
1284   case X86::XSAVEOPT:
1285   case X86::XSAVEOPT64:
1286   case X86::XSAVEC:
1287   case X86::XSAVEC64:
1288   case X86::XSAVES:
1289   case X86::XSAVES64:
1290   case X86::XRSTOR:
1291   case X86::XRSTOR64:
1292   case X86::XRSTORS:
1293   case X86::XRSTORS64:
1294     return false;
1295   }
1296   uint64_t OpMap = TSFlags & X86II::OpMapMask;
1297   return !Encoding && (OpMap == X86II::OB || OpMap == X86II::TB);
1298 }
1299
1300 /// \returns true if the MemoryOperand is a 32 extended (zmm16 or higher)
1301 /// registers, e.g. zmm21, etc.
1302 static inline bool is32ExtendedReg(MCRegister Reg) {
1303   return ((Reg >= X86::XMM16 && Reg <= X86::XMM31) ||
1304           (Reg >= X86::YMM16 && Reg <= X86::YMM31) ||
1305           (Reg >= X86::ZMM16 && Reg <= X86::ZMM31));
1306 }
1307
1308 inline bool isX86_64NonExtLowByteReg(MCRegister Reg) {
1309   return (Reg == X86::SPL || Reg == X86::BPL || Reg == X86::SIL ||
1310           Reg == X86::DIL);
1311 }
1312
1313 /// \returns true if this is a masked instruction.
1314 inline bool isKMasked(uint64_t TSFlags) {
1315   return (TSFlags & X86II::EVEX_K) != 0;
1316 }
1317
1318 /// \returns true if this is a merge masked instruction.
1319 inline bool isKMergeMasked(uint64_t TSFlags) {
1320   return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0;
1321 }
1322
1323 /// \returns true if the intruction needs a SIB.
1324 inline bool needSIB(MCRegister BaseReg, MCRegister IndexReg, bool In64BitMode) {
1325   // The SIB byte must be used if there is an index register.
1326   if (IndexReg)
1327     return true;
1328
1329   // The SIB byte must be used if the base is ESP/RSP/R12/R20/R28, all of
1330   // which encode to an R/M value of 4, which indicates that a SIB byte is
1331   // present.
1332   switch (BaseReg.id()) {
1333   default:
1334     // If there is no base register and we're in 64-bit mode, we need a SIB
1335     // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
1336     return In64BitMode && !BaseReg;
1337   case X86::ESP:
1338   case X86::RSP:
1339   case X86::R12:
1340   case X86::R12D:
1341   case X86::R20:
1342   case X86::R20D:
1343   case X86::R28:
1344   case X86::R28D:
1345     return true;
1346   }
1347 }
1348
1349 } // namespace X86II
1350 } // namespace llvm
1351 #endif