1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 // X86 Instruction Format Definitions.
13 // Format specifies the encoding used by the instruction. This is part of the
14 // ad-hoc solution used to emit machine instruction encodings by our machine
16 class Format<bits<7> val> {
20 def Pseudo : Format<0>;
21 def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>;
23 def RawFrmMemOffs : Format<3>;
24 def RawFrmSrc : Format<4>;
25 def RawFrmDst : Format<5>;
26 def RawFrmDstSrc : Format<6>;
27 def RawFrmImm8 : Format<7>;
28 def RawFrmImm16 : Format<8>;
29 def AddCCFrm : Format<9>;
30 def PrefixByte : Format<10>;
31 def MRMDestRegCC : Format<18>;
32 def MRMDestMemCC : Format<19>;
33 def MRMDestMem4VOp3CC : Format<20>;
34 def MRMr0 : Format<21>;
35 def MRMSrcMemFSIB : Format<22>;
36 def MRMDestMemFSIB : Format<23>;
37 def MRMDestMem : Format<24>;
38 def MRMSrcMem : Format<25>;
39 def MRMSrcMem4VOp3 : Format<26>;
40 def MRMSrcMemOp4 : Format<27>;
41 def MRMSrcMemCC : Format<28>;
42 def MRMXmCC: Format<30>;
43 def MRMXm : Format<31>;
44 def MRM0m : Format<32>; def MRM1m : Format<33>; def MRM2m : Format<34>;
45 def MRM3m : Format<35>; def MRM4m : Format<36>; def MRM5m : Format<37>;
46 def MRM6m : Format<38>; def MRM7m : Format<39>;
47 def MRMDestReg : Format<40>;
48 def MRMSrcReg : Format<41>;
49 def MRMSrcReg4VOp3 : Format<42>;
50 def MRMSrcRegOp4 : Format<43>;
51 def MRMSrcRegCC : Format<44>;
52 def MRMXrCC: Format<46>;
53 def MRMXr : Format<47>;
54 def MRM0r : Format<48>; def MRM1r : Format<49>; def MRM2r : Format<50>;
55 def MRM3r : Format<51>; def MRM4r : Format<52>; def MRM5r : Format<53>;
56 def MRM6r : Format<54>; def MRM7r : Format<55>;
57 def MRM0X : Format<56>; def MRM1X : Format<57>; def MRM2X : Format<58>;
58 def MRM3X : Format<59>; def MRM4X : Format<60>; def MRM5X : Format<61>;
59 def MRM6X : Format<62>; def MRM7X : Format<63>;
60 def MRM_C0 : Format<64>; def MRM_C1 : Format<65>; def MRM_C2 : Format<66>;
61 def MRM_C3 : Format<67>; def MRM_C4 : Format<68>; def MRM_C5 : Format<69>;
62 def MRM_C6 : Format<70>; def MRM_C7 : Format<71>; def MRM_C8 : Format<72>;
63 def MRM_C9 : Format<73>; def MRM_CA : Format<74>; def MRM_CB : Format<75>;
64 def MRM_CC : Format<76>; def MRM_CD : Format<77>; def MRM_CE : Format<78>;
65 def MRM_CF : Format<79>; def MRM_D0 : Format<80>; def MRM_D1 : Format<81>;
66 def MRM_D2 : Format<82>; def MRM_D3 : Format<83>; def MRM_D4 : Format<84>;
67 def MRM_D5 : Format<85>; def MRM_D6 : Format<86>; def MRM_D7 : Format<87>;
68 def MRM_D8 : Format<88>; def MRM_D9 : Format<89>; def MRM_DA : Format<90>;
69 def MRM_DB : Format<91>; def MRM_DC : Format<92>; def MRM_DD : Format<93>;
70 def MRM_DE : Format<94>; def MRM_DF : Format<95>; def MRM_E0 : Format<96>;
71 def MRM_E1 : Format<97>; def MRM_E2 : Format<98>; def MRM_E3 : Format<99>;
72 def MRM_E4 : Format<100>; def MRM_E5 : Format<101>; def MRM_E6 : Format<102>;
73 def MRM_E7 : Format<103>; def MRM_E8 : Format<104>; def MRM_E9 : Format<105>;
74 def MRM_EA : Format<106>; def MRM_EB : Format<107>; def MRM_EC : Format<108>;
75 def MRM_ED : Format<109>; def MRM_EE : Format<110>; def MRM_EF : Format<111>;
76 def MRM_F0 : Format<112>; def MRM_F1 : Format<113>; def MRM_F2 : Format<114>;
77 def MRM_F3 : Format<115>; def MRM_F4 : Format<116>; def MRM_F5 : Format<117>;
78 def MRM_F6 : Format<118>; def MRM_F7 : Format<119>; def MRM_F8 : Format<120>;
79 def MRM_F9 : Format<121>; def MRM_FA : Format<122>; def MRM_FB : Format<123>;
80 def MRM_FC : Format<124>; def MRM_FD : Format<125>; def MRM_FE : Format<126>;
81 def MRM_FF : Format<127>;
83 // ImmType - This specifies the immediate type used by an instruction. This is
84 // part of the ad-hoc solution used to emit machine instruction encodings by our
85 // machine code emitter.
86 class ImmType<bits<4> val> {
89 def NoImm : ImmType<0>;
90 def Imm8 : ImmType<1>;
91 def Imm8PCRel : ImmType<2>;
92 def Imm8Reg : ImmType<3>; // Register encoded in [7:4].
93 def Imm16 : ImmType<4>;
94 def Imm16PCRel : ImmType<5>;
95 def Imm32 : ImmType<6>;
96 def Imm32PCRel : ImmType<7>;
97 def Imm32S : ImmType<8>;
98 def Imm64 : ImmType<9>;
100 // FPFormat - This specifies what form this FP instruction has. This is used by
101 // the Floating-Point stackifier pass.
102 class FPFormat<bits<3> val> {
105 def NotFP : FPFormat<0>;
106 def ZeroArgFP : FPFormat<1>;
107 def OneArgFP : FPFormat<2>;
108 def OneArgFPRW : FPFormat<3>;
109 def TwoArgFP : FPFormat<4>;
110 def CompareFP : FPFormat<5>;
111 def CondMovFP : FPFormat<6>;
112 def SpecialFP : FPFormat<7>;
114 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
115 // Keep in sync with tables in X86InstrInfo.cpp.
116 class Domain<bits<2> val> {
119 def GenericDomain : Domain<0>;
120 def SSEPackedSingle : Domain<1>;
121 def SSEPackedDouble : Domain<2>;
122 def SSEPackedInt : Domain<3>;
124 // Class specifying the vector form of the decompressed
125 // displacement of 8-bit.
126 class CD8VForm<bits<3> val> {
129 def CD8VF : CD8VForm<0>; // v := VL
130 def CD8VH : CD8VForm<1>; // v := VL/2
131 def CD8VQ : CD8VForm<2>; // v := VL/4
132 def CD8VO : CD8VForm<3>; // v := VL/8
133 // The tuple (subvector) forms.
134 def CD8VT1 : CD8VForm<4>; // v := 1
135 def CD8VT2 : CD8VForm<5>; // v := 2
136 def CD8VT4 : CD8VForm<6>; // v := 4
137 def CD8VT8 : CD8VForm<7>; // v := 8
139 // Class specifying the prefix used an opcode extension.
140 class Prefix<bits<3> val> {
143 def NoPrfx : Prefix<0>;
147 def PS : Prefix<4>; // Similar to NoPrfx, but disassembler uses this to know
148 // that other instructions with this opcode use PD/XS/XD
149 // and if any of those is not supported they shouldn't
150 // decode to this instruction. e.g. ANDSS/ANDSD don't
151 // exist, but the 0xf2/0xf3 encoding shouldn't
154 // Class specifying the opcode map.
155 class Map<bits<4> val> {
165 def ThreeDNow : Map<7>;
168 def T_MAP6 : Map<10>;
169 def T_MAP7 : Map<11>;
171 // Class specifying the encoding
172 class Encoding<bits<2> val> {
175 def EncNormal : Encoding<0>;
176 def EncVEX : Encoding<1>;
177 def EncXOP : Encoding<2>;
178 def EncEVEX : Encoding<3>;
180 // Operand size for encodings that change based on mode.
181 class OperandSize<bits<2> val> {
184 def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
185 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32/64-bit mode.
186 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
188 // Address size for encodings that change based on mode.
189 class AddressSize<bits<2> val> {
192 def AdSizeX : AddressSize<0>; // Address size determined using addr operand.
193 def AdSize16 : AddressSize<1>; // Encodes a 16-bit address.
194 def AdSize32 : AddressSize<2>; // Encodes a 32-bit address.
195 def AdSize64 : AddressSize<3>; // Encodes a 64-bit address.
197 // Force the instruction to use REX2/VEX/EVEX encoding.
198 class ExplicitOpPrefix<bits<2> val> {
201 def NoExplicitOpPrefix : ExplicitOpPrefix<0>;
202 def ExplicitREX2 : ExplicitOpPrefix<1>;
203 def ExplicitVEX : ExplicitOpPrefix<2>;
204 def ExplicitEVEX : ExplicitOpPrefix<3>;
206 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
207 string AsmStr, Domain d = GenericDomain>
209 let Namespace = "X86";
211 bits<8> Opcode = opcod;
213 bits<7> FormBits = Form.Value;
216 dag OutOperandList = outs;
217 dag InOperandList = ins;
218 string AsmString = AsmStr;
220 // If this is a pseudo instruction, mark it isCodeGenOnly.
221 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
223 let HasPositionOrder = 1;
226 // Attributes specific to X86 instructions...
228 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's
229 // isCodeGenonly. Needed to hide an ambiguous
230 // AsmString from the parser, but still disassemble.
232 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
233 // based on operand size of the mode?
234 bits<2> OpSizeBits = OpSize.Value;
235 AddressSize AdSize = AdSizeX; // Does this instruction's encoding change
236 // based on address size of the mode?
237 bits<2> AdSizeBits = AdSize.Value;
239 Encoding OpEnc = EncNormal; // Encoding used by this instruction
240 // Which prefix byte does this inst have?
241 Prefix OpPrefix = !if(!eq(OpEnc, EncNormal), NoPrfx, PS);
242 bits<3> OpPrefixBits = OpPrefix.Value;
243 Map OpMap = OB; // Which opcode map does this inst have?
244 bits<4> OpMapBits = OpMap.Value;
245 bit hasREX_W = 0; // Does this inst require the REX.W prefix?
246 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
247 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
248 Domain ExeDomain = d;
249 bit hasREPPrefix = 0; // Does this inst have a REP prefix?
250 bits<2> OpEncBits = OpEnc.Value;
251 bit IgnoresW = 0; // Does this inst ignore REX_W field?
252 bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field?
253 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
254 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
255 bit hasEVEX_K = 0; // Does this inst require masking?
256 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field?
257 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field?
258 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field?
259 bit hasEVEX_NF = 0; // Does this inst set the EVEX_NF field?
260 bit hasTwoConditionalOps = 0; // Does this inst have two conditional operands?
261 bits<3> CD8_Form = 0; // Compressed disp8 form - vector-width.
262 // Declare it int rather than bits<4> so that all bits are defined when
263 // assigning to bits<7>.
264 int CD8_EltSize = 0; // Compressed disp8 form - element-size in bytes.
265 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction.
266 bit hasNoTrackPrefix = 0; // Does this inst has 0x3E (NoTrack) prefix?
268 // Vector size in bytes.
269 bits<7> VectSize = !if(hasEVEX_L2, 64, !if(hasVEX_L, 32, 16));
271 // The scaling factor for AVX512's compressed displacement is either
272 // - the size of a power-of-two number of elements or
273 // - the size of a single element for broadcasts or
274 // - the total vector size divided by a power-of-two number.
275 // Possible values are: 0 (non-AVX512 inst), 1, 2, 4, 8, 16, 32 and 64.
276 bits<7> CD8_Scale = !if (!eq (OpEnc.Value, EncEVEX.Value),
278 !shl(CD8_EltSize, CD8_Form{1-0}),
281 !srl(VectSize, CD8_Form{1-0}))), 0);
283 ExplicitOpPrefix explicitOpPrefix = NoExplicitOpPrefix;
284 bits<2> explicitOpPrefixBits = explicitOpPrefix.Value;
285 bit hasEVEX_U = 0; // Does this inst set the EVEX_U field?
286 // TSFlags layout should be kept in sync with X86BaseInfo.h.
287 let TSFlags{6-0} = FormBits;
288 let TSFlags{8-7} = OpSizeBits;
289 let TSFlags{10-9} = AdSizeBits;
290 // No need for 3rd bit, we don't need to distinguish NoPrfx from PS.
291 let TSFlags{12-11} = OpPrefixBits{1-0};
292 let TSFlags{16-13} = OpMapBits;
293 let TSFlags{17} = hasREX_W;
294 let TSFlags{21-18} = ImmT.Value;
295 let TSFlags{24-22} = FPForm.Value;
296 let TSFlags{25} = hasLockPrefix;
297 let TSFlags{26} = hasREPPrefix;
298 let TSFlags{28-27} = ExeDomain.Value;
299 let TSFlags{30-29} = OpEncBits;
300 let TSFlags{38-31} = Opcode;
301 let TSFlags{39} = hasVEX_4V;
302 let TSFlags{40} = hasVEX_L;
303 let TSFlags{41} = hasEVEX_K;
304 let TSFlags{42} = hasEVEX_Z;
305 let TSFlags{43} = hasEVEX_L2;
306 let TSFlags{44} = hasEVEX_B;
307 let TSFlags{47-45} = !if(!eq(CD8_Scale, 0), 0, !add(!logtwo(CD8_Scale), 1));
308 let TSFlags{48} = hasEVEX_RC;
309 let TSFlags{49} = hasNoTrackPrefix;
310 let TSFlags{51-50} = explicitOpPrefixBits;
311 let TSFlags{52} = hasEVEX_NF;
312 let TSFlags{53} = hasTwoConditionalOps;
313 let TSFlags{54} = hasEVEX_U;