llvm/lib/Target/X86/X86InstrFragments.td

   1 //===----------X86InstrFragments - X86 Pattern fragments. --*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 // X86-specific DAG node.
  10 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
  11                                          SDTCisSameAs<1, 2>]>;
  12 def SDTX86FCmp    : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisFP<1>,
  13                                          SDTCisSameAs<1, 2>]>;
  14
  15 def SDTX86Ccmp    : SDTypeProfile<1, 5,
  16                                   [SDTCisVT<3, i8>, SDTCisVT<4, i8>, SDTCisVT<5, i32>]>;
  17
  18 // RES = op PTR, PASSTHRU, COND, EFLAGS
  19 def SDTX86Cload    : SDTypeProfile<1, 4,
  20                                   [SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisSameAs<0, 2>,
  21                                    SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
  22 // op VAL, PTR, COND, EFLAGS
  23 def SDTX86Cstore    : SDTypeProfile<0, 4,
  24                                   [SDTCisInt<0>, SDTCisPtrTy<1>,
  25                                    SDTCisVT<2, i8>, SDTCisVT<3, i32>]>;
  26
  27 def SDTX86Cmov    : SDTypeProfile<1, 4,
  28                                   [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  29                                    SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
  30
  31 // Unary and binary operator instructions that set EFLAGS as a side-effect.
  32 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
  33                                            [SDTCisSameAs<0, 2>,
  34                                             SDTCisInt<0>, SDTCisVT<1, i32>]>;
  35
  36 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
  37                                             [SDTCisSameAs<0, 2>,
  38                                              SDTCisSameAs<0, 3>,
  39                                              SDTCisInt<0>, SDTCisVT<1, i32>]>;
  40
  41 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
  42 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
  43                                             [SDTCisSameAs<0, 2>,
  44                                              SDTCisSameAs<0, 3>,
  45                                              SDTCisInt<0>,
  46                                              SDTCisVT<1, i32>,
  47                                              SDTCisVT<4, i32>]>;
  48
  49 def SDTX86BrCond  : SDTypeProfile<0, 3,
  50                                   [SDTCisVT<0, OtherVT>,
  51                                    SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
  52
  53 def SDTX86SetCC   : SDTypeProfile<1, 2,
  54                                   [SDTCisVT<0, i8>,
  55                                    SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
  56 def SDTX86SetCC_C : SDTypeProfile<1, 2,
  57                                   [SDTCisInt<0>,
  58                                    SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
  59
  60 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
  61
  62 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
  63
  64 def SDTX86rdpkru : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
  65 def SDTX86wrpkru : SDTypeProfile<0, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
  66                                         SDTCisVT<2, i32>]>;
  67
  68 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
  69                                      SDTCisVT<2, i8>]>;
  70 def SDTX86cas8pair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
  71 def SDTX86cas16pair : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i64>]>;
  72
  73 def SDTLockBinaryArithWithFlags : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
  74                                                        SDTCisPtrTy<1>,
  75                                                        SDTCisInt<2>]>;
  76
  77 def SDTLockUnaryArithWithFlags : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
  78                                                       SDTCisPtrTy<1>]>;
  79
  80 def SDTX86Ret     : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
  81
  82 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
  83                                           SDTCisVT<1, i32>]>;
  84 def SDT_X86CallSeqEnd   : SDCallSeqEnd<[SDTCisVT<0, i32>,
  85                                         SDTCisVT<1, i32>]>;
  86
  87 def SDT_X86Call   : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
  88
  89 def SDT_X86NtBrind : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
  90
  91 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
  92                                                          SDTCisPtrTy<1>]>;
  93
  94 def SDT_X86VAARG : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
  95                                          SDTCisPtrTy<1>,
  96                                          SDTCisVT<2, i32>,
  97                                          SDTCisVT<3, i8>,
  98                                          SDTCisVT<4, i32>]>;
  99
 100 def SDTX86RepStr  : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
 101
 102 def SDTX86Void    : SDTypeProfile<0, 0, []>;
 103
 104 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
 105
 106 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 107
 108 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 109
 110 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 111
 112 def SDT_X86DYN_ALLOCA : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
 113
 114 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
 115
 116 def SDT_X86PROBED_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
 117
 118 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 119
 120 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
 121
 122 def SDT_X86ENQCMD : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
 123                                          SDTCisPtrTy<1>, SDTCisSameAs<1, 2>]>;
 124
 125 def SDT_X86AESENCDECKL : SDTypeProfile<2, 2, [SDTCisVT<0, v2i64>,
 126                                               SDTCisVT<1, i32>,
 127                                               SDTCisVT<2, v2i64>,
 128                                               SDTCisPtrTy<3>]>;
 129
 130 def SDTX86Cmpccxadd : SDTypeProfile<1, 4, [SDTCisSameAs<0, 2>,
 131                                            SDTCisPtrTy<1>, SDTCisSameAs<2, 3>,
 132                                            SDTCisVT<4, i8>]>;
 133
 134 def X86MFence : SDNode<"X86ISD::MFENCE", SDTNone, [SDNPHasChain]>;
 135
 136
 137 def X86bsf     : SDNode<"X86ISD::BSF",      SDTUnaryArithWithFlags>;
 138 def X86bsr     : SDNode<"X86ISD::BSR",      SDTUnaryArithWithFlags>;
 139 def X86fshl    : SDNode<"X86ISD::FSHL",     SDTIntShiftDOp>;
 140 def X86fshr    : SDNode<"X86ISD::FSHR",     SDTIntShiftDOp>;
 141
 142 def X86cmp     : SDNode<"X86ISD::CMP" ,     SDTX86CmpTest>;
 143 def X86fcmp    : SDNode<"X86ISD::FCMP",     SDTX86FCmp>;
 144 def X86strict_fcmp : SDNode<"X86ISD::STRICT_FCMP", SDTX86FCmp, [SDNPHasChain]>;
 145 def X86strict_fcmps : SDNode<"X86ISD::STRICT_FCMPS", SDTX86FCmp, [SDNPHasChain]>;
 146 def X86bt      : SDNode<"X86ISD::BT",       SDTX86CmpTest>;
 147
 148 def X86ccmp    : SDNode<"X86ISD::CCMP",     SDTX86Ccmp>;
 149 def X86ctest   : SDNode<"X86ISD::CTEST",    SDTX86Ccmp>;
 150
 151 def X86cload    : SDNode<"X86ISD::CLOAD",   SDTX86Cload, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 152 def X86cstore   : SDNode<"X86ISD::CSTORE",  SDTX86Cstore, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 153
 154 def X86cmov    : SDNode<"X86ISD::CMOV",     SDTX86Cmov>;
 155 def X86brcond  : SDNode<"X86ISD::BRCOND",   SDTX86BrCond,
 156                         [SDNPHasChain]>;
 157 def X86setcc   : SDNode<"X86ISD::SETCC",    SDTX86SetCC>;
 158 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
 159
 160 def X86rdrand  : SDNode<"X86ISD::RDRAND",   SDTX86rdrand,
 161                         [SDNPHasChain, SDNPSideEffect]>;
 162
 163 def X86rdseed  : SDNode<"X86ISD::RDSEED",   SDTX86rdrand,
 164                         [SDNPHasChain, SDNPSideEffect]>;
 165
 166 def X86rdpkru : SDNode<"X86ISD::RDPKRU",    SDTX86rdpkru,
 167                        [SDNPHasChain, SDNPSideEffect]>;
 168 def X86wrpkru : SDNode<"X86ISD::WRPKRU",    SDTX86wrpkru,
 169                        [SDNPHasChain, SDNPSideEffect]>;
 170
 171 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
 172                         [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
 173                          SDNPMayLoad, SDNPMemOperand]>;
 174 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8pair,
 175                         [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
 176                          SDNPMayLoad, SDNPMemOperand]>;
 177 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86cas16pair,
 178                         [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
 179                          SDNPMayLoad, SDNPMemOperand]>;
 180
 181 def X86retglue : SDNode<"X86ISD::RET_GLUE", SDTX86Ret,
 182                         [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
 183 def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret,
 184                         [SDNPHasChain, SDNPOptInGlue]>;
 185
 186 def X86vastart_save_xmm_regs :
 187                  SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
 188                         SDT_X86VASTART_SAVE_XMM_REGS,
 189                         [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPVariadic]>;
 190 def X86vaarg64 :
 191                  SDNode<"X86ISD::VAARG_64", SDT_X86VAARG,
 192                         [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
 193                          SDNPMemOperand]>;
 194 def X86vaargx32 :
 195                  SDNode<"X86ISD::VAARG_X32", SDT_X86VAARG,
 196                         [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
 197                          SDNPMemOperand]>;
 198 def X86callseq_start :
 199                  SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
 200                         [SDNPHasChain, SDNPOutGlue]>;
 201 def X86callseq_end :
 202                  SDNode<"ISD::CALLSEQ_END",   SDT_X86CallSeqEnd,
 203                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 204
 205 def X86call    : SDNode<"X86ISD::CALL",     SDT_X86Call,
 206                         [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
 207                          SDNPVariadic]>;
 208
 209 def X86call_rvmarker  : SDNode<"X86ISD::CALL_RVMARKER",     SDT_X86Call,
 210                         [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
 211                          SDNPVariadic]>;
 212
 213
 214 def X86NoTrackCall : SDNode<"X86ISD::NT_CALL", SDT_X86Call,
 215                             [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
 216                              SDNPVariadic]>;
 217 def X86NoTrackBrind : SDNode<"X86ISD::NT_BRIND", SDT_X86NtBrind,
 218                              [SDNPHasChain]>;
 219
 220 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
 221                         [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
 222 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
 223                         [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
 224                          SDNPMayLoad]>;
 225
 226 def X86Wrapper    : SDNode<"X86ISD::Wrapper",     SDTX86Wrapper>;
 227 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP",  SDTX86Wrapper>;
 228
 229 def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER",
 230                                   SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
 231                                                        SDTCisInt<1>]>>;
 232
 233 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
 234                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 235
 236 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
 237                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 238
 239 def X86tlsdesc : SDNode<"X86ISD::TLSDESC", SDT_X86TLSADDR,
 240                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 241
 242 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
 243                         [SDNPHasChain]>;
 244
 245 def X86eh_sjlj_setjmp  : SDNode<"X86ISD::EH_SJLJ_SETJMP",
 246                                 SDTypeProfile<1, 1, [SDTCisInt<0>,
 247                                                      SDTCisPtrTy<1>]>,
 248                                 [SDNPHasChain, SDNPSideEffect]>;
 249 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
 250                                 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
 251                                 [SDNPHasChain, SDNPSideEffect]>;
 252 def X86eh_sjlj_setup_dispatch : SDNode<"X86ISD::EH_SJLJ_SETUP_DISPATCH",
 253                                        SDTypeProfile<0, 0, []>,
 254                                        [SDNPHasChain, SDNPSideEffect]>;
 255
 256 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
 257                         [SDNPHasChain,  SDNPOptInGlue, SDNPVariadic]>;
 258
 259 def X86add_flag  : SDNode<"X86ISD::ADD",  SDTBinaryArithWithFlags,
 260                           [SDNPCommutative]>;
 261 def X86sub_flag  : SDNode<"X86ISD::SUB",  SDTBinaryArithWithFlags>;
 262 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
 263                           [SDNPCommutative]>;
 264 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTBinaryArithWithFlags,
 265                           [SDNPCommutative]>;
 266 def X86adc_flag  : SDNode<"X86ISD::ADC",  SDTBinaryArithWithFlagsInOut>;
 267 def X86sbb_flag  : SDNode<"X86ISD::SBB",  SDTBinaryArithWithFlagsInOut>;
 268
 269 def X86or_flag   : SDNode<"X86ISD::OR",   SDTBinaryArithWithFlags,
 270                           [SDNPCommutative]>;
 271 def X86xor_flag  : SDNode<"X86ISD::XOR",  SDTBinaryArithWithFlags,
 272                           [SDNPCommutative]>;
 273 def X86and_flag  : SDNode<"X86ISD::AND",  SDTBinaryArithWithFlags,
 274                           [SDNPCommutative]>;
 275
 276 def X86lock_add  : SDNode<"X86ISD::LADD",  SDTLockBinaryArithWithFlags,
 277                           [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
 278                            SDNPMemOperand]>;
 279 def X86lock_sub  : SDNode<"X86ISD::LSUB",  SDTLockBinaryArithWithFlags,
 280                           [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
 281                            SDNPMemOperand]>;
 282 def X86lock_or  : SDNode<"X86ISD::LOR",  SDTLockBinaryArithWithFlags,
 283                          [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
 284                           SDNPMemOperand]>;
 285 def X86lock_xor  : SDNode<"X86ISD::LXOR",  SDTLockBinaryArithWithFlags,
 286                           [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
 287                            SDNPMemOperand]>;
 288 def X86lock_and  : SDNode<"X86ISD::LAND",  SDTLockBinaryArithWithFlags,
 289                           [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
 290                            SDNPMemOperand]>;
 291
 292 def X86bextr  : SDNode<"X86ISD::BEXTR",  SDTIntBinOp>;
 293 def X86bextri : SDNode<"X86ISD::BEXTRI", SDTIntBinOp>;
 294
 295 def X86bzhi   : SDNode<"X86ISD::BZHI",   SDTIntBinOp>;
 296
 297 def X86pdep   : SDNode<"X86ISD::PDEP",   SDTIntBinOp>;
 298 def X86pext   : SDNode<"X86ISD::PEXT",   SDTIntBinOp>;
 299
 300 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
 301
 302 def X86DynAlloca : SDNode<"X86ISD::DYN_ALLOCA", SDT_X86DYN_ALLOCA,
 303                           [SDNPHasChain, SDNPOutGlue]>;
 304
 305 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
 306                           [SDNPHasChain]>;
 307
 308 def X86ProbedAlloca : SDNode<"X86ISD::PROBED_ALLOCA", SDT_X86PROBED_ALLOCA,
 309                           [SDNPHasChain]>;
 310
 311 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
 312                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 313
 314 def X86lwpins : SDNode<"X86ISD::LWPINS",
 315                        SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>,
 316                                             SDTCisVT<2, i32>, SDTCisVT<3, i32>]>,
 317                        [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>;
 318
 319 def X86umwait : SDNode<"X86ISD::UMWAIT",
 320                        SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>,
 321                                             SDTCisVT<2, i32>, SDTCisVT<3, i32>]>,
 322                        [SDNPHasChain, SDNPSideEffect]>;
 323
 324 def X86tpause : SDNode<"X86ISD::TPAUSE",
 325                        SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>,
 326                                             SDTCisVT<2, i32>, SDTCisVT<3, i32>]>,
 327                        [SDNPHasChain, SDNPSideEffect]>;
 328
 329 def X86enqcmd : SDNode<"X86ISD::ENQCMD", SDT_X86ENQCMD,
 330                        [SDNPHasChain, SDNPSideEffect]>;
 331 def X86enqcmds : SDNode<"X86ISD::ENQCMDS", SDT_X86ENQCMD,
 332                        [SDNPHasChain, SDNPSideEffect]>;
 333 def X86testui : SDNode<"X86ISD::TESTUI",
 334                        SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>,
 335                        [SDNPHasChain, SDNPSideEffect]>;
 336
 337 def X86aesenc128kl : SDNode<"X86ISD::AESENC128KL", SDT_X86AESENCDECKL,
 338                             [SDNPHasChain, SDNPMayLoad, SDNPSideEffect,
 339                              SDNPMemOperand]>;
 340 def X86aesdec128kl : SDNode<"X86ISD::AESDEC128KL", SDT_X86AESENCDECKL,
 341                             [SDNPHasChain, SDNPMayLoad, SDNPSideEffect,
 342                              SDNPMemOperand]>;
 343 def X86aesenc256kl : SDNode<"X86ISD::AESENC256KL", SDT_X86AESENCDECKL,
 344                             [SDNPHasChain, SDNPMayLoad, SDNPSideEffect,
 345                              SDNPMemOperand]>;
 346 def X86aesdec256kl : SDNode<"X86ISD::AESDEC256KL", SDT_X86AESENCDECKL,
 347                             [SDNPHasChain, SDNPMayLoad, SDNPSideEffect,
 348                              SDNPMemOperand]>;
 349
 350 def X86cmpccxadd : SDNode<"X86ISD::CMPCCXADD", SDTX86Cmpccxadd,
 351                           [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
 352                            SDNPMemOperand]>;
 353
 354 // Define X86-specific addressing mode.
 355 let WantsParent = true in
 356 def addr      : ComplexPattern<iPTR, 5, "selectAddr">;
 357 def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr",
 358                                [add, sub, mul, X86mul_imm, shl, or, xor, frameindex],
 359                                []>;
 360 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
 361 def lea64_32addr : ComplexPattern<i32, 5, "selectLEA64_32Addr",
 362                                   [add, sub, mul, X86mul_imm, shl, or, xor,
 363                                    frameindex, X86WrapperRIP],
 364                                   []>;
 365
 366 def tls32addr : ComplexPattern<i32, 5, "selectTLSADDRAddr",
 367                                [tglobaltlsaddr], []>;
 368
 369 def tls32baseaddr : ComplexPattern<i32, 5, "selectTLSADDRAddr",
 370                                [tglobaltlsaddr], []>;
 371
 372 def lea64addr : ComplexPattern<i64, 5, "selectLEAAddr",
 373                         [add, sub, mul, X86mul_imm, shl, or, xor, frameindex,
 374                          X86WrapperRIP], []>;
 375
 376 def tls64addr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
 377                                [tglobaltlsaddr], []>;
 378
 379 def tls64baseaddr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
 380                                [tglobaltlsaddr], []>;
 381
 382 let WantsParent = true in
 383 def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr">;
 384
 385 // A relocatable immediate is an operand that can be relocated by the linker to
 386 // an immediate, such as a regular symbol in non-PIC code.
 387 def relocImm : ComplexPattern<iAny, 1, "selectRelocImm",
 388                               [X86Wrapper], [], 0>;
 389
 390 // X86 specific condition code. These correspond to CondCode in
 391 // X86InstrInfo.h. They must be kept in synch.
 392 def X86_COND_O   : PatLeaf<(i8 0)>;
 393 def X86_COND_NO  : PatLeaf<(i8 1)>;
 394 def X86_COND_B   : PatLeaf<(i8 2)>;  // alt. COND_C
 395 def X86_COND_AE  : PatLeaf<(i8 3)>;  // alt. COND_NC
 396 def X86_COND_E   : PatLeaf<(i8 4)>;  // alt. COND_Z
 397 def X86_COND_NE  : PatLeaf<(i8 5)>;  // alt. COND_NZ
 398 def X86_COND_BE  : PatLeaf<(i8 6)>;  // alt. COND_NA
 399 def X86_COND_A   : PatLeaf<(i8 7)>;  // alt. COND_NBE
 400 def X86_COND_S   : PatLeaf<(i8 8)>;
 401 def X86_COND_NS  : PatLeaf<(i8 9)>;
 402 def X86_COND_P   : PatLeaf<(i8 10)>; // alt. COND_PE
 403 def X86_COND_NP  : PatLeaf<(i8 11)>; // alt. COND_PO
 404 def X86_COND_L   : PatLeaf<(i8 12)>; // alt. COND_NGE
 405 def X86_COND_GE  : PatLeaf<(i8 13)>; // alt. COND_NL
 406 def X86_COND_LE  : PatLeaf<(i8 14)>; // alt. COND_NG
 407 def X86_COND_G   : PatLeaf<(i8 15)>; // alt. COND_NLE
 408
 409 def i16immSExt8  : ImmLeaf<i16, [{ return isInt<8>(Imm); }]>;
 410 def i32immSExt8  : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>;
 411 def i64immSExt8  : ImmLeaf<i64, [{ return isInt<8>(Imm); }]>;
 412 def i64immSExt32 : ImmLeaf<i64, [{ return isInt<32>(Imm); }]>;
 413 def i64timmSExt32 : TImmLeaf<i64, [{ return isInt<32>(Imm); }]>;
 414
 415 def i16relocImmSExt8 : PatLeaf<(i16 relocImm), [{
 416   return isSExtAbsoluteSymbolRef(8, N);
 417 }]>;
 418 def i32relocImmSExt8 : PatLeaf<(i32 relocImm), [{
 419   return isSExtAbsoluteSymbolRef(8, N);
 420 }]>;
 421 def i64relocImmSExt8 : PatLeaf<(i64 relocImm), [{
 422   return isSExtAbsoluteSymbolRef(8, N);
 423 }]>;
 424 def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{
 425   return isSExtAbsoluteSymbolRef(32, N);
 426 }]>;
 427
 428 // If we have multiple users of an immediate, it's much smaller to reuse
 429 // the register, rather than encode the immediate in every instruction.
 430 // This has the risk of increasing register pressure from stretched live
 431 // ranges, however, the immediates should be trivial to rematerialize by
 432 // the RA in the event of high register pressure.
 433 // TODO : This is currently enabled for stores and binary ops. There are more
 434 // cases for which this can be enabled, though this catches the bulk of the
 435 // issues.
 436 // TODO2 : This should really also be enabled under O2, but there's currently
 437 // an issue with RA where we don't pull the constants into their users
 438 // when we rematerialize them. I'll follow-up on enabling O2 after we fix that
 439 // issue.
 440 // TODO3 : This is currently limited to single basic blocks (DAG creation
 441 // pulls block immediates to the top and merges them if necessary).
 442 // Eventually, it would be nice to allow ConstantHoisting to merge constants
 443 // globally for potentially added savings.
 444 //
 445 def imm_su : PatLeaf<(imm), [{
 446     return !shouldAvoidImmediateInstFormsForSize(N);
 447 }]>;
 448 def i64immSExt32_su : PatLeaf<(i64immSExt32), [{
 449     return !shouldAvoidImmediateInstFormsForSize(N);
 450 }]>;
 451
 452 def relocImm8_su : PatLeaf<(i8 relocImm), [{
 453     return !shouldAvoidImmediateInstFormsForSize(N);
 454 }]>;
 455 def relocImm16_su : PatLeaf<(i16 relocImm), [{
 456     return !shouldAvoidImmediateInstFormsForSize(N);
 457 }]>;
 458 def relocImm32_su : PatLeaf<(i32 relocImm), [{
 459     return !shouldAvoidImmediateInstFormsForSize(N);
 460 }]>;
 461
 462 def i16relocImmSExt8_su : PatLeaf<(i16relocImmSExt8), [{
 463     return !shouldAvoidImmediateInstFormsForSize(N);
 464 }]>;
 465 def i32relocImmSExt8_su : PatLeaf<(i32relocImmSExt8), [{
 466     return !shouldAvoidImmediateInstFormsForSize(N);
 467 }]>;
 468 def i64relocImmSExt8_su : PatLeaf<(i64relocImmSExt8), [{
 469     return !shouldAvoidImmediateInstFormsForSize(N);
 470 }]>;
 471 def i64relocImmSExt32_su : PatLeaf<(i64relocImmSExt32), [{
 472     return !shouldAvoidImmediateInstFormsForSize(N);
 473 }]>;
 474
 475 def i16immSExt8_su : PatLeaf<(i16immSExt8), [{
 476     return !shouldAvoidImmediateInstFormsForSize(N);
 477 }]>;
 478 def i32immSExt8_su : PatLeaf<(i32immSExt8), [{
 479     return !shouldAvoidImmediateInstFormsForSize(N);
 480 }]>;
 481 def i64immSExt8_su : PatLeaf<(i64immSExt8), [{
 482     return !shouldAvoidImmediateInstFormsForSize(N);
 483 }]>;
 484
 485 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
 486 // unsigned field.
 487 def i64immZExt32 : ImmLeaf<i64, [{ return isUInt<32>(Imm); }]>;
 488
 489 def i64immZExt32SExt8 : ImmLeaf<i64, [{
 490   return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm));
 491 }]>;
 492
 493 // Helper fragments for loads.
 494
 495 // It's safe to fold a zextload/extload from i1 as a regular i8 load. The
 496 // upper bits are guaranteed to be zero and we were going to emit a MOV8rm
 497 // which might get folded during peephole anyway.
 498 def loadi8 : PatFrag<(ops node:$ptr), (i8 (unindexedload node:$ptr)), [{
 499   LoadSDNode *LD = cast<LoadSDNode>(N);
 500   ISD::LoadExtType ExtType = LD->getExtensionType();
 501   return ExtType == ISD::NON_EXTLOAD || ExtType == ISD::EXTLOAD ||
 502          ExtType == ISD::ZEXTLOAD;
 503 }]>;
 504
 505 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
 506 // known to be 32-bit aligned or better. Ditto for i8 to i16.
 507 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
 508   LoadSDNode *LD = cast<LoadSDNode>(N);
 509   ISD::LoadExtType ExtType = LD->getExtensionType();
 510   if (ExtType == ISD::NON_EXTLOAD)
 511     return true;
 512   if (ExtType == ISD::EXTLOAD && EnablePromoteAnyextLoad)
 513     return LD->getAlign() >= 2 && LD->isSimple();
 514   return false;
 515 }]>;
 516
 517 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
 518   LoadSDNode *LD = cast<LoadSDNode>(N);
 519   ISD::LoadExtType ExtType = LD->getExtensionType();
 520   if (ExtType == ISD::NON_EXTLOAD)
 521     return true;
 522   if (ExtType == ISD::EXTLOAD && EnablePromoteAnyextLoad)
 523     return LD->getAlign() >= 4 && LD->isSimple();
 524   return false;
 525 }]>;
 526
 527 def loadi64  : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
 528 def loadf16  : PatFrag<(ops node:$ptr), (f16 (load node:$ptr))>;
 529 def loadf32  : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
 530 def loadf64  : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
 531 def loadf80  : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
 532 def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>;
 533 def alignedloadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{
 534   LoadSDNode *Ld = cast<LoadSDNode>(N);
 535   return Ld->getAlign() >= Ld->getMemoryVT().getStoreSize();
 536 }]>;
 537 def memopf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{
 538   LoadSDNode *Ld = cast<LoadSDNode>(N);
 539   return Subtarget->hasSSEUnalignedMem() ||
 540          Ld->getAlign() >= Ld->getMemoryVT().getStoreSize();
 541 }]>;
 542
 543 def sextloadi16i8  : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
 544 def sextloadi32i8  : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
 545 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
 546 def sextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
 547 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
 548 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
 549
 550 def zextloadi8i1   : PatFrag<(ops node:$ptr), (i8  (zextloadi1 node:$ptr))>;
 551 def zextloadi16i1  : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
 552 def zextloadi32i1  : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
 553 def zextloadi16i8  : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
 554 def zextloadi32i8  : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
 555 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
 556 def zextloadi64i1  : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
 557 def zextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
 558 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
 559 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
 560
 561 def extloadi8i1    : PatFrag<(ops node:$ptr), (i8  (extloadi1 node:$ptr))>;
 562 def extloadi16i1   : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
 563 def extloadi32i1   : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
 564 def extloadi16i8   : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
 565 def extloadi32i8   : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
 566 def extloadi32i16  : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
 567 def extloadi64i1   : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
 568 def extloadi64i8   : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
 569 def extloadi64i16  : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
 570
 571 // We can treat an i8/i16 extending load to i64 as a 32 bit load if its known
 572 // to be 4 byte aligned or better.
 573 def extloadi64i32  : PatFrag<(ops node:$ptr), (i64 (unindexedload node:$ptr)), [{
 574   LoadSDNode *LD = cast<LoadSDNode>(N);
 575   ISD::LoadExtType ExtType = LD->getExtensionType();
 576   if (ExtType != ISD::EXTLOAD)
 577     return false;
 578   if (LD->getMemoryVT() == MVT::i32)
 579     return true;
 580
 581   return LD->getAlign() >= 4 && LD->isSimple();
 582 }]>;
 583
 584 // binary op with only one user
 585 class binop_oneuse<SDPatternOperator operator>
 586     : PatFrag<(ops node:$A, node:$B),
 587               (operator node:$A, node:$B), [{
 588   return N->hasOneUse();
 589 }]>;
 590
 591 def add_su : binop_oneuse<add>;
 592 def and_su : binop_oneuse<and>;
 593 def srl_su : binop_oneuse<srl>;
 594
 595 class binop_twouses<SDPatternOperator operator>
 596     : PatFrag<(ops node:$A, node:$B),
 597               (operator node:$A, node:$B), [{
 598   return N->hasNUsesOfValue(2, 0);
 599 }]>;
 600
 601 def and_du : binop_twouses<and>;
 602
 603 // unary op with only one user
 604 class unop_oneuse<SDPatternOperator operator>
 605     : PatFrag<(ops node:$A),
 606               (operator node:$A), [{
 607   return N->hasOneUse();
 608 }]>;
 609
 610
 611 def ineg_su : unop_oneuse<ineg>;
 612 def trunc_su : unop_oneuse<trunc>;
 613
 614 def X86add_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs),
 615                                (X86add_flag node:$lhs, node:$rhs), [{
 616   return hasNoCarryFlagUses(SDValue(N, 1));
 617 }]>;
 618
 619 def X86sub_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs),
 620                                (X86sub_flag node:$lhs, node:$rhs), [{
 621   // Only use DEC if the result is used.
 622   return !SDValue(N, 0).use_empty() && hasNoCarryFlagUses(SDValue(N, 1));
 623 }]>;
 624
 625 def X86testpat : PatFrag<(ops node:$lhs, node:$rhs),
 626                          (X86cmp (and_su node:$lhs, node:$rhs), 0)>;
 627 def X86ctestpat : PatFrag<(ops node:$lhs, node:$rhs, node:$dcf, node:$cond),
 628                           (X86ctest (and_du node:$lhs, node:$rhs),
 629                             (and_du node:$lhs, node:$rhs), node:$dcf,
 630                             node:$cond, EFLAGS)>;
 631
 632 def X86any_fcmp : PatFrags<(ops node:$lhs, node:$rhs),
 633                           [(X86strict_fcmp node:$lhs, node:$rhs),
 634                            (X86fcmp node:$lhs, node:$rhs)]>;
 635
 636 def PrefetchWLevel : PatFrag<(ops), (i32 timm), [{
 637   return N->getSExtValue() <= 3;
 638 }]>;
 639
 640 def X86lock_add_nocf : PatFrag<(ops node:$lhs, node:$rhs),
 641                                (X86lock_add node:$lhs, node:$rhs), [{
 642   return hasNoCarryFlagUses(SDValue(N, 0));
 643 }]>;
 644
 645 def X86lock_sub_nocf : PatFrag<(ops node:$lhs, node:$rhs),
 646                                (X86lock_sub node:$lhs, node:$rhs), [{
 647   return hasNoCarryFlagUses(SDValue(N, 0));
 648 }]>;
 649
 650 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
 651                              (X86tcret node:$ptr, node:$off), [{
 652   // X86tcret args: (*chain, ptr, imm, regs..., glue)
 653   unsigned NumRegs = 0;
 654   for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
 655     if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
 656       return false;
 657   return true;
 658 }]>;
 659
 660 def X86tcret_1reg : PatFrag<(ops node:$ptr, node:$off),
 661                              (X86tcret node:$ptr, node:$off), [{
 662   // X86tcret args: (*chain, ptr, imm, regs..., glue)
 663   unsigned NumRegs = 1;
 664   const SDValue& BasePtr = cast<LoadSDNode>(N->getOperand(1))->getBasePtr();
 665   if (isa<FrameIndexSDNode>(BasePtr))
 666     NumRegs = 3;
 667   else if (BasePtr->getNumOperands() && isa<GlobalAddressSDNode>(BasePtr->getOperand(0)))
 668     NumRegs = 3;
 669   for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
 670     if (isa<RegisterSDNode>(N->getOperand(i)) && ( NumRegs-- == 0))
 671       return false;
 672   return true;
 673 }]>;
 674
 675 // If this is an anyext of the remainder of an 8-bit sdivrem, use a MOVSX
 676 // instead of a MOVZX. The sdivrem lowering will emit emit a MOVSX to move
 677 // %ah to the lower byte of a register. By using a MOVSX here we allow a
 678 // post-isel peephole to merge the two MOVSX instructions into one.
 679 def anyext_sdiv : PatFrag<(ops node:$lhs), (anyext node:$lhs),[{
 680   return (N->getOperand(0).getOpcode() == ISD::SDIVREM &&
 681           N->getOperand(0).getResNo() == 1);
 682 }]>;
 683
 684 // Any instruction that defines a 32-bit result leaves the high half of the
 685 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
 686 // be copying from a truncate. AssertSext/AssertZext/AssertAlign aren't saying
 687 // anything about the upper 32 bits, they're probably just qualifying a
 688 // CopyFromReg. FREEZE may be coming from a a truncate. Any other 32-bit
 689 // operation will zero-extend up to 64 bits.
 690 def def32 : PatLeaf<(i32 GR32:$src), [{
 691   return N->getOpcode() != ISD::TRUNCATE &&
 692          N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
 693          N->getOpcode() != ISD::CopyFromReg &&
 694          N->getOpcode() != ISD::AssertSext &&
 695          N->getOpcode() != ISD::AssertZext &&
 696          N->getOpcode() != ISD::AssertAlign &&
 697          N->getOpcode() != ISD::FREEZE;
 698 }]>;
 699
 700 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
 701 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
 702   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
 703     return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
 704
 705   KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0);
 706   KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0);
 707   return (~Known0.Zero & ~Known1.Zero) == 0;
 708 }]>;
 709
 710 def shiftMask8 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{
 711   return isUnneededShiftMask(N, 3);
 712 }]>;
 713
 714 def shiftMask16 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{
 715   return isUnneededShiftMask(N, 4);
 716 }]>;
 717
 718 def shiftMask32 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{
 719   return isUnneededShiftMask(N, 5);
 720 }]>;
 721
 722 def shiftMask64 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{
 723   return isUnneededShiftMask(N, 6);
 724 }]>;
 725
 726 //===----------------------------------------------------------------------===//
 727 // Pattern fragments to auto generate BMI instructions.
 728 //===----------------------------------------------------------------------===//
 729
 730 def or_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs),
 731                            (X86or_flag node:$lhs, node:$rhs), [{
 732   return hasNoCarryFlagUses(SDValue(N, 1));
 733 }]>;
 734
 735 def xor_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs),
 736                             (X86xor_flag node:$lhs, node:$rhs), [{
 737   return hasNoCarryFlagUses(SDValue(N, 1));
 738 }]>;
 739
 740 def and_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs),
 741                             (X86and_flag node:$lhs, node:$rhs), [{
 742   return hasNoCarryFlagUses(SDValue(N, 1));
 743 }]>;
 744
 745 //===----------------------------------------------------------------------===//
 746 // FPStack specific DAG Nodes.
 747 //===----------------------------------------------------------------------===//
 748
 749 def SDTX86Fld       : SDTypeProfile<1, 1, [SDTCisFP<0>,
 750                                            SDTCisPtrTy<1>]>;
 751 def SDTX86Fst       : SDTypeProfile<0, 2, [SDTCisFP<0>,
 752                                            SDTCisPtrTy<1>]>;
 753 def SDTX86Fild      : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
 754 def SDTX86Fist      : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
 755
 756 def SDTX86CwdStore  : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
 757 def SDTX86CwdLoad   : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
 758 def SDTX86FPEnv     : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
 759
 760 def X86fp80_add     : SDNode<"X86ISD::FP80_ADD", SDTFPBinOp, [SDNPCommutative]>;
 761 def X86strict_fp80_add : SDNode<"X86ISD::STRICT_FP80_ADD", SDTFPBinOp,
 762                         [SDNPHasChain,SDNPCommutative]>;
 763 def any_X86fp80_add : PatFrags<(ops node:$lhs, node:$rhs),
 764                                [(X86strict_fp80_add node:$lhs, node:$rhs),
 765                                 (X86fp80_add node:$lhs, node:$rhs)]>;
 766
 767 def X86fld          : SDNode<"X86ISD::FLD", SDTX86Fld,
 768                              [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 769 def X86fst          : SDNode<"X86ISD::FST", SDTX86Fst,
 770                              [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 771 def X86fild         : SDNode<"X86ISD::FILD", SDTX86Fild,
 772                              [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 773 def X86fist         : SDNode<"X86ISD::FIST", SDTX86Fist,
 774                              [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 775 def X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst,
 776                           [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 777 def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m",          SDTX86CwdStore,
 778                              [SDNPHasChain, SDNPMayStore, SDNPSideEffect,
 779                               SDNPMemOperand]>;
 780 def X86fp_cwd_set16 : SDNode<"X86ISD::FLDCW16m",           SDTX86CwdLoad,
 781                              [SDNPHasChain, SDNPMayLoad, SDNPSideEffect,
 782                               SDNPMemOperand]>;
 783 def X86fpenv_get    : SDNode<"X86ISD::FNSTENVm",           SDTX86FPEnv,
 784                              [SDNPHasChain, SDNPMayStore, SDNPSideEffect,
 785                               SDNPMemOperand]>;
 786 def X86fpenv_set    : SDNode<"X86ISD::FLDENVm",            SDTX86FPEnv,
 787                              [SDNPHasChain, SDNPMayLoad, SDNPSideEffect,
 788                               SDNPMemOperand]>;
 789
 790 def X86fstf32 : PatFrag<(ops node:$val, node:$ptr),
 791                         (X86fst node:$val, node:$ptr), [{
 792   return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32;
 793 }]>;
 794 def X86fstf64 : PatFrag<(ops node:$val, node:$ptr),
 795                         (X86fst node:$val, node:$ptr), [{
 796   return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64;
 797 }]>;
 798 def X86fstf80 : PatFrag<(ops node:$val, node:$ptr),
 799                         (X86fst node:$val, node:$ptr), [{
 800   return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80;
 801 }]>;
 802
 803 def X86fldf32 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{
 804   return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32;
 805 }]>;
 806 def X86fldf64 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{
 807   return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64;
 808 }]>;
 809 def X86fldf80 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{
 810   return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80;
 811 }]>;
 812
 813 def X86fild16 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{
 814   return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
 815 }]>;
 816 def X86fild32 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{
 817   return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
 818 }]>;
 819 def X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{
 820   return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
 821 }]>;
 822
 823 def X86fist32 : PatFrag<(ops node:$val, node:$ptr),
 824                         (X86fist node:$val, node:$ptr), [{
 825   return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
 826 }]>;
 827
 828 def X86fist64 : PatFrag<(ops node:$val, node:$ptr),
 829                         (X86fist node:$val, node:$ptr), [{
 830   return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
 831 }]>;
 832
 833 def X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr),
 834                               (X86fp_to_mem node:$val, node:$ptr), [{
 835   return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
 836 }]>;
 837 def X86fp_to_i32mem : PatFrag<(ops node:$val, node:$ptr),
 838                               (X86fp_to_mem node:$val, node:$ptr), [{
 839   return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
 840 }]>;
 841 def X86fp_to_i64mem : PatFrag<(ops node:$val, node:$ptr),
 842                               (X86fp_to_mem node:$val, node:$ptr), [{
 843   return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
 844 }]>;
 845
 846 //===----------------------------------------------------------------------===//
 847 // FPStack pattern fragments
 848 //===----------------------------------------------------------------------===//
 849
 850 def fpimm0 : FPImmLeaf<fAny, [{
 851   return Imm.isExactlyValue(+0.0);
 852 }]>;
 853
 854 def fpimmneg0 : FPImmLeaf<fAny, [{
 855   return Imm.isExactlyValue(-0.0);
 856 }]>;
 857
 858 def fpimm1 : FPImmLeaf<fAny, [{
 859   return Imm.isExactlyValue(+1.0);
 860 }]>;
 861
 862 def fpimmneg1 : FPImmLeaf<fAny, [{
 863   return Imm.isExactlyValue(-1.0);
 864 }]>;