llvm/lib/Target/X86/X86PfmCounters.td

   1 //===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This describes the available hardware counters for various subtargets.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 def UnhaltedCoreCyclesPfmCounter : PfmCounter<"unhalted_core_cycles">;
  14 def UopsIssuedPfmCounter : PfmCounter<"uops_issued:any">;
  15
  16 // No default counters on X86.
  17 def DefaultPfmCounters : ProcPfmCounters {}
  18 def : PfmCountersDefaultBinding<DefaultPfmCounters>;
  19
  20 // Intel X86 Counters.
  21 defvar DefaultIntelPfmValidationCounters = [
  22   PfmValidationCounter<InstructionRetired, "INSTRUCTIONS_RETIRED">,
  23   PfmValidationCounter<L1DCacheLoadMiss, "MEM_LOAD_UOPS_RETIRED:L1_MISS">,
  24   PfmValidationCounter<L1ICacheLoadMiss, "L1-ICACHE-LOAD-MISSES">,
  25   PfmValidationCounter<DataTLBLoadMiss, "DTLB_LOAD_MISSES:MISS_CAUSES_A_WALK">,
  26   PfmValidationCounter<DataTLBStoreMiss, "DTLB_STORE_MISSES:MISS_CAUSES_A_WALK">,
  27   PfmValidationCounter<InstructionTLBLoadMiss, "ITLB_MISSES:MISS_CAUSES_A_WALK">,
  28   PfmValidationCounter<BranchPredictionMiss, "BRANCH-MISSES">
  29 ];
  30
  31 def PentiumPfmCounters : ProcPfmCounters {
  32   let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
  33   let UopsCounter = PfmCounter<"uops_retired">;
  34 }
  35 def : PfmCountersBinding<"pentiumpro", PentiumPfmCounters>;
  36 def : PfmCountersBinding<"pentium2", PentiumPfmCounters>;
  37 def : PfmCountersBinding<"pentium3", PentiumPfmCounters>;
  38 def : PfmCountersBinding<"pentium3m", PentiumPfmCounters>;
  39 def : PfmCountersBinding<"pentium-m", PentiumPfmCounters>;
  40
  41 def CorePfmCounters : ProcPfmCounters {
  42   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
  43   let UopsCounter = PfmCounter<"uops_retired:any">;
  44 }
  45 def : PfmCountersBinding<"yonah", CorePfmCounters>;
  46 def : PfmCountersBinding<"prescott", CorePfmCounters>;
  47
  48 def AtomPfmCounters : ProcPfmCounters {
  49   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
  50   let UopsCounter = PfmCounter<"uops_retired:any">;
  51 }
  52 def : PfmCountersBinding<"bonnell", AtomPfmCounters>;
  53 def : PfmCountersBinding<"atom", AtomPfmCounters>;
  54
  55 def SLMPfmCounters : ProcPfmCounters {
  56   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
  57   let UopsCounter = PfmCounter<"uops_retired:any">;
  58   let IssueCounters = [
  59     PfmIssueCounter<"SLM_MEC_RSV", "mem_uop_retired:any_ld + mem_uop_retired:any_st">
  60   ];
  61 }
  62 def : PfmCountersBinding<"silvermont", SLMPfmCounters>;
  63 def : PfmCountersBinding<"goldmont", SLMPfmCounters>;
  64 def : PfmCountersBinding<"goldmont-plus", SLMPfmCounters>;
  65 def : PfmCountersBinding<"tremont", SLMPfmCounters>;
  66
  67 def KnightPfmCounters : ProcPfmCounters {
  68   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
  69   let UopsCounter = PfmCounter<"uops_retired:all">;
  70 }
  71 def : PfmCountersBinding<"knl", KnightPfmCounters>;
  72 def : PfmCountersBinding<"knm", KnightPfmCounters>;
  73
  74 def Core2PfmCounters : ProcPfmCounters {
  75   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
  76   let UopsCounter = PfmCounter<"uops_retired:any">;
  77   let IssueCounters = [
  78     PfmIssueCounter<"SBPort0",  "rs_uops_dispatched_cycles:port_0">,
  79     PfmIssueCounter<"SBPort1",  "rs_uops_dispatched_cycles:port_1">,
  80     PfmIssueCounter<"SBPort23", "rs_uops_dispatched_cycles:port_2 + rs_uops_dispatched_cycles:port_3">,
  81     PfmIssueCounter<"SBPort4",  "rs_uops_dispatched_cycles:port_4">,
  82     PfmIssueCounter<"SBPort5",  "rs_uops_dispatched_cycles:port_5">
  83   ];
  84 }
  85 def : PfmCountersBinding<"core2", Core2PfmCounters>;
  86 def : PfmCountersBinding<"penryn", Core2PfmCounters>;
  87
  88 def NehalemPfmCounters : ProcPfmCounters {
  89   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
  90   let UopsCounter = PfmCounter<"uops_retired:any">;
  91   let IssueCounters = [
  92     PfmIssueCounter<"SBPort0",  "uops_executed:port0">,
  93     PfmIssueCounter<"SBPort1",  "uops_executed:port1">,
  94     PfmIssueCounter<"SBPort23", "uops_executed:port2_core + uops_executed:port3_core">,
  95     PfmIssueCounter<"SBPort4",  "uops_executed:port4_core">,
  96     PfmIssueCounter<"SBPort5",  "uops_executed:port5">
  97   ];
  98 }
  99 def : PfmCountersBinding<"nehalem", NehalemPfmCounters>;
 100 def : PfmCountersBinding<"corei7", NehalemPfmCounters>;
 101 def : PfmCountersBinding<"westmere", NehalemPfmCounters>;
 102
 103 def SandyBridgePfmCounters : ProcPfmCounters {
 104   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
 105   let UopsCounter = UopsIssuedPfmCounter;
 106   let IssueCounters = [
 107     PfmIssueCounter<"SBPort0",  "uops_dispatched_port:port_0">,
 108     PfmIssueCounter<"SBPort1",  "uops_dispatched_port:port_1">,
 109     PfmIssueCounter<"SBPort23", "uops_dispatched_port:port_2 + uops_dispatched_port:port_3">,
 110     PfmIssueCounter<"SBPort4",  "uops_dispatched_port:port_4">,
 111     PfmIssueCounter<"SBPort5",  "uops_dispatched_port:port_5">
 112   ];
 113   let ValidationCounters = DefaultIntelPfmValidationCounters;
 114 }
 115 def : PfmCountersBinding<"sandybridge", SandyBridgePfmCounters>;
 116 def : PfmCountersBinding<"ivybridge", SandyBridgePfmCounters>;
 117
 118 def HaswellPfmCounters : ProcPfmCounters {
 119   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
 120   let UopsCounter = UopsIssuedPfmCounter;
 121   let IssueCounters = [
 122     PfmIssueCounter<"HWPort0", "uops_executed_port:port_0">,
 123     PfmIssueCounter<"HWPort1", "uops_executed_port:port_1">,
 124     PfmIssueCounter<"HWPort2", "uops_executed_port:port_2">,
 125     PfmIssueCounter<"HWPort3", "uops_executed_port:port_3">,
 126     PfmIssueCounter<"HWPort4", "uops_executed_port:port_4">,
 127     PfmIssueCounter<"HWPort5", "uops_executed_port:port_5">,
 128     PfmIssueCounter<"HWPort6", "uops_executed_port:port_6">,
 129     PfmIssueCounter<"HWPort7", "uops_executed_port:port_7">
 130   ];
 131   let ValidationCounters = DefaultIntelPfmValidationCounters;
 132 }
 133 def : PfmCountersBinding<"haswell", HaswellPfmCounters>;
 134
 135 def BroadwellPfmCounters : ProcPfmCounters {
 136   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
 137   let UopsCounter = UopsIssuedPfmCounter;
 138   let IssueCounters = [
 139     PfmIssueCounter<"BWPort0", "uops_executed_port:port_0">,
 140     PfmIssueCounter<"BWPort1", "uops_executed_port:port_1">,
 141     PfmIssueCounter<"BWPort2", "uops_executed_port:port_2">,
 142     PfmIssueCounter<"BWPort3", "uops_executed_port:port_3">,
 143     PfmIssueCounter<"BWPort4", "uops_executed_port:port_4">,
 144     PfmIssueCounter<"BWPort5", "uops_executed_port:port_5">,
 145     PfmIssueCounter<"BWPort6", "uops_executed_port:port_6">,
 146     PfmIssueCounter<"BWPort7", "uops_executed_port:port_7">
 147   ];
 148   let ValidationCounters = DefaultIntelPfmValidationCounters;
 149 }
 150 def : PfmCountersBinding<"broadwell", BroadwellPfmCounters>;
 151
 152 def SkylakeClientPfmCounters : ProcPfmCounters {
 153   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
 154   let UopsCounter = UopsIssuedPfmCounter;
 155   let IssueCounters = [
 156     PfmIssueCounter<"SKLPort0", "uops_dispatched_port:port_0">,
 157     PfmIssueCounter<"SKLPort1", "uops_dispatched_port:port_1">,
 158     PfmIssueCounter<"SKLPort2", "uops_dispatched_port:port_2">,
 159     PfmIssueCounter<"SKLPort3", "uops_dispatched_port:port_3">,
 160     PfmIssueCounter<"SKLPort4", "uops_dispatched_port:port_4">,
 161     PfmIssueCounter<"SKLPort5", "uops_dispatched_port:port_5">,
 162     PfmIssueCounter<"SKLPort6", "uops_dispatched_port:port_6">,
 163     PfmIssueCounter<"SKLPort7", "uops_dispatched_port:port_7">
 164   ];
 165   let ValidationCounters = DefaultIntelPfmValidationCounters;
 166 }
 167 def : PfmCountersBinding<"skylake", SkylakeClientPfmCounters>;
 168
 169 def SkylakeServerPfmCounters : ProcPfmCounters {
 170   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
 171   let UopsCounter = UopsIssuedPfmCounter;
 172   let IssueCounters = [
 173     PfmIssueCounter<"SKXPort0", "uops_dispatched_port:port_0">,
 174     PfmIssueCounter<"SKXPort1", "uops_dispatched_port:port_1">,
 175     PfmIssueCounter<"SKXPort2", "uops_dispatched_port:port_2">,
 176     PfmIssueCounter<"SKXPort3", "uops_dispatched_port:port_3">,
 177     PfmIssueCounter<"SKXPort4", "uops_dispatched_port:port_4">,
 178     PfmIssueCounter<"SKXPort5", "uops_dispatched_port:port_5">,
 179     PfmIssueCounter<"SKXPort6", "uops_dispatched_port:port_6">,
 180     PfmIssueCounter<"SKXPort7", "uops_dispatched_port:port_7">
 181   ];
 182   let ValidationCounters = DefaultIntelPfmValidationCounters;
 183 }
 184 def : PfmCountersBinding<"skylake-avx512", SkylakeServerPfmCounters>;
 185 def : PfmCountersBinding<"cascadelake", SkylakeServerPfmCounters>;
 186 def : PfmCountersBinding<"cannonlake", SkylakeServerPfmCounters>;
 187
 188 def IceLakePfmCounters : ProcPfmCounters {
 189   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
 190   let UopsCounter = UopsIssuedPfmCounter;
 191   let IssueCounters = [
 192     PfmIssueCounter<"ICXPort0",  "uops_dispatched:port_0">,
 193     PfmIssueCounter<"ICXPort1",  "uops_dispatched:port_1">,
 194     PfmIssueCounter<"ICXPort23", "uops_dispatched:port_2_3">,
 195     PfmIssueCounter<"ICXPort49", "uops_dispatched:port_4_9">,
 196     PfmIssueCounter<"ICXPort5",  "uops_dispatched:port_5">,
 197     PfmIssueCounter<"ICXPort6",  "uops_dispatched:port_6">,
 198     PfmIssueCounter<"ICXPort78", "uops_dispatched:port_7_8">
 199   ];
 200   let ValidationCounters = DefaultIntelPfmValidationCounters;
 201 }
 202 def : PfmCountersBinding<"icelake-client", IceLakePfmCounters>;
 203 def : PfmCountersBinding<"icelake-server", IceLakePfmCounters>;
 204 def : PfmCountersBinding<"rocketlake", IceLakePfmCounters>;
 205 def : PfmCountersBinding<"tigerlake", IceLakePfmCounters>;
 206
 207 def AlderLakePfmCounters : ProcPfmCounters {
 208   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
 209   let UopsCounter = UopsIssuedPfmCounter;
 210   let IssueCounters = [
 211     PfmIssueCounter<"ADLPPort00", "uops_dispatched:port_0">,
 212     PfmIssueCounter<"ADLPPort01", "uops_dispatched:port_1">,
 213     PfmIssueCounter<"ADLPPort02_03_10", "uops_dispatched:port_2_3_10">,
 214     PfmIssueCounter<"ADLPPort04_09", "uops_dispatched:port_4_9">,
 215     PfmIssueCounter<"ADLPPort05_11", "uops_dispatched:port_5_11">,
 216     PfmIssueCounter<"ADLPPort06", "uops_dispatched:port_6">,
 217     PfmIssueCounter<"ADLPPort07_08", "uops_dispatched:port_7_8">
 218   ];
 219   let ValidationCounters = DefaultIntelPfmValidationCounters;
 220 }
 221 def : PfmCountersBinding<"alderlake", AlderLakePfmCounters>;
 222
 223 def SapphireRapidsPfmCounters : ProcPfmCounters {
 224   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
 225   let UopsCounter = UopsIssuedPfmCounter;
 226   let IssueCounters = [
 227     PfmIssueCounter<"SPRPort00", "uops_dispatched:port_0">,
 228     PfmIssueCounter<"SPRPort01", "uops_dispatched:port_1">,
 229     PfmIssueCounter<"SPRPort02_03_10", "uops_dispatched:port_2_3_10">,
 230     PfmIssueCounter<"SPRPort04_09", "uops_dispatched:port_4_9">,
 231     PfmIssueCounter<"SPRPort05_11", "uops_dispatched:port_5_11">,
 232     PfmIssueCounter<"SPRPort06", "uops_dispatched:port_6">,
 233     PfmIssueCounter<"SPRPort07_08", "uops_dispatched:port_7_8">,
 234   ];
 235   let ValidationCounters = DefaultIntelPfmValidationCounters;
 236 }
 237 def : PfmCountersBinding<"sapphirerapids", SapphireRapidsPfmCounters>;
 238
 239 // AMD X86 Counters.
 240 defvar DefaultAMDPfmValidationCounters = [
 241   PfmValidationCounter<InstructionRetired, "RETIRED_INSTRUCTIONS">,
 242   PfmValidationCounter<L1DCacheLoadMiss, "L1-DCACHE-LOAD-MISSES">,
 243   PfmValidationCounter<L1DCacheStoreMiss, "L1-DCACHE-STORE-MISSES">,
 244   PfmValidationCounter<L1ICacheLoadMiss, "L1-ICACHE-LOAD-MISSES">,
 245   PfmValidationCounter<DataTLBLoadMiss, "DTLB-LOAD-MISSES">,
 246   PfmValidationCounter<InstructionTLBLoadMiss, "ITLB-LOAD-MISSES">,
 247   PfmValidationCounter<BranchPredictionMiss, "BRANCH-MISSES">
 248 ];
 249
 250 // Set basic counters for AMD cpus that we know libpfm4 supports.
 251 def DefaultAMDPfmCounters : ProcPfmCounters {
 252   let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
 253   let UopsCounter = PfmCounter<"retired_uops">;
 254 }
 255 def : PfmCountersBinding<"athlon", DefaultAMDPfmCounters>;
 256 def : PfmCountersBinding<"athlon-tbird", DefaultAMDPfmCounters>;
 257 def : PfmCountersBinding<"athlon-4", DefaultAMDPfmCounters>;
 258 def : PfmCountersBinding<"athlon-xp", DefaultAMDPfmCounters>;
 259 def : PfmCountersBinding<"athlon-mp", DefaultAMDPfmCounters>;
 260 def : PfmCountersBinding<"k8", DefaultAMDPfmCounters>;
 261 def : PfmCountersBinding<"opteron", DefaultAMDPfmCounters>;
 262 def : PfmCountersBinding<"athlon64", DefaultAMDPfmCounters>;
 263 def : PfmCountersBinding<"athlon-fx", DefaultAMDPfmCounters>;
 264 def : PfmCountersBinding<"k8-sse3", DefaultAMDPfmCounters>;
 265 def : PfmCountersBinding<"opteron-sse3", DefaultAMDPfmCounters>;
 266 def : PfmCountersBinding<"athlon64-sse3", DefaultAMDPfmCounters>;
 267 def : PfmCountersBinding<"amdfam10", DefaultAMDPfmCounters>;
 268 def : PfmCountersBinding<"barcelona", DefaultAMDPfmCounters>;
 269
 270 def BdVer2PfmCounters : ProcPfmCounters {
 271   let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
 272   let UopsCounter = PfmCounter<"retired_uops">;
 273   let IssueCounters = [
 274     PfmIssueCounter<"PdFPU0", "dispatched_fpu_ops:ops_pipe0 + dispatched_fpu_ops:ops_dual_pipe0">,
 275     PfmIssueCounter<"PdFPU1", "dispatched_fpu_ops:ops_pipe1 + dispatched_fpu_ops:ops_dual_pipe1">,
 276     PfmIssueCounter<"PdFPU2", "dispatched_fpu_ops:ops_pipe2 + dispatched_fpu_ops:ops_dual_pipe2">,
 277     PfmIssueCounter<"PdFPU3", "dispatched_fpu_ops:ops_pipe3 + dispatched_fpu_ops:ops_dual_pipe3">
 278   ];
 279 }
 280 def : PfmCountersBinding<"bdver1", BdVer2PfmCounters>;
 281 def : PfmCountersBinding<"bdver2", BdVer2PfmCounters>;
 282
 283 def BdVer3PfmCounters : ProcPfmCounters {
 284   let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
 285   let UopsCounter = PfmCounter<"retired_uops">;
 286   let IssueCounters = [
 287     PfmIssueCounter<"SrFPU0", "dispatched_fpu_ops:ops_pipe0 + dispatched_fpu_ops:ops_dual_pipe0">,
 288     PfmIssueCounter<"SrFPU1", "dispatched_fpu_ops:ops_pipe1 + dispatched_fpu_ops:ops_dual_pipe1">,
 289     PfmIssueCounter<"SrFPU2", "dispatched_fpu_ops:ops_pipe2 + dispatched_fpu_ops:ops_dual_pipe2">
 290   ];
 291 }
 292 def : PfmCountersBinding<"bdver3", BdVer3PfmCounters>;
 293 def : PfmCountersBinding<"bdver4", BdVer3PfmCounters>;
 294
 295 def BtVer1PfmCounters : ProcPfmCounters {
 296   let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
 297   let UopsCounter = PfmCounter<"retired_uops">;
 298   let IssueCounters = [
 299     PfmIssueCounter<"BtFPU0", "dispatched_fpu:pipe0">,
 300     PfmIssueCounter<"BtFPU1", "dispatched_fpu:pipe1">
 301   ];
 302 }
 303 def : PfmCountersBinding<"btver1", BtVer1PfmCounters>;
 304
 305 def BtVer2PfmCounters : ProcPfmCounters {
 306   let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
 307   let UopsCounter = PfmCounter<"retired_uops">;
 308   let IssueCounters = [
 309     PfmIssueCounter<"JFPU0", "dispatched_fpu:pipe0">,
 310     PfmIssueCounter<"JFPU1", "dispatched_fpu:pipe1">
 311   ];
 312 }
 313 def : PfmCountersBinding<"btver2", BtVer2PfmCounters>;
 314
 315 def ZnVer1PfmCounters : ProcPfmCounters {
 316   let CycleCounter = PfmCounter<"cycles_not_in_halt">;
 317   let UopsCounter = PfmCounter<"retired_uops">;
 318   let IssueCounters = [
 319     PfmIssueCounter<"ZnFPU0", "fpu_pipe_assignment:total0">,
 320     PfmIssueCounter<"ZnFPU1", "fpu_pipe_assignment:total1">,
 321     PfmIssueCounter<"ZnFPU2", "fpu_pipe_assignment:total2">,
 322     PfmIssueCounter<"ZnFPU3", "fpu_pipe_assignment:total3">,
 323     PfmIssueCounter<"ZnAGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">,
 324     PfmIssueCounter<"ZnDivider", "div_op_count">
 325   ];
 326   let ValidationCounters = DefaultAMDPfmValidationCounters;
 327 }
 328 def : PfmCountersBinding<"znver1", ZnVer1PfmCounters>;
 329
 330 def ZnVer2PfmCounters : ProcPfmCounters {
 331   let CycleCounter = PfmCounter<"cycles_not_in_halt">;
 332   let UopsCounter = PfmCounter<"retired_uops">;
 333   let IssueCounters = [
 334     PfmIssueCounter<"Zn2AGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">,
 335     PfmIssueCounter<"Zn2Divider", "div_op_count">
 336   ];
 337   let ValidationCounters = DefaultAMDPfmValidationCounters;
 338 }
 339 def : PfmCountersBinding<"znver2", ZnVer2PfmCounters>;
 340
 341 def ZnVer3PfmCounters : ProcPfmCounters {
 342   let CycleCounter = PfmCounter<"cycles_not_in_halt">;
 343   let UopsCounter = PfmCounter<"retired_ops">;
 344   let IssueCounters = [
 345     PfmIssueCounter<"Zn3Int", "ops_type_dispatched_from_decoder:int_disp_retire_mode">,
 346     PfmIssueCounter<"Zn3FPU", "ops_type_dispatched_from_decoder:fp_disp_retire_mode">,
 347     PfmIssueCounter<"Zn3Load", "ls_dispatch:ld_dispatch">,
 348     PfmIssueCounter<"Zn3Store", "ls_dispatch:store_dispatch">,
 349     PfmIssueCounter<"Zn3Divider", "div_op_count">
 350   ];
 351   let ValidationCounters = DefaultAMDPfmValidationCounters;
 352 }
 353 def : PfmCountersBinding<"znver3", ZnVer3PfmCounters>;
 354
 355 def ZnVer4PfmCounters : ProcPfmCounters {
 356   let CycleCounter = PfmCounter<"cycles_not_in_halt">;
 357   let UopsCounter = PfmCounter<"retired_ops">;
 358   let IssueCounters = [
 359     PfmIssueCounter<"Zn4Int", "ops_type_dispatched_from_decoder:int_disp_retire_mode">,
 360     PfmIssueCounter<"Zn4FPU", "ops_type_dispatched_from_decoder:fp_disp_retire_mode">,
 361     PfmIssueCounter<"Zn4Load", "ls_dispatch:ld_dispatch">,
 362     PfmIssueCounter<"Zn4Store", "ls_dispatch:store_dispatch">,
 363     PfmIssueCounter<"Zn4Divider", "div_op_count">,
 364     PfmIssueCounter<"Zn4AGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">
 365   ];
 366   let ValidationCounters = DefaultAMDPfmValidationCounters;
 367 }
 368 def : PfmCountersBinding<"znver4", ZnVer4PfmCounters>;
 369 def : PfmCountersBinding<"znver5", ZnVer4PfmCounters>;