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1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the X86 Register file, defining the registers themselves,
10 // aliases between the registers, and the register classes built out of the
11 // registers.
12 //
13 //===----------------------------------------------------------------------===//
15 class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> {
16 let Namespace = "X86";
17 let HWEncoding = Enc;
18 let SubRegs = subregs;
19 }
21 // Subregister indices.
22 let Namespace = "X86" in {
23 def sub_8bit : SubRegIndex<8>;
24 def sub_8bit_hi : SubRegIndex<8, 8>;
25 def sub_8bit_hi_phony : SubRegIndex<8, 8>;
26 def sub_16bit : SubRegIndex<16>;
27 def sub_16bit_hi : SubRegIndex<16, 16>;
28 def sub_32bit : SubRegIndex<32>;
29 def sub_xmm : SubRegIndex<128>;
30 def sub_ymm : SubRegIndex<256>;
31 def sub_mask_0 : SubRegIndex<-1>;
32 def sub_mask_1 : SubRegIndex<-1, -1>;
33 def sub_t0 : SubRegIndex<8192>;
34 def sub_t1 : SubRegIndex<8192, 8192>;
35 }
37 //===----------------------------------------------------------------------===//
38 // Register definitions...
39 //
41 // In the register alias definitions below, we define which registers alias
42 // which others. We only specify which registers the small registers alias,
43 // because the register file generator is smart enough to figure out that
44 // AL aliases AX if we tell it that AX aliased AL (for example).
46 // Dwarf numbering is different for 32-bit and 64-bit, and there are
47 // variations by target as well. Currently the first entry is for X86-64,
48 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
49 // and debug information on X86-32/Darwin)
51 // 8-bit registers
52 // Low registers
53 def AL : X86Reg<"al", 0>;
54 def DL : X86Reg<"dl", 2>;
55 def CL : X86Reg<"cl", 1>;
56 def BL : X86Reg<"bl", 3>;
58 // High registers. On x86-64, these cannot be used in any instruction
59 // with a REX prefix.
60 def AH : X86Reg<"ah", 4>;
61 def DH : X86Reg<"dh", 6>;
62 def CH : X86Reg<"ch", 5>;
63 def BH : X86Reg<"bh", 7>;
65 // X86-64 only, requires REX.
66 def SIL : X86Reg<"sil", 6>;
67 def DIL : X86Reg<"dil", 7>;
68 def BPL : X86Reg<"bpl", 5>;
69 def SPL : X86Reg<"spl", 4>;
70 def R8B : X86Reg<"r8b", 8>;
71 def R9B : X86Reg<"r9b", 9>;
72 def R10B : X86Reg<"r10b", 10>;
73 def R11B : X86Reg<"r11b", 11>;
74 def R12B : X86Reg<"r12b", 12>;
75 def R13B : X86Reg<"r13b", 13>;
76 def R14B : X86Reg<"r14b", 14>;
77 def R15B : X86Reg<"r15b", 15>;
78 // RAGreedy prefers to select a cheaper register
79 // For x86,
80 // Cost(caller-save reg) < Cost(callee-save reg)
81 // b/c callee-save register needs push/pop in prolog/epilog.
82 // If both registers are callee-saved or caller-saved,
83 // Cost(short-encoding reg) < Cost(long-encoding reg)
84 //
85 // To achieve this, we do the following things:
86 // 1. Set CostPerUse=1 for registers that need prefix
87 // 2. Consider callee-save register is never cheaper than a register w/ cost 1
88 // 3. List caller-save register before callee-save regsiter in RegisterClass
89 // or AllocationOrder
90 //
91 // NOTE:
92 // D133902 stopped assigning register costs for R8-R15, which brought gain
93 // and regression. We don't know if we should assign cost to R16-R31 w/o
94 // performance data.
95 // TODO:
96 // Update the comment/cost after tuning.
97 // APX only, requires REX2 or EVEX.
98 let PositionOrder = 4 in {
99 def R16B : X86Reg<"r16b", 16>;
100 def R17B : X86Reg<"r17b", 17>;
101 def R18B : X86Reg<"r18b", 18>;
102 def R19B : X86Reg<"r19b", 19>;
103 def R20B : X86Reg<"r20b", 20>;
104 def R21B : X86Reg<"r21b", 21>;
105 def R22B : X86Reg<"r22b", 22>;
106 def R23B : X86Reg<"r23b", 23>;
107 def R24B : X86Reg<"r24b", 24>;
108 def R25B : X86Reg<"r25b", 25>;
109 def R26B : X86Reg<"r26b", 26>;
110 def R27B : X86Reg<"r27b", 27>;
111 def R28B : X86Reg<"r28b", 28>;
112 def R29B : X86Reg<"r29b", 29>;
113 def R30B : X86Reg<"r30b", 30>;
114 def R31B : X86Reg<"r31b", 31>;
115 }
117 let isArtificial = 1 in {
118 // High byte of the low 16 bits of the super-register:
119 def SIH : X86Reg<"", -1>;
120 def DIH : X86Reg<"", -1>;
121 def BPH : X86Reg<"", -1>;
122 def SPH : X86Reg<"", -1>;
123 def R8BH : X86Reg<"", -1>;
124 def R9BH : X86Reg<"", -1>;
125 def R10BH : X86Reg<"", -1>;
126 def R11BH : X86Reg<"", -1>;
127 def R12BH : X86Reg<"", -1>;
128 def R13BH : X86Reg<"", -1>;
129 def R14BH : X86Reg<"", -1>;
130 def R15BH : X86Reg<"", -1>;
131 let PositionOrder = 4 in {
132 def R16BH : X86Reg<"", -1>;
133 def R17BH : X86Reg<"", -1>;
134 def R18BH : X86Reg<"", -1>;
135 def R19BH : X86Reg<"", -1>;
136 def R20BH : X86Reg<"", -1>;
137 def R21BH : X86Reg<"", -1>;
138 def R22BH : X86Reg<"", -1>;
139 def R23BH : X86Reg<"", -1>;
140 def R24BH : X86Reg<"", -1>;
141 def R25BH : X86Reg<"", -1>;
142 def R26BH : X86Reg<"", -1>;
143 def R27BH : X86Reg<"", -1>;
144 def R28BH : X86Reg<"", -1>;
145 def R29BH : X86Reg<"", -1>;
146 def R30BH : X86Reg<"", -1>;
147 def R31BH : X86Reg<"", -1>;
148 }
149 // High word of the low 32 bits of the super-register:
150 def HAX : X86Reg<"", -1>;
151 def HDX : X86Reg<"", -1>;
152 def HCX : X86Reg<"", -1>;
153 def HBX : X86Reg<"", -1>;
154 def HSI : X86Reg<"", -1>;
155 def HDI : X86Reg<"", -1>;
156 def HBP : X86Reg<"", -1>;
157 def HSP : X86Reg<"", -1>;
158 def HIP : X86Reg<"", -1>;
159 def R8WH : X86Reg<"", -1>;
160 def R9WH : X86Reg<"", -1>;
161 def R10WH : X86Reg<"", -1>;
162 def R11WH : X86Reg<"", -1>;
163 def R12WH : X86Reg<"", -1>;
164 def R13WH : X86Reg<"", -1>;
165 def R14WH : X86Reg<"", -1>;
166 def R15WH : X86Reg<"", -1>;
167 let PositionOrder = 4 in {
168 def R16WH : X86Reg<"", -1>;
169 def R17WH : X86Reg<"", -1>;
170 def R18WH : X86Reg<"", -1>;
171 def R19WH : X86Reg<"", -1>;
172 def R20WH : X86Reg<"", -1>;
173 def R21WH : X86Reg<"", -1>;
174 def R22WH : X86Reg<"", -1>;
175 def R23WH : X86Reg<"", -1>;
176 def R24WH : X86Reg<"", -1>;
177 def R25WH : X86Reg<"", -1>;
178 def R26WH : X86Reg<"", -1>;
179 def R27WH : X86Reg<"", -1>;
180 def R28WH : X86Reg<"", -1>;
181 def R29WH : X86Reg<"", -1>;
182 def R30WH : X86Reg<"", -1>;
183 def R31WH : X86Reg<"", -1>;
184 }
185 }
187 // 16-bit registers
188 let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {
189 def AX : X86Reg<"ax", 0, [AL,AH]>;
190 def DX : X86Reg<"dx", 2, [DL,DH]>;
191 def CX : X86Reg<"cx", 1, [CL,CH]>;
192 def BX : X86Reg<"bx", 3, [BL,BH]>;
193 }
194 let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in {
195 def SI : X86Reg<"si", 6, [SIL,SIH]>;
196 def DI : X86Reg<"di", 7, [DIL,DIH]>;
197 def BP : X86Reg<"bp", 5, [BPL,BPH]>;
198 def SP : X86Reg<"sp", 4, [SPL,SPH]>;
199 }
200 def IP : X86Reg<"ip", 0>;
202 // X86-64 only, requires REX.
203 let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in {
204 def R8W : X86Reg<"r8w", 8, [R8B,R8BH]>;
205 def R9W : X86Reg<"r9w", 9, [R9B,R9BH]>;
206 def R10W : X86Reg<"r10w", 10, [R10B,R10BH]>;
207 def R11W : X86Reg<"r11w", 11, [R11B,R11BH]>;
208 def R12W : X86Reg<"r12w", 12, [R12B,R12BH]>;
209 def R13W : X86Reg<"r13w", 13, [R13B,R13BH]>;
210 def R14W : X86Reg<"r14w", 14, [R14B,R14BH]>;
211 def R15W : X86Reg<"r15w", 15, [R15B,R15BH]>;
212 }
213 // APX only, requires REX2 or EVEX.
214 let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in {
215 let PositionOrder = 4 in {
216 def R16W : X86Reg<"r16w", 16, [R16B,R16BH]>;
217 def R17W : X86Reg<"r17w", 17, [R17B,R17BH]>;
218 def R18W : X86Reg<"r18w", 18, [R18B,R18BH]>;
219 def R19W : X86Reg<"r19w", 19, [R19B,R19BH]>;
220 def R20W : X86Reg<"r20w", 20, [R20B,R20BH]>;
221 def R21W : X86Reg<"r21w", 21, [R21B,R21BH]>;
222 def R22W : X86Reg<"r22w", 22, [R22B,R22BH]>;
223 def R23W : X86Reg<"r23w", 23, [R23B,R23BH]>;
224 def R24W : X86Reg<"r24w", 24, [R24B,R24BH]>;
225 def R25W : X86Reg<"r25w", 25, [R25B,R25BH]>;
226 def R26W : X86Reg<"r26w", 26, [R26B,R26BH]>;
227 def R27W : X86Reg<"r27w", 27, [R27B,R27BH]>;
228 def R28W : X86Reg<"r28w", 28, [R28B,R28BH]>;
229 def R29W : X86Reg<"r29w", 29, [R29B,R29BH]>;
230 def R30W : X86Reg<"r30w", 30, [R30B,R30BH]>;
231 def R31W : X86Reg<"r31w", 31, [R31B,R31BH]>;
232 }
233 }
235 // 32-bit registers
236 let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in {
237 def EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>;
238 def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>;
239 def ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>;
240 def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>;
241 def ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>;
242 def EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>;
243 def EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>;
244 def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>;
245 def EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>;
246 }
248 // X86-64 only, requires REX
249 let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in {
250 def R8D : X86Reg<"r8d", 8, [R8W,R8WH]>;
251 def R9D : X86Reg<"r9d", 9, [R9W,R9WH]>;
252 def R10D : X86Reg<"r10d", 10, [R10W,R10WH]>;
253 def R11D : X86Reg<"r11d", 11, [R11W,R11WH]>;
254 def R12D : X86Reg<"r12d", 12, [R12W,R12WH]>;
255 def R13D : X86Reg<"r13d", 13, [R13W,R13WH]>;
256 def R14D : X86Reg<"r14d", 14, [R14W,R14WH]>;
257 def R15D : X86Reg<"r15d", 15, [R15W,R15WH]>;
258 }
260 // APX only, requires REX2 or EVEX.
261 let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in {
262 let PositionOrder = 4 in {
263 def R16D : X86Reg<"r16d", 16, [R16W,R16WH]>;
264 def R17D : X86Reg<"r17d", 17, [R17W,R17WH]>;
265 def R18D : X86Reg<"r18d", 18, [R18W,R18WH]>;
266 def R19D : X86Reg<"r19d", 19, [R19W,R19WH]>;
267 def R20D : X86Reg<"r20d", 20, [R20W,R20WH]>;
268 def R21D : X86Reg<"r21d", 21, [R21W,R21WH]>;
269 def R22D : X86Reg<"r22d", 22, [R22W,R22WH]>;
270 def R23D : X86Reg<"r23d", 23, [R23W,R23WH]>;
271 def R24D : X86Reg<"r24d", 24, [R24W,R24WH]>;
272 def R25D : X86Reg<"r25d", 25, [R25W,R25WH]>;
273 def R26D : X86Reg<"r26d", 26, [R26W,R26WH]>;
274 def R27D : X86Reg<"r27d", 27, [R27W,R27WH]>;
275 def R28D : X86Reg<"r28d", 28, [R28W,R28WH]>;
276 def R29D : X86Reg<"r29d", 29, [R29W,R29WH]>;
277 def R30D : X86Reg<"r30d", 30, [R30W,R30WH]>;
278 def R31D : X86Reg<"r31d", 31, [R31W,R31WH]>;
279 }
280 }
281 // 64-bit registers, X86-64 only
282 let SubRegIndices = [sub_32bit] in {
283 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
284 def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>;
285 def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>;
286 def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>;
287 def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>;
288 def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>;
289 def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>;
290 def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;
292 // These also require REX.
293 def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>;
294 def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>;
295 def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>;
296 def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>;
297 def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>;
298 def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>;
299 def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>;
300 def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>;
301 def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;
302 // APX only, requires REX2 or EVEX.
303 let PositionOrder = 4 in {
304 def R16 : X86Reg<"r16", 16, [R16D]>, DwarfRegNum<[130, -2, -2]>;
305 def R17 : X86Reg<"r17", 17, [R17D]>, DwarfRegNum<[131, -2, -2]>;
306 def R18 : X86Reg<"r18", 18, [R18D]>, DwarfRegNum<[132, -2, -2]>;
307 def R19 : X86Reg<"r19", 19, [R19D]>, DwarfRegNum<[133, -2, -2]>;
308 def R20 : X86Reg<"r20", 20, [R20D]>, DwarfRegNum<[134, -2, -2]>;
309 def R21 : X86Reg<"r21", 21, [R21D]>, DwarfRegNum<[135, -2, -2]>;
310 def R22 : X86Reg<"r22", 22, [R22D]>, DwarfRegNum<[136, -2, -2]>;
311 def R23 : X86Reg<"r23", 23, [R23D]>, DwarfRegNum<[137, -2, -2]>;
312 def R24 : X86Reg<"r24", 24, [R24D]>, DwarfRegNum<[138, -2, -2]>;
313 def R25 : X86Reg<"r25", 25, [R25D]>, DwarfRegNum<[139, -2, -2]>;
314 def R26 : X86Reg<"r26", 26, [R26D]>, DwarfRegNum<[140, -2, -2]>;
315 def R27 : X86Reg<"r27", 27, [R27D]>, DwarfRegNum<[141, -2, -2]>;
316 def R28 : X86Reg<"r28", 28, [R28D]>, DwarfRegNum<[142, -2, -2]>;
317 def R29 : X86Reg<"r29", 29, [R29D]>, DwarfRegNum<[143, -2, -2]>;
318 def R30 : X86Reg<"r30", 30, [R30D]>, DwarfRegNum<[144, -2, -2]>;
319 def R31 : X86Reg<"r31", 31, [R31D]>, DwarfRegNum<[145, -2, -2]>;
320 }
321 }
323 // MMX Registers. These are actually aliased to ST0 .. ST7
324 def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;
325 def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>;
326 def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>;
327 def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>;
328 def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>;
329 def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>;
330 def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>;
331 def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>;
333 // Pseudo Floating Point registers
334 def FP0 : X86Reg<"fp0", 0>;
335 def FP1 : X86Reg<"fp1", 0>;
336 def FP2 : X86Reg<"fp2", 0>;
337 def FP3 : X86Reg<"fp3", 0>;
338 def FP4 : X86Reg<"fp4", 0>;
339 def FP5 : X86Reg<"fp5", 0>;
340 def FP6 : X86Reg<"fp6", 0>;
341 def FP7 : X86Reg<"fp7", 0>;
343 // XMM Registers, used by the various SSE instruction set extensions.
344 def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>;
345 def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>;
346 def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>;
347 def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>;
348 def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>;
349 def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>;
350 def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>;
351 def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>;
353 // X86-64 only
354 def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>;
355 def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>;
356 def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>;
357 def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>;
358 def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>;
359 def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>;
360 def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>;
361 def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>;
363 let PositionOrder = 2 in {
364 // XMM16-31 registers, used by AVX-512 instructions.
365 def XMM16: X86Reg<"xmm16", 16>, DwarfRegNum<[67, -2, -2]>;
366 def XMM17: X86Reg<"xmm17", 17>, DwarfRegNum<[68, -2, -2]>;
367 def XMM18: X86Reg<"xmm18", 18>, DwarfRegNum<[69, -2, -2]>;
368 def XMM19: X86Reg<"xmm19", 19>, DwarfRegNum<[70, -2, -2]>;
369 def XMM20: X86Reg<"xmm20", 20>, DwarfRegNum<[71, -2, -2]>;
370 def XMM21: X86Reg<"xmm21", 21>, DwarfRegNum<[72, -2, -2]>;
371 def XMM22: X86Reg<"xmm22", 22>, DwarfRegNum<[73, -2, -2]>;
372 def XMM23: X86Reg<"xmm23", 23>, DwarfRegNum<[74, -2, -2]>;
373 def XMM24: X86Reg<"xmm24", 24>, DwarfRegNum<[75, -2, -2]>;
374 def XMM25: X86Reg<"xmm25", 25>, DwarfRegNum<[76, -2, -2]>;
375 def XMM26: X86Reg<"xmm26", 26>, DwarfRegNum<[77, -2, -2]>;
376 def XMM27: X86Reg<"xmm27", 27>, DwarfRegNum<[78, -2, -2]>;
377 def XMM28: X86Reg<"xmm28", 28>, DwarfRegNum<[79, -2, -2]>;
378 def XMM29: X86Reg<"xmm29", 29>, DwarfRegNum<[80, -2, -2]>;
379 def XMM30: X86Reg<"xmm30", 30>, DwarfRegNum<[81, -2, -2]>;
380 def XMM31: X86Reg<"xmm31", 31>, DwarfRegNum<[82, -2, -2]>;
381 }
383 // YMM0-15 registers, used by AVX instructions and
384 // YMM16-31 registers, used by AVX-512 instructions.
385 let SubRegIndices = [sub_xmm], PositionOrder = 1 in {
386 foreach Index = 0-15 in {
387 def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>,
388 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
389 }
390 }
391 let SubRegIndices = [sub_xmm], PositionOrder = 2 in {
392 foreach Index = 16-31 in {
393 def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>,
394 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
395 }
396 }
399 // ZMM Registers, used by AVX-512 instructions.
400 let SubRegIndices = [sub_ymm], PositionOrder = 2 in {
401 foreach Index = 0-31 in {
402 def ZMM#Index : X86Reg<"zmm"#Index, Index, [!cast<X86Reg>("YMM"#Index)]>,
403 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
404 }
405 }
407 let PositionOrder = 2 in {
408 // Mask Registers, used by AVX-512 instructions.
409 def K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, 93, 93]>;
410 def K1 : X86Reg<"k1", 1>, DwarfRegNum<[119, 94, 94]>;
411 def K2 : X86Reg<"k2", 2>, DwarfRegNum<[120, 95, 95]>;
412 def K3 : X86Reg<"k3", 3>, DwarfRegNum<[121, 96, 96]>;
413 def K4 : X86Reg<"k4", 4>, DwarfRegNum<[122, 97, 97]>;
414 def K5 : X86Reg<"k5", 5>, DwarfRegNum<[123, 98, 98]>;
415 def K6 : X86Reg<"k6", 6>, DwarfRegNum<[124, 99, 99]>;
416 def K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, 100, 100]>;
417 // Mask register pairs
418 def KPAIRS : RegisterTuples<[sub_mask_0, sub_mask_1],
419 [(add K0, K2, K4, K6), (add K1, K3, K5, K7)]>;
420 }
422 // TMM registers, used by AMX instructions.
423 let PositionOrder = 3 in {
424 // Tile config registers.
425 def TMMCFG: X86Reg<"tmmcfg", 0>;
426 // Tile "registers".
427 def TMM0: X86Reg<"tmm0", 0>;
428 def TMM1: X86Reg<"tmm1", 1>;
429 def TMM2: X86Reg<"tmm2", 2>;
430 def TMM3: X86Reg<"tmm3", 3>;
431 def TMM4: X86Reg<"tmm4", 4>;
432 def TMM5: X86Reg<"tmm5", 5>;
433 def TMM6: X86Reg<"tmm6", 6>;
434 def TMM7: X86Reg<"tmm7", 7>;
435 // TMM register pairs
436 def TPAIRS : RegisterTuples<[sub_t0, sub_t1],
437 [(add TMM0, TMM2, TMM4, TMM6),
438 (add TMM1, TMM3, TMM5, TMM7)]>;
439 }
441 // Floating point stack registers. These don't map one-to-one to the FP
442 // pseudo registers, but we still mark them as aliasing FP registers. That
443 // way both kinds can be live without exceeding the stack depth. ST registers
444 // are only live around inline assembly.
445 def ST0 : X86Reg<"st", 0>, DwarfRegNum<[33, 12, 11]>;
446 def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>;
447 def ST2 : X86Reg<"st(2)", 2>, DwarfRegNum<[35, 14, 13]>;
448 def ST3 : X86Reg<"st(3)", 3>, DwarfRegNum<[36, 15, 14]>;
449 def ST4 : X86Reg<"st(4)", 4>, DwarfRegNum<[37, 16, 15]>;
450 def ST5 : X86Reg<"st(5)", 5>, DwarfRegNum<[38, 17, 16]>;
451 def ST6 : X86Reg<"st(6)", 6>, DwarfRegNum<[39, 18, 17]>;
452 def ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]>;
454 // Floating-point status word
455 def FPSW : X86Reg<"fpsr", 0>;
457 // Floating-point control word
458 def FPCW : X86Reg<"fpcr", 0>;
460 // SIMD Floating-point control register.
461 // Note: We only model the "Uses" of the control bits: current rounding modes,
462 // DAZ, FTZ and exception masks. We don't model the "Defs" of flag bits.
463 def MXCSR : X86Reg<"mxcsr", 0>;
465 // Status flags register.
466 //
467 // Note that some flags that are commonly thought of as part of the status
468 // flags register are modeled separately. Typically this is due to instructions
469 // reading and updating those flags independently of all the others. We don't
470 // want to create false dependencies between these instructions and so we use
471 // a separate register to model them.
472 def EFLAGS : X86Reg<"flags", 0>, DwarfRegNum<[49, 9, 9]>;
473 def _EFLAGS : X86Reg<"eflags", 0>, DwarfRegAlias<EFLAGS>;
474 def RFLAGS : X86Reg<"rflags", 0>, DwarfRegNum<[49, -2, -2]>;
476 // The direction flag.
477 def DF : X86Reg<"dirflag", 0>;
480 // Segment registers
481 def CS : X86Reg<"cs", 1>, DwarfRegNum<[51, -2, 41]>;
482 def DS : X86Reg<"ds", 3>, DwarfRegNum<[53, -2, 43]>;
483 def SS : X86Reg<"ss", 2>, DwarfRegNum<[52, -2, 42]>;
484 def ES : X86Reg<"es", 0>, DwarfRegNum<[50, -2, 40]>;
485 def FS : X86Reg<"fs", 4>, DwarfRegNum<[54, -2, 44]>;
486 def GS : X86Reg<"gs", 5>, DwarfRegNum<[55, -2, 45]>;
488 def FS_BASE : X86Reg<"fs.base", 0>, DwarfRegNum<[58, -2, -2]>;
489 def GS_BASE : X86Reg<"gs.base", 0>, DwarfRegNum<[59, -2, -2]>;
491 // Debug registers
492 def DR0 : X86Reg<"dr0", 0>;
493 def DR1 : X86Reg<"dr1", 1>;
494 def DR2 : X86Reg<"dr2", 2>;
495 def DR3 : X86Reg<"dr3", 3>;
496 def DR4 : X86Reg<"dr4", 4>;
497 def DR5 : X86Reg<"dr5", 5>;
498 def DR6 : X86Reg<"dr6", 6>;
499 def DR7 : X86Reg<"dr7", 7>;
500 def DR8 : X86Reg<"dr8", 8>;
501 def DR9 : X86Reg<"dr9", 9>;
502 def DR10 : X86Reg<"dr10", 10>;
503 def DR11 : X86Reg<"dr11", 11>;
504 def DR12 : X86Reg<"dr12", 12>;
505 def DR13 : X86Reg<"dr13", 13>;
506 def DR14 : X86Reg<"dr14", 14>;
507 def DR15 : X86Reg<"dr15", 15>;
509 // Control registers
510 def CR0 : X86Reg<"cr0", 0>;
511 def CR1 : X86Reg<"cr1", 1>;
512 def CR2 : X86Reg<"cr2", 2>;
513 def CR3 : X86Reg<"cr3", 3>;
514 def CR4 : X86Reg<"cr4", 4>;
515 def CR5 : X86Reg<"cr5", 5>;
516 def CR6 : X86Reg<"cr6", 6>;
517 def CR7 : X86Reg<"cr7", 7>;
518 def CR8 : X86Reg<"cr8", 8>;
519 def CR9 : X86Reg<"cr9", 9>;
520 def CR10 : X86Reg<"cr10", 10>;
521 def CR11 : X86Reg<"cr11", 11>;
522 def CR12 : X86Reg<"cr12", 12>;
523 def CR13 : X86Reg<"cr13", 13>;
524 def CR14 : X86Reg<"cr14", 14>;
525 def CR15 : X86Reg<"cr15", 15>;
527 // Pseudo index registers
528 def EIZ : X86Reg<"eiz", 4>;
529 def RIZ : X86Reg<"riz", 4>;
531 // CET registers - Shadow Stack Pointer
532 def SSP : X86Reg<"ssp", 0>;
534 //===----------------------------------------------------------------------===//
535 // Register Class Definitions... now that we have all of the pieces, define the
536 // top-level register classes. The order specified in the register list is
537 // implicitly defined to be the register allocation order.
538 //
540 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
541 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
542 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
543 // R8B, ... R15B.
544 // Allocate R12, R13, R20, R21, R28 and R29 last, as these require an extra byte
545 // when encoded in x86_64 instructions.
546 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
547 // 64-bit mode. The main complication is that they cannot be encoded in an
548 // instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
549 // require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
550 // cannot be encoded.
551 def GR8 : RegisterClass<"X86", [i8], 8,
552 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
553 R8B, R9B, R10B, R11B, R16B, R17B, R18B, R19B, R22B,
554 R23B, R24B, R25B, R26B, R27B, R30B, R31B, R14B,
555 R15B, R12B, R13B, R20B, R21B, R28B, R29B)> {
556 let AltOrders = [(sub GR8, AH, BH, CH, DH)];
557 let AltOrderSelect = [{
558 return MF.getSubtarget<X86Subtarget>().is64Bit();
559 }];
560 }
562 let isAllocatable = 0 in
563 def GRH8 : RegisterClass<"X86", [i8], 8,
564 (add SIH, DIH, BPH, SPH, R8BH, R9BH, R10BH, R11BH,
565 R12BH, R13BH, R14BH, R15BH, R16BH, R17BH, R18BH,
566 R19BH, R20BH, R21BH, R22BH, R23BH, R24BH, R25BH,
567 R26BH, R27BH, R28BH, R29BH, R30BH, R31BH)>;
568 def GR16 : RegisterClass<"X86", [i16], 16,
569 (add AX, CX, DX, SI, DI, BX, BP, SP, R8W, R9W, R10W,
570 R11W, R16W, R17W, R18W, R19W, R22W, R23W, R24W,
571 R25W, R26W, R27W, R30W, R31W, R14W, R15W, R12W,
572 R13W, R20W, R21W, R28W, R29W)>;
574 let isAllocatable = 0 in
575 def GRH16 : RegisterClass<"X86", [i16], 16,
576 (add HAX, HCX, HDX, HSI, HDI, HBX, HBP, HSP, HIP, R8WH,
577 R9WH, R10WH, R11WH, R12WH, R13WH, R14WH, R15WH, R16WH,
578 R17WH, R18WH, R19WH, R20WH, R21WH, R22WH, R23WH, R24WH,
579 R25WH, R26WH, R27WH, R28WH, R29WH, R30WH, R31WH)>;
580 def GR32 : RegisterClass<"X86", [i32], 32,
581 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, R8D, R9D,
582 R10D, R11D, R16D, R17D, R18D, R19D, R22D, R23D,
583 R24D, R25D, R26D, R27D, R30D, R31D, R14D, R15D,
584 R12D, R13D, R20D, R21D, R28D, R29D)>;
586 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
587 // RIP isn't really a register and it can't be used anywhere except in an
588 // address, but it doesn't cause trouble.
589 // FIXME: it *does* cause trouble - CheckBaseRegAndIndexReg() has extra
590 // tests because of the inclusion of RIP in this register class.
591 def GR64 : RegisterClass<"X86", [i64], 64,
592 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, R16, R17,
593 R18, R19, R22, R23, R24, R25, R26, R27, R30, R31, RBX,
594 R14, R15, R12, R13, R20, R21, R28, R29, RBP, RSP, RIP)>;
596 // GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when
597 // emitting code for intrinsics, which use implict input registers.
598 def GR64PLTSafe : RegisterClass<"X86", [i64], 64,
599 (add RAX, RCX, RDX, RSI, RDI, R8, R9,
600 RBX, R14, R15, R12, R13, RBP)>;
602 // It includes the GPR that are used as scratch register for Linux64 calling
603 // convention.
604 def GR64_ArgRef: RegisterClass<"X86", [i64], 64, (add R10, R11)> {
605 let GeneratePressureSet = 0;
606 }
608 // It includes the GPR that are used as scratch register for Linux32 calling
609 // convention.
610 def GR32_ArgRef: RegisterClass<"X86", [i32], 32, (add ECX, EDX)> {
611 let GeneratePressureSet = 0;
612 }
614 // Segment registers for use by MOV instructions (and others) that have a
615 // segment register as one operand. Always contain a 16-bit segment
616 // descriptor.
617 def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>;
619 // Debug registers.
620 def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 15)>;
622 // Control registers.
623 def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>;
625 // GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
626 // GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"
627 // registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
628 // that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
629 // and GR64_ABCD are classes for registers that support 8-bit h-register
630 // operations.
631 def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>;
632 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;
633 def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>;
634 def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>;
635 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
636 def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, ESP)>;
637 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
638 R8, R9, R11, RIP, RSP)>;
639 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
640 R8, R9, R10, R11,
641 RIP, RSP)>;
643 // GR8_NOREX - GR8 registers which do not require a REX prefix.
644 def GR8_NOREX : RegisterClass<"X86", [i8], 8,
645 (add AL, CL, DL, AH, CH, DH, BL, BH)> {
646 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
647 let AltOrderSelect = [{
648 return MF.getSubtarget<X86Subtarget>().is64Bit();
649 }];
650 }
651 // GR16_NOREX - GR16 registers which do not require a REX prefix.
652 def GR16_NOREX : RegisterClass<"X86", [i16], 16,
653 (add AX, CX, DX, SI, DI, BX, BP, SP)>;
654 // GR32_NOREX - GR32 registers which do not require a REX prefix.
655 def GR32_NOREX : RegisterClass<"X86", [i32], 32,
656 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>;
657 // GR64_NOREX - GR64 registers which do not require a REX prefix.
658 def GR64_NOREX : RegisterClass<"X86", [i64], 64,
659 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
660 // GeneratePressureSet = 0 here is a temporary workaround for lots of
661 // LIT fail. Whether enabling in the future still needs discussion.
662 let GeneratePressureSet = 0 in {
663 // GR8_NOREX2 - GR8 registers which do not require a REX2 prefix.
664 def GR8_NOREX2 : RegisterClass<"X86", [i8], 8,
665 (sub GR8, (sequence "R%uB", 16, 31))> {
666 let AltOrders = [(sub GR8_NOREX2, AH, BH, CH, DH)];
667 let AltOrderSelect = [{
668 return MF.getSubtarget<X86Subtarget>().is64Bit();
669 }];
670 }
671 // GR16_NOREX2 - GR16 registers which do not require a REX2 prefix.
672 def GR16_NOREX2 : RegisterClass<"X86", [i16], 16,
673 (sub GR16, (sequence "R%uW", 16, 31))>;
674 // GR32_NOREX2 - GR32 registers which do not require a REX2 prefix.
675 def GR32_NOREX2 : RegisterClass<"X86", [i32], 32,
676 (sub GR32, (sequence "R%uD", 16, 31))>;
677 // GR64_NOREX2 - GR64 registers which do not require a REX2 prefix.
678 def GR64_NOREX2 : RegisterClass<"X86", [i64], 64,
679 (sub GR64, (sequence "R%u", 16, 31))>;
680 }
682 // GR32_NOSP - GR32 registers except ESP.
683 def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>;
685 // GR64_NOSP - GR64 registers except RSP (and RIP).
686 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
688 // GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except
689 // ESP.
690 def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32,
691 (and GR32_NOREX, GR32_NOSP)>;
693 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
694 def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
695 (and GR64_NOREX, GR64_NOSP)>;
696 let GeneratePressureSet = 0 in {
697 // GR32_NOREX2_NOSP - GR32_NOREX2 registers except ESP.
698 def GR32_NOREX2_NOSP : RegisterClass<"X86", [i32], 32,
699 (sub GR32_NOREX2, ESP)>;
701 // GR64_NOREX2_NOSP - GR64_NOREX2 registers except RSP, RIP.
702 def GR64_NOREX2_NOSP : RegisterClass<"X86", [i64], 64,
703 (sub GR64_NOREX2, RSP, RIP)>;
704 }
706 // Register classes used for ABIs that use 32-bit address accesses,
707 // while using the whole x86_64 ISA.
709 // In such cases, it is fine to use RIP as we are sure the 32 high
710 // bits are not set. We do not need variants for NOSP as RIP is not
711 // allowed there.
712 // RIP is not spilled anywhere for now, so stick to 32-bit alignment
713 // to save on memory space.
714 // FIXME: We could allow all 64bit registers, but we would need
715 // something to check that the 32 high bits are not set,
716 // which we do not have right now.
717 def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>;
719 // When RBP is used as a base pointer in a 32-bit addresses environment,
720 // this is also safe to use the full register to access addresses.
721 // Since RBP will never be spilled, stick to a 32 alignment to save
722 // on memory consumption.
723 def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,
724 (add LOW32_ADDR_ACCESS, RBP)>;
726 // A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.
727 def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
728 def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;
730 // Classes to support the 64-bit assembler constraint tied to a fixed
731 // register in 32-bit mode. The second register is always the next in
732 // the list. Wrap around causes an error.
733 def GR32_DC : RegisterClass<"X86", [i32], 32, (add EDX, ECX)>;
734 def GR32_CB : RegisterClass<"X86", [i32], 32, (add ECX, EBX)>;
735 def GR32_BSI : RegisterClass<"X86", [i32], 32, (add EBX, ESI)>;
736 def GR32_SIDI : RegisterClass<"X86", [i32], 32, (add ESI, EDI)>;
737 def GR32_DIBP : RegisterClass<"X86", [i32], 32, (add EDI, EBP)>;
738 def GR32_BPSP : RegisterClass<"X86", [i32], 32, (add EBP, ESP)>;
740 // Scalar SSE2 floating point registers.
741 def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>;
743 def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>;
745 def FR16 : RegisterClass<"X86", [f16], 16, (add FR32)> {let Size = 32;}
748 // FIXME: This sets up the floating point register files as though they are f64
749 // values, though they really are f80 values. This will cause us to spill
750 // values as 64-bit quantities instead of 80-bit quantities, which is much much
751 // faster on common hardware. In reality, this should be controlled by a
752 // command line option or something.
755 def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>;
756 def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>;
757 def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>;
759 // st(7) may be is not allocatable.
760 def RFP80_7 : RegisterClass<"X86",[f80], 32, (add FP7)> {
761 let isAllocatable = 0;
762 }
764 // Floating point stack registers (these are not allocatable by the
765 // register allocator - the floating point stackifier is responsible
766 // for transforming FPn allocations to STn registers)
767 def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> {
768 let isAllocatable = 0;
769 }
771 // Helper to allow %st to print as %st(0) when its encoded in the instruction.
772 def RSTi : RegisterOperand<RST, "printSTiRegOperand">;
774 // Generic vector registers: VR64 and VR128.
775 // Ensure that float types are declared first - only float is legal on SSE1.
776 def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>;
777 def VR128 : RegisterClass<"X86", [v4f32, v2f64, v8f16, v8bf16, v16i8, v8i16, v4i32, v2i64, f128],
778 128, (add FR32)>;
779 def VR256 : RegisterClass<"X86", [v8f32, v4f64, v16f16, v16bf16, v32i8, v16i16, v8i32, v4i64],
780 256, (sequence "YMM%u", 0, 15)>;
782 // Status flags registers.
783 def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> {
784 let CopyCost = -1; // Don't allow copying of status registers.
785 let isAllocatable = 0;
786 }
787 def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> {
788 let CopyCost = -1; // Don't allow copying of status registers.
789 let isAllocatable = 0;
790 }
791 def DFCCR : RegisterClass<"X86", [i32], 32, (add DF)> {
792 let CopyCost = -1; // Don't allow copying of status registers.
793 let isAllocatable = 0;
794 }
796 // AVX-512 vector/mask registers.
797 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v32f16, v32bf16, v64i8, v32i16, v16i32, v8i64],
798 512, (sequence "ZMM%u", 0, 31)>;
800 // Represents the lower 16 registers that have VEX/legacy encodable subregs.
801 def VR512_0_15 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
802 512, (sequence "ZMM%u", 0, 15)>;
804 // Scalar AVX-512 floating point registers.
805 def FR32X : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 31)>;
807 def FR64X : RegisterClass<"X86", [f64], 64, (add FR32X)>;
809 def FR16X : RegisterClass<"X86", [f16], 16, (add FR32X)> {let Size = 32;}
811 // Extended VR128 and VR256 for AVX-512 instructions
812 def VR128X : RegisterClass<"X86", [v4f32, v2f64, v8f16, v8bf16, v16i8, v8i16, v4i32, v2i64, f128],
813 128, (add FR32X)>;
814 def VR256X : RegisterClass<"X86", [v8f32, v4f64, v16f16, v16bf16, v32i8, v16i16, v8i32, v4i64],
815 256, (sequence "YMM%u", 0, 31)>;
817 // Mask registers
818 def VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;}
819 def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;}
820 def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;}
821 def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;}
822 def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;}
823 def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}
824 def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}
826 def VK1PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
827 def VK2PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
828 def VK4PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
829 def VK8PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
830 def VK16PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
832 def VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;}
833 def VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;}
834 def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;}
835 def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;}
836 def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;}
837 def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}
838 def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}
840 // Tiles
841 let CopyCost = -1 in // Don't allow copying of tile registers
842 def TILE : RegisterClass<"X86", [x86amx], 8192,
843 (sequence "TMM%u", 0, 7)> {let Size = 8192;}
844 // Need check alignment 3rd operand size=1024*2*8
845 let isAllocatable = 1 in
846 def TILEPAIR : RegisterClass<"X86", [untyped], 512, (add TPAIRS)> {let Size = 16384;}
848 //===----------------------------------------------------------------------===//
849 // Register categories.
850 //
852 // The TILE and VK*PAIR registers may not be "fixed", but we don't want them
853 // anyway.
854 def FixedRegisters : RegisterCategory<[DEBUG_REG, CONTROL_REG, CCR, FPCCR,
855 DFCCR, TILE, VK1PAIR, VK2PAIR, VK4PAIR,
856 VK8PAIR, VK16PAIR]>;
857 def GeneralPurposeRegisters : RegisterCategory<[GR64, GR32, GR16, GR8]>;