| blob | 4f0d3669a311d46ca6b093f331a3ebf1f61bb273 |
1 //=- X86SchedSapphireRapids.td - X86 SapphireRapids Scheduling *- tablegen -*=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the machine model for SapphireRapids to support instruction
10 // scheduling and other instruction cost heuristics.
11 //
12 //===----------------------------------------------------------------------===//
14 def SapphireRapidsModel : SchedMachineModel {
15 // SapphireRapids can allocate 6 uops per cycle.
16 let IssueWidth = 6; // Based on allocator width.
17 let MicroOpBufferSize = 512; // Based on the reorder buffer.
18 let LoadLatency = 5;
19 let MispredictPenalty = 14;
21 // Latency for microcoded instructions or instructions without latency info.
22 int MaxLatency = 100;
24 // Based on the LSD (loop-stream detector) queue size (ST).
25 let LoopMicroOpBufferSize = 72;
27 // This flag is set to allow the scheduler to assign a default model to
28 // unrecognized opcodes.
29 let CompleteModel = 0;
30 }
32 let SchedModel = SapphireRapidsModel in {
34 // SapphireRapids can issue micro-ops to 12 different ports in one cycle.
35 def SPRPort00 : ProcResource<1>;
36 def SPRPort01 : ProcResource<1>;
37 def SPRPort02 : ProcResource<1>;
38 def SPRPort03 : ProcResource<1>;
39 def SPRPort04 : ProcResource<1>;
40 def SPRPort05 : ProcResource<1>;
41 def SPRPort06 : ProcResource<1>;
42 def SPRPort07 : ProcResource<1>;
43 def SPRPort08 : ProcResource<1>;
44 def SPRPort09 : ProcResource<1>;
45 def SPRPort10 : ProcResource<1>;
46 def SPRPort11 : ProcResource<1>;
48 // Workaround to represent invalid ports. WriteRes shouldn't use this resource.
49 def SPRPortInvalid :ProcResource<1>;
51 // Many micro-ops are capable of issuing on multiple ports.
52 def SPRPort00_01 : ProcResGroup<[SPRPort00, SPRPort01]>;
53 def SPRPort00_01_05 : ProcResGroup<[SPRPort00, SPRPort01, SPRPort05]>;
54 def SPRPort00_01_05_06 : ProcResGroup<[SPRPort00, SPRPort01, SPRPort05, SPRPort06]>;
55 def SPRPort00_05 : ProcResGroup<[SPRPort00, SPRPort05]>;
56 def SPRPort00_05_06 : ProcResGroup<[SPRPort00, SPRPort05, SPRPort06]>;
57 def SPRPort00_06 : ProcResGroup<[SPRPort00, SPRPort06]>;
58 def SPRPort01_05 : ProcResGroup<[SPRPort01, SPRPort05]>;
59 def SPRPort01_05_11 : ProcResGroup<[SPRPort01, SPRPort05, SPRPort11]>;
60 def SPRPort02_03 : ProcResGroup<[SPRPort02, SPRPort03]>;
61 def SPRPort02_03_10 : ProcResGroup<[SPRPort02, SPRPort03, SPRPort10]>;
62 def SPRPort05_11 : ProcResGroup<[SPRPort05, SPRPort11]>;
63 def SPRPort07_08 : ProcResGroup<[SPRPort07, SPRPort08]>;
65 // EU has 112 reservation stations.
66 def SPRPort00_01_05_06_11 : ProcResGroup<[SPRPort00, SPRPort01, SPRPort05,
67 SPRPort06, SPRPort11]> {
68 let BufferSize = 112;
69 }
71 // STD has 48 reservation stations.
72 def SPRPort04_09 : ProcResGroup<[SPRPort04, SPRPort09]> {
73 let BufferSize = 48;
74 }
76 // MEM has 72 reservation stations.
77 def SPRPort02_03_07_08_10 : ProcResGroup<[SPRPort02, SPRPort03, SPRPort07,
78 SPRPort08, SPRPort10]> {
79 let BufferSize = 72;
80 }
82 def SPRPortAny : ProcResGroup<[SPRPort00, SPRPort01, SPRPort02, SPRPort03,
83 SPRPort04, SPRPort05, SPRPort06, SPRPort07,
84 SPRPort08, SPRPort09, SPRPort10, SPRPort11]>;
86 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available
87 // until 5 cycles after the memory operand.
88 def : ReadAdvance<ReadAfterLd, 5>;
90 // Vector loads are 6 cycles, so ReadAfterVec*Ld registers needn't be available
91 // until 6 cycles after the memory operand.
92 def : ReadAdvance<ReadAfterVecLd, 6>;
93 def : ReadAdvance<ReadAfterVecXLd, 6>;
94 def : ReadAdvance<ReadAfterVecYLd, 6>;
96 def : ReadAdvance<ReadInt2Fpu, 0>;
98 // Many SchedWrites are defined in pairs with and without a folded load.
99 // Instructions with folded loads are usually micro-fused, so they only appear
100 // as two micro-ops when queued in the reservation station.
101 // This multiclass defines the resource usage for variants with and without
102 // folded loads.
103 multiclass SPRWriteResPair<X86FoldableSchedWrite SchedRW,
104 list<ProcResourceKind> ExePorts,
105 int Lat, list<int> Res = [1], int UOps = 1,
106 int LoadLat = 5, int LoadUOps = 1> {
107 // Register variant is using a single cycle on ExePort.
108 def : WriteRes<SchedRW, ExePorts> {
109 let Latency = Lat;
110 let ReleaseAtCycles = Res;
111 let NumMicroOps = UOps;
112 }
114 // Memory variant also uses a cycle on port 2/3/11 and adds LoadLat cycles to
115 // the latency (default = 5).
116 def : WriteRes<SchedRW.Folded, !listconcat([SPRPort02_03_10], ExePorts)> {
117 let Latency = !add(Lat, LoadLat);
118 let ReleaseAtCycles = !listconcat([1], Res);
119 let NumMicroOps = !add(UOps, LoadUOps);
120 }
121 }
123 //===----------------------------------------------------------------------===//
124 // The following definitons are infered by smg.
125 //===----------------------------------------------------------------------===//
127 // Infered SchedWrite definition.
128 def : WriteRes<WriteADC, [SPRPort00_06]>;
129 defm : X86WriteRes<WriteADCLd, [SPRPort00_01_05_06_11, SPRPort00_06], 11, [1, 1], 2>;
130 defm : SPRWriteResPair<WriteAESDecEnc, [SPRPort00_01], 5, [1], 1, 7>;
131 defm : SPRWriteResPair<WriteAESIMC, [SPRPort00_01], 8, [2], 2, 7>;
132 defm : X86WriteRes<WriteAESKeyGen, [SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort01_05, SPRPort05], 7, [4, 1, 1, 2, 3, 3], 14>;
133 defm : X86WriteRes<WriteAESKeyGenLd, [SPRPort00, SPRPort00_01, SPRPort00_06, SPRPort01_05, SPRPort02_03_10, SPRPort05], 12, [4, 1, 2, 3, 1, 3], 14>;
134 def : WriteRes<WriteALU, [SPRPort00_01_05_06_11]>;
135 def : WriteRes<WriteALULd, [SPRPort00_01_05_06_11]> {
136 let Latency = 11;
137 }
138 defm : SPRWriteResPair<WriteBEXTR, [SPRPort00_06, SPRPort01], 6, [1, 1], 2>;
139 defm : SPRWriteResPair<WriteBLS, [SPRPort01_05_11], 2, [1]>;
140 defm : SPRWriteResPair<WriteBSF, [SPRPort01], 3, [1]>;
141 defm : SPRWriteResPair<WriteBSR, [SPRPort01], 3, [1]>;
142 def : WriteRes<WriteBSWAP32, [SPRPort01]>;
143 defm : X86WriteRes<WriteBSWAP64, [SPRPort00_06, SPRPort01], 2, [1, 1], 2>;
144 defm : SPRWriteResPair<WriteBZHI, [SPRPort01], 3, [1]>;
145 def : WriteRes<WriteBitTest, [SPRPort01]>;
146 defm : X86WriteRes<WriteBitTestImmLd, [SPRPort01, SPRPort02_03_10], 6, [1, 1], 2>;
147 defm : X86WriteRes<WriteBitTestRegLd, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10], 11, [4, 2, 1, 2, 1], 10>;
148 def : WriteRes<WriteBitTestSet, [SPRPort01]>;
149 def : WriteRes<WriteBitTestSetImmLd, [SPRPort01]> {
150 let Latency = 11;
151 }
152 defm : X86WriteRes<WriteBitTestSetRegLd, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11], 17, [3, 2, 1, 2], 8>;
153 defm : SPRWriteResPair<WriteBlend, [SPRPort01_05], 1, [1], 1, 7>;
154 defm : SPRWriteResPair<WriteBlendY, [SPRPort00_01_05], 1, [1], 1, 8>;
155 defm : SPRWriteResPair<WriteCLMul, [SPRPort05], 3, [1], 1, 7>;
156 defm : SPRWriteResPair<WriteCMOV, [SPRPort00_06], 1, [1], 1, 6>;
157 defm : X86WriteRes<WriteCMPXCHG, [SPRPort00_01_05_06_11, SPRPort00_06], 3, [3, 2], 5>;
158 defm : X86WriteRes<WriteCMPXCHGRMW, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08], 12, [1, 2, 1, 1, 1], 6>;
159 defm : SPRWriteResPair<WriteCRC32, [SPRPort01], 3, [1]>;
160 defm : X86WriteRes<WriteCvtI2PD, [SPRPort00_01, SPRPort05], 5, [1, 1], 2>;
161 defm : X86WriteRes<WriteCvtI2PDLd, [SPRPort00_01, SPRPort02_03_10], 11, [1, 1], 2>;
162 defm : X86WriteRes<WriteCvtI2PDY, [SPRPort00_01, SPRPort05], 7, [1, 1], 2>;
163 defm : X86WriteRes<WriteCvtI2PDYLd, [SPRPort00_01, SPRPort02_03_10], 12, [1, 1], 2>;
164 defm : SPRWriteResPair<WriteCvtI2PDZ, [SPRPort00], 4, [1], 1, 8>;
165 defm : SPRWriteResPair<WriteCvtI2PS, [SPRPort00_01], 4, [1], 1, 7>;
166 defm : SPRWriteResPair<WriteCvtI2PSY, [SPRPort00_01], 4, [1], 1, 8>;
167 defm : SPRWriteResPair<WriteCvtI2PSZ, [SPRPort00], 4, [1], 1, 8>;
168 defm : X86WriteRes<WriteCvtI2SD, [SPRPort00_01, SPRPort05], 7, [1, 1], 2>;
169 defm : X86WriteRes<WriteCvtI2SDLd, [SPRPort00_01, SPRPort02_03_10], 11, [1, 1], 2>;
170 defm : X86WriteRes<WriteCvtI2SS, [SPRPort00_01, SPRPort00_01_05, SPRPort05], 9, [1, 1, 1], 3>;
171 defm : X86WriteRes<WriteCvtI2SSLd, [SPRPort00_01, SPRPort02_03_10], 11, [1, 1], 2>;
172 defm : X86WriteRes<WriteCvtPD2I, [SPRPort00_01, SPRPort05], 5, [1, 1], 2>;
173 defm : X86WriteRes<WriteCvtPD2ILd, [SPRPort00_01, SPRPort02_03_10], 12, [1, 1], 2>;
174 defm : X86WriteRes<WriteCvtPD2IY, [SPRPort00_01, SPRPort05], 7, [1, 1], 2>;
175 defm : X86WriteRes<WriteCvtPD2IYLd, [SPRPort00_01, SPRPort02_03_10], 12, [1, 1], 2>;
176 defm : X86WriteRes<WriteCvtPD2IZ, [SPRPort00, SPRPort05], 7, [1, 1], 2>;
177 defm : X86WriteRes<WriteCvtPD2IZLd, [SPRPort00, SPRPort02_03_10], 12, [1, 1], 2>;
178 defm : SPRWriteResPair<WriteCvtPD2PS, [SPRPort00_01, SPRPort05], 5, [1, 1], 2, 7>;
179 defm : SPRWriteResPair<WriteCvtPD2PSY, [SPRPort00_01, SPRPort05], 7, [1, 1], 2, 8>;
180 defm : SPRWriteResPair<WriteCvtPD2PSZ, [SPRPort00, SPRPort05], 7, [1, 1], 2, 8>;
181 defm : X86WriteRes<WriteCvtPH2PS, [SPRPort00_01, SPRPort05], 6, [1, 1], 2>;
182 defm : X86WriteRes<WriteCvtPH2PSLd, [SPRPort00_01, SPRPort02_03_10], 12, [1, 1], 2>;
183 defm : X86WriteRes<WriteCvtPH2PSY, [SPRPort00_01, SPRPort05], 8, [1, 1], 2>;
184 defm : X86WriteRes<WriteCvtPH2PSYLd, [SPRPort00_01, SPRPort02_03_10], 12, [1, 1], 2>;
185 defm : SPRWriteResPair<WriteCvtPH2PSZ, [SPRPort00, SPRPort05], 11, [1, 1], 2>;
186 defm : SPRWriteResPair<WriteCvtPS2I, [SPRPort00_01], 4, [1], 1, 7>;
187 defm : SPRWriteResPair<WriteCvtPS2IY, [SPRPort00_01], 4, [1], 1, 8>;
188 defm : X86WriteRes<WriteCvtPS2IZ, [SPRPort00, SPRPort00_05, SPRPort05], 10, [1, 2, 1], 4>;
189 defm : X86WriteRes<WriteCvtPS2IZLd, [SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_10, SPRPort05], 18, [1, 2, 1, 1, 1], 6>;
190 defm : X86WriteRes<WriteCvtPS2PD, [SPRPort00_01, SPRPort05], 5, [1, 1], 2>;
191 defm : X86WriteRes<WriteCvtPS2PDLd, [SPRPort00_01, SPRPort02_03_10], 11, [1, 1], 2>;
192 defm : X86WriteRes<WriteCvtPS2PDY, [SPRPort00_01, SPRPort05], 7, [1, 1], 2>;
193 defm : X86WriteRes<WriteCvtPS2PDYLd, [SPRPort00_01, SPRPort02_03_10], 12, [1, 1], 2>;
194 defm : SPRWriteResPair<WriteCvtPS2PDZ, [SPRPort00, SPRPort05], 7, [1, 1], 2, 6>;
195 defm : X86WriteRes<WriteCvtPS2PH, [SPRPort00_01, SPRPort05], 6, [1, 1], 2>;
196 defm : X86WriteRes<WriteCvtPS2PHSt, [SPRPort00_01, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1], 3>;
197 defm : X86WriteRes<WriteCvtPS2PHY, [SPRPort00_01, SPRPort05], 8, [1, 1], 2>;
198 defm : X86WriteRes<WriteCvtPS2PHYSt, [SPRPort00_01, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1], 3>;
199 defm : X86WriteRes<WriteCvtPS2PHZ, [SPRPort00, SPRPort05], 11, [1, 1], 2>;
200 defm : X86WriteRes<WriteCvtPS2PHZSt, [SPRPort00, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1], 3>;
201 defm : SPRWriteResPair<WriteCvtSD2I, [SPRPort00, SPRPort00_01], 7, [1, 1], 2>;
202 defm : SPRWriteResPair<WriteCvtSD2SS, [SPRPort00_01, SPRPort05], 5, [1, 1], 2, 7>;
203 defm : SPRWriteResPair<WriteCvtSS2I, [SPRPort00, SPRPort00_01], 7, [1, 1], 2>;
204 defm : X86WriteRes<WriteCvtSS2SD, [SPRPort00_01, SPRPort05], 5, [1, 1], 2>;
205 defm : X86WriteRes<WriteCvtSS2SDLd, [SPRPort00_01, SPRPort02_03_10], 11, [1, 1], 2>;
206 defm : SPRWriteResPair<WriteDPPD, [SPRPort00_01, SPRPort01_05], 9, [2, 1], 3, 7>;
207 defm : SPRWriteResPair<WriteDPPS, [SPRPort00_01, SPRPort00_06, SPRPort01_05, SPRPort05], 14, [2, 1, 2, 1], 6, 7>;
208 defm : SPRWriteResPair<WriteDPPSY, [SPRPort00_01, SPRPort00_06, SPRPort01_05, SPRPort05], 14, [2, 1, 2, 1], 6, 8>;
209 defm : SPRWriteResPair<WriteDiv16, [SPRPort00_01_05_06_11, SPRPort01], 16, [1, 3], 4, 4>;
210 defm : SPRWriteResPair<WriteDiv32, [SPRPort00_01_05_06_11, SPRPort01], 15, [1, 3], 4, 4>;
211 defm : SPRWriteResPair<WriteDiv64, [SPRPort01], 18, [3], 3>;
212 defm : X86WriteRes<WriteDiv8, [SPRPort01], 17, [3], 3>;
213 defm : X86WriteRes<WriteDiv8Ld, [SPRPort01], 22, [3], 3>;
214 defm : X86WriteRes<WriteEMMS, [SPRPort00, SPRPort00_05, SPRPort00_06], 10, [1, 8, 1], 10>;
215 defm : SPRWriteResPair<WriteFAdd, [SPRPort01_05], 3, [1], 1, 7>;
216 defm : SPRWriteResPair<WriteFAdd64, [SPRPort01_05], 3, [1], 1, 7>;
217 defm : SPRWriteResPair<WriteFAdd64X, [SPRPort01_05], 3, [1], 1, 7>;
218 defm : SPRWriteResPair<WriteFAdd64Y, [SPRPort01_05], 3, [1], 1, 8>;
219 defm : SPRWriteResPair<WriteFAdd64Z, [SPRPort00_05], 4, [1], 1, 7>;
220 defm : SPRWriteResPair<WriteFAddX, [SPRPort00_01], 4, [1], 1, 7>;
221 defm : SPRWriteResPair<WriteFAddY, [SPRPort00_01], 4, [1], 1, 8>;
222 defm : SPRWriteResPair<WriteFAddZ, [SPRPort00], 4, [1], 1, 8>;
223 defm : SPRWriteResPair<WriteFBlend, [SPRPort00_01_05], 1, [1], 1, 7>;
224 defm : SPRWriteResPair<WriteFBlendY, [SPRPort00_01_05], 1, [1], 1, 8>;
225 def : WriteRes<WriteFCMOV, [SPRPort01]> {
226 let Latency = 3;
227 }
228 defm : SPRWriteResPair<WriteFCmp, [SPRPort00_01], 4, [1], 1, 7>;
229 defm : SPRWriteResPair<WriteFCmp64, [SPRPort00_01], 4, [1], 1, 7>;
230 defm : SPRWriteResPair<WriteFCmp64X, [SPRPort00_01], 4, [1], 1, 7>;
231 defm : SPRWriteResPair<WriteFCmp64Y, [SPRPort00_01], 4, [1], 1, 8>;
232 defm : SPRWriteResPair<WriteFCmp64Z, [SPRPort00], 4, [1], 1, 8>;
233 defm : SPRWriteResPair<WriteFCmpX, [SPRPort00_01], 4, [1], 1, 7>;
234 defm : SPRWriteResPair<WriteFCmpY, [SPRPort00_01], 4, [1], 1, 8>;
235 def : WriteRes<WriteFCmpZ, [SPRPort05]> {
236 let Latency = 3;
237 }
238 defm : X86WriteRes<WriteFCmpZLd, [SPRPort00, SPRPort02_03_10], 12, [1, 1], 2>;
239 defm : SPRWriteResPair<WriteFCom, [SPRPort05], 1, [1], 1, 7>;
240 defm : SPRWriteResPair<WriteFComX, [SPRPort00], 3, [1]>;
241 defm : SPRWriteResPair<WriteFDiv, [SPRPort00], 11, [1], 1, 7>;
242 defm : SPRWriteResPair<WriteFDiv64, [SPRPort00], 14, [1], 1, 6>;
243 defm : SPRWriteResPair<WriteFDiv64X, [SPRPort00], 14, [1], 1, 6>;
244 defm : SPRWriteResPair<WriteFDiv64Y, [SPRPort00], 14, [1], 1, 7>;
245 defm : SPRWriteResPair<WriteFDiv64Z, [SPRPort00, SPRPort00_05], 23, [2, 1], 3, 7>;
246 defm : SPRWriteResPair<WriteFDivX, [SPRPort00], 11, [1], 1, 7>;
247 defm : SPRWriteResPair<WriteFDivY, [SPRPort00], 11, [1], 1, 8>;
248 defm : SPRWriteResPair<WriteFDivZ, [SPRPort00, SPRPort00_05], 18, [2, 1], 3, 7>;
249 defm : SPRWriteResPair<WriteFHAdd, [SPRPort01_05, SPRPort05], 6, [1, 2], 3, 6>;
250 defm : SPRWriteResPair<WriteFHAddY, [SPRPort01_05, SPRPort05], 5, [1, 2], 3, 8>;
251 def : WriteRes<WriteFLD0, [SPRPort00_05]>;
252 defm : X86WriteRes<WriteFLD1, [SPRPort00_05], 1, [2], 2>;
253 defm : X86WriteRes<WriteFLDC, [SPRPort00_05], 1, [2], 2>;
254 def : WriteRes<WriteFLoad, [SPRPort02_03_10]> {
255 let Latency = 7;
256 }
257 def : WriteRes<WriteFLoadX, [SPRPort02_03_10]> {
258 let Latency = 7;
259 }
260 def : WriteRes<WriteFLoadY, [SPRPort02_03_10]> {
261 let Latency = 8;
262 }
263 defm : SPRWriteResPair<WriteFLogic, [SPRPort00_01_05], 1, [1], 1, 7>;
264 defm : SPRWriteResPair<WriteFLogicY, [SPRPort00_01_05], 1, [1], 1, 8>;
265 defm : SPRWriteResPair<WriteFLogicZ, [SPRPort00_05], 1, [1], 1, 8>;
266 defm : SPRWriteResPair<WriteFMA, [SPRPort00_01], 4, [1], 1, 7>;
267 defm : SPRWriteResPair<WriteFMAX, [SPRPort00_01], 4, [1], 1, 7>;
268 defm : SPRWriteResPair<WriteFMAY, [SPRPort00_01], 4, [1], 1, 8>;
269 defm : SPRWriteResPair<WriteFMAZ, [SPRPort00], 4, [1], 1, 8>;
270 def : WriteRes<WriteFMOVMSK, [SPRPort00]> {
271 let Latency = 3;
272 }
273 defm : X86WriteRes<WriteFMaskedLoad, [SPRPort00_01_05, SPRPort02_03_10], 8, [1, 1], 2>;
274 defm : X86WriteRes<WriteFMaskedLoadY, [SPRPort00_01_05, SPRPort02_03_10], 9, [1, 1], 2>;
275 defm : X86WriteRes<WriteFMaskedStore32, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
276 defm : X86WriteRes<WriteFMaskedStore32Y, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
277 defm : X86WriteRes<WriteFMaskedStore64, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
278 defm : X86WriteRes<WriteFMaskedStore64Y, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
279 defm : X86WriteRes<WriteFMoveX, [], 1, [], 0>;
280 defm : X86WriteRes<WriteFMoveY, [], 1, [], 0>;
281 def : WriteRes<WriteFMoveZ, [SPRPort00_05]>;
282 defm : SPRWriteResPair<WriteFMul, [SPRPort00_01], 4, [1], 1, 7>;
283 defm : SPRWriteResPair<WriteFMul64, [SPRPort00_01], 4, [1], 1, 7>;
284 defm : SPRWriteResPair<WriteFMul64X, [SPRPort00_01], 4, [1], 1, 7>;
285 defm : SPRWriteResPair<WriteFMul64Y, [SPRPort00_01], 4, [1], 1, 8>;
286 defm : SPRWriteResPair<WriteFMul64Z, [SPRPort00], 4, [1], 1, 8>;
287 defm : SPRWriteResPair<WriteFMulX, [SPRPort00_01], 4, [1], 1, 7>;
288 defm : SPRWriteResPair<WriteFMulY, [SPRPort00_01], 4, [1], 1, 8>;
289 defm : SPRWriteResPair<WriteFMulZ, [SPRPort00], 4, [1], 1, 8>;
290 defm : SPRWriteResPair<WriteFRcp, [SPRPort00], 4, [1], 1, 7>;
291 defm : SPRWriteResPair<WriteFRcpX, [SPRPort00], 4, [1], 1, 7>;
292 defm : SPRWriteResPair<WriteFRcpY, [SPRPort00], 4, [1], 1, 8>;
293 defm : SPRWriteResPair<WriteFRcpZ, [SPRPort00, SPRPort00_05], 7, [2, 1], 3, 7>;
294 defm : SPRWriteResPair<WriteFRnd, [SPRPort00_01], 4, [1], 1, 7>;
295 defm : SPRWriteResPair<WriteFRndY, [SPRPort00_01], 4, [1], 1, 8>;
296 defm : SPRWriteResPair<WriteFRndZ, [SPRPort00], 4, [1], 1, 8>;
297 defm : SPRWriteResPair<WriteFRsqrt, [SPRPort00], 4, [1], 1, 7>;
298 defm : SPRWriteResPair<WriteFRsqrtX, [SPRPort00], 4, [1], 1, 7>;
299 defm : SPRWriteResPair<WriteFRsqrtY, [SPRPort00], 4, [1], 1, 8>;
300 defm : SPRWriteResPair<WriteFRsqrtZ, [SPRPort00, SPRPort00_05], 9, [2, 1], 3>;
301 defm : SPRWriteResPair<WriteFShuffle, [SPRPort05], 1, [1], 1, 7>;
302 defm : SPRWriteResPair<WriteFShuffle256, [SPRPort05], 3, [1], 1, 8>;
303 defm : SPRWriteResPair<WriteFShuffleY, [SPRPort05], 1, [1], 1, 8>;
304 defm : SPRWriteResPair<WriteFShuffleZ, [SPRPort05], 1, [1], 1, 8>;
305 def : WriteRes<WriteFSign, [SPRPort00]>;
306 defm : SPRWriteResPair<WriteFSqrt, [SPRPort00], 12, [1], 1, 7>;
307 defm : SPRWriteResPair<WriteFSqrt64, [SPRPort00], 18, [1]>;
308 defm : SPRWriteResPair<WriteFSqrt64X, [SPRPort00], 18, [1], 1, 6>;
309 defm : SPRWriteResPair<WriteFSqrt64Y, [SPRPort00], 18, [1], 1, 3>;
310 // Warning: negtive load latency.
311 defm : SPRWriteResPair<WriteFSqrt64Z, [SPRPort00, SPRPort00_05], 32, [2, 1], 3, -1>;
312 def : WriteRes<WriteFSqrt80, [SPRPortInvalid, SPRPort00]> {
313 let ReleaseAtCycles = [7, 1];
314 let Latency = 21;
315 }
316 defm : SPRWriteResPair<WriteFSqrtX, [SPRPort00], 12, [1], 1, 7>;
317 defm : SPRWriteResPair<WriteFSqrtY, [SPRPort00], 12, [1], 1, 8>;
318 defm : SPRWriteResPair<WriteFSqrtZ, [SPRPort00, SPRPort00_05], 20, [2, 1], 3, 7>;
319 defm : X86WriteRes<WriteFStore, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>;
320 defm : X86WriteResUnsupported<WriteFStoreNT>;
321 defm : X86WriteRes<WriteFStoreNTX, [SPRPort04_09, SPRPort07_08], 518, [1, 1], 2>;
322 defm : X86WriteRes<WriteFStoreNTY, [SPRPort04_09, SPRPort07_08], 542, [1, 1], 2>;
323 defm : X86WriteRes<WriteFStoreX, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>;
324 defm : X86WriteRes<WriteFStoreY, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>;
325 defm : SPRWriteResPair<WriteFTest, [SPRPort00], 3, [1]>;
326 defm : SPRWriteResPair<WriteFTestY, [SPRPort00], 5, [1], 1, 6>;
327 defm : SPRWriteResPair<WriteFVarBlend, [SPRPort00_01_05], 1, [1], 1, 7>;
328 defm : SPRWriteResPair<WriteFVarBlendY, [SPRPort00_01_05], 1, [1], 1, 8>;
329 defm : SPRWriteResPair<WriteFVarBlendZ, [SPRPort00_05], 1, [1], 1, 8>;
330 defm : SPRWriteResPair<WriteFVarShuffle, [SPRPort05], 1, [1], 1, 7>;
331 defm : SPRWriteResPair<WriteFVarShuffle256, [SPRPort05], 3, [1], 1, 8>;
332 defm : SPRWriteResPair<WriteFVarShuffleY, [SPRPort05], 1, [1], 1, 8>;
333 defm : SPRWriteResPair<WriteFVarShuffleZ, [SPRPort05], 1, [1], 1, 8>;
334 def : WriteRes<WriteFence, [SPRPort00_06]> {
335 let Latency = 2;
336 }
337 defm : SPRWriteResPair<WriteIDiv16, [SPRPort00_01_05_06_11, SPRPort01], 16, [1, 3], 4, 4>;
338 defm : SPRWriteResPair<WriteIDiv32, [SPRPort00_01_05_06_11, SPRPort01], 15, [1, 3], 4, 4>;
339 defm : SPRWriteResPair<WriteIDiv64, [SPRPort01], 18, [3], 3>;
340 defm : X86WriteRes<WriteIDiv8, [SPRPort01], 17, [3], 3>;
341 defm : X86WriteRes<WriteIDiv8Ld, [SPRPort01], 22, [3], 3>;
342 defm : SPRWriteResPair<WriteIMul16, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01], 5, [2, 1, 1], 4>;
343 defm : SPRWriteResPair<WriteIMul16Imm, [SPRPort00_01_05_06_11, SPRPort01], 4, [1, 1], 2>;
344 defm : SPRWriteResPair<WriteIMul16Reg, [SPRPort01], 3, [1]>;
345 defm : SPRWriteResPair<WriteIMul32, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01], 4, [1, 1, 1], 3>;
346 defm : SPRWriteResPair<WriteIMul32Imm, [SPRPort01], 3, [1]>;
347 defm : SPRWriteResPair<WriteIMul32Reg, [SPRPort01], 3, [1]>;
348 defm : SPRWriteResPair<WriteIMul64, [SPRPort01, SPRPort05], 4, [1, 1], 2>;
349 defm : SPRWriteResPair<WriteIMul64Imm, [SPRPort01], 3, [1]>;
350 defm : SPRWriteResPair<WriteIMul64Reg, [SPRPort01], 3, [1]>;
351 defm : SPRWriteResPair<WriteIMul8, [SPRPort01], 3, [1]>;
352 def : WriteRes<WriteIMulH, []> {
353 let Latency = 3;
354 }
355 def : WriteRes<WriteIMulHLd, []> {
356 let Latency = 3;
357 }
358 defm : SPRWriteResPair<WriteJump, [SPRPort00_06], 1, [1]>;
359 def : WriteRes<WriteLAHFSAHF, [SPRPort00_06]> {
360 let Latency = 3;
361 }
362 defm : X86WriteRes<WriteLDMXCSR, [SPRPort00, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10], 7, [1, 1, 1, 1], 4>;
363 def : WriteRes<WriteLEA, [SPRPort01]>;
364 defm : SPRWriteResPair<WriteLZCNT, [SPRPort01], 3, [1]>;
365 def : WriteRes<WriteLoad, [SPRPort02_03_10]> {
366 let Latency = 5;
367 }
368 def : WriteRes<WriteMMXMOVMSK, [SPRPort00]> {
369 let Latency = 3;
370 }
371 defm : SPRWriteResPair<WriteMPSAD, [SPRPort01_05, SPRPort05], 4, [1, 1], 2, 7>;
372 defm : SPRWriteResPair<WriteMPSADY, [SPRPort01_05, SPRPort05], 4, [1, 1], 2, 8>;
373 defm : SPRWriteResPair<WriteMULX32, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01], 4, [1, 1, 1], 2>;
374 defm : SPRWriteResPair<WriteMULX64, [SPRPort01, SPRPort05], 4, [1, 1]>;
375 def : WriteRes<WriteMicrocoded, [SPRPort00_01_05_06]> {
376 let Latency = SapphireRapidsModel.MaxLatency;
377 }
378 def : WriteRes<WriteMove, [SPRPort00]> {
379 let Latency = 3;
380 }
381 defm : X86WriteRes<WriteNop, [], 1, [], 0>;
382 defm : X86WriteRes<WritePCmpEStrI, [SPRPort00, SPRPort00_01_05, SPRPort00_06, SPRPort01, SPRPort05], 16, [3, 2, 1, 1, 1], 8>;
383 defm : X86WriteRes<WritePCmpEStrILd, [SPRPort00, SPRPort00_01_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05], 31, [3, 1, 1, 1, 1, 1], 8>;
384 defm : X86WriteRes<WritePCmpEStrM, [SPRPort00, SPRPort00_01_05, SPRPort00_06, SPRPort01, SPRPort05], 16, [3, 3, 1, 1, 1], 9>;
385 defm : X86WriteRes<WritePCmpEStrMLd, [SPRPort00, SPRPort00_01_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05], 17, [3, 2, 1, 1, 1, 1], 9>;
386 defm : SPRWriteResPair<WritePCmpIStrI, [SPRPort00], 11, [3], 3, 20>;
387 defm : SPRWriteResPair<WritePCmpIStrM, [SPRPort00], 11, [3], 3>;
388 defm : SPRWriteResPair<WritePHAdd, [SPRPort00_05, SPRPort05], 3, [1, 2], 3, 8>;
389 defm : SPRWriteResPair<WritePHAddX, [SPRPort00_01_05, SPRPort01_05], 2, [1, 2], 3, 7>;
390 defm : SPRWriteResPair<WritePHAddY, [SPRPort00_01_05, SPRPort01_05], 2, [1, 2], 3, 8>;
391 defm : SPRWriteResPair<WritePHMINPOS, [SPRPort00], 4, [1], 1, 7>;
392 defm : SPRWriteResPair<WritePMULLD, [SPRPort00_01], 10, [2], 2, 8>;
393 defm : SPRWriteResPair<WritePMULLDY, [SPRPort00_01], 10, [2], 2, 8>;
394 defm : SPRWriteResPair<WritePMULLDZ, [SPRPort00], 10, [2], 2, 8>;
395 defm : SPRWriteResPair<WritePOPCNT, [SPRPort01], 3, [1]>;
396 defm : SPRWriteResPair<WritePSADBW, [SPRPort05], 3, [1], 1, 8>;
397 defm : SPRWriteResPair<WritePSADBWX, [SPRPort05], 3, [1], 1, 7>;
398 defm : SPRWriteResPair<WritePSADBWY, [SPRPort05], 3, [1], 1, 8>;
399 defm : SPRWriteResPair<WritePSADBWZ, [SPRPort05], 3, [1], 1, 8>;
400 defm : X86WriteRes<WriteRMW, [SPRPort02_03_10, SPRPort04_09, SPRPort07_08], 1, [1, 1, 1], 3>;
401 defm : X86WriteRes<WriteRotate, [SPRPort00_01_05_06_11, SPRPort00_06], 2, [1, 2], 3>;
402 defm : X86WriteRes<WriteRotateLd, [SPRPort00_01_05_06_11, SPRPort00_06], 12, [1, 2], 3>;
403 defm : X86WriteRes<WriteRotateCL, [SPRPort00_06], 2, [2], 2>;
404 defm : X86WriteRes<WriteRotateCLLd, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01], 19, [2, 3, 2], 7>;
405 defm : X86WriteRes<WriteSETCC, [SPRPort00_06], 2, [2], 2>;
406 defm : X86WriteRes<WriteSETCCStore, [SPRPort00_06, SPRPort04_09, SPRPort07_08], 13, [2, 1, 1], 4>;
407 defm : X86WriteRes<WriteSHDmrcl, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1, 1, 1, 1], 6>;
408 defm : X86WriteRes<WriteSHDmri, [SPRPort00_01_05_06_11, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1, 1, 1], 5>;
409 defm : X86WriteRes<WriteSHDrrcl, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01], 5, [1, 1, 1], 3>;
410 def : WriteRes<WriteSHDrri, [SPRPort01]> {
411 let Latency = 3;
412 }
413 defm : X86WriteRes<WriteSTMXCSR, [SPRPort00, SPRPort00_06, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1, 1], 4>;
414 def : WriteRes<WriteShift, [SPRPort00_06]>;
415 def : WriteRes<WriteShiftLd, [SPRPort00_06]> {
416 let Latency = 12;
417 }
418 defm : X86WriteRes<WriteShiftCL, [SPRPort00_06], 2, [2], 2>;
419 defm : X86WriteRes<WriteShiftCLLd, [SPRPort00_06], 12, [2], 2>;
420 defm : SPRWriteResPair<WriteShuffle, [SPRPort05], 1, [1], 1, 8>;
421 defm : SPRWriteResPair<WriteShuffle256, [SPRPort05], 3, [1], 1, 8>;
422 defm : SPRWriteResPair<WriteShuffleX, [SPRPort01_05], 1, [1], 1, 7>;
423 defm : SPRWriteResPair<WriteShuffleY, [SPRPort01_05], 1, [1], 1, 8>;
424 defm : SPRWriteResPair<WriteShuffleZ, [SPRPort05], 3, [1], 1, 6>;
425 defm : X86WriteRes<WriteStore, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>;
426 defm : X86WriteRes<WriteStoreNT, [SPRPort04_09, SPRPort07_08], 512, [1, 1], 2>;
427 def : WriteRes<WriteSystem, [SPRPort00_01_05_06]> {
428 let Latency = SapphireRapidsModel.MaxLatency;
429 }
430 defm : SPRWriteResPair<WriteTZCNT, [SPRPort01], 3, [1]>;
431 defm : SPRWriteResPair<WriteVPMOV256, [SPRPort05], 3, [1], 1, 8>;
432 defm : SPRWriteResPair<WriteVarBlend, [SPRPort00_01_05], 1, [1], 1, 7>;
433 defm : SPRWriteResPair<WriteVarBlendY, [SPRPort00_01_05], 1, [1], 1, 8>;
434 defm : SPRWriteResPair<WriteVarBlendZ, [SPRPort00_05], 1, [1], 1, 8>;
435 defm : SPRWriteResPair<WriteVarShuffle, [SPRPort00, SPRPort05], 3, [1, 1], 2, 8>;
436 defm : X86WriteRes<WriteVarShuffle256, [SPRPort05], 6, [2], 2>;
437 defm : X86WriteRes<WriteVarShuffle256Ld, [SPRPort02_03_10, SPRPort05], 11, [1, 1], 2>;
438 defm : SPRWriteResPair<WriteVarShuffleX, [SPRPort01_05], 1, [1], 1, 7>;
439 defm : SPRWriteResPair<WriteVarShuffleY, [SPRPort01_05], 1, [1], 1, 8>;
440 defm : SPRWriteResPair<WriteVarShuffleZ, [SPRPort05], 3, [1], 1, 8>;
441 defm : SPRWriteResPair<WriteVarVecShift, [SPRPort00_01], 1, [1], 1, 7>;
442 defm : SPRWriteResPair<WriteVarVecShiftY, [SPRPort00_01], 1, [1], 1, 8>;
443 defm : SPRWriteResPair<WriteVarVecShiftZ, [SPRPort00], 1, [1], 1, 8>;
444 defm : SPRWriteResPair<WriteVecALU, [SPRPort00], 1, [1], 1, 8>;
445 defm : SPRWriteResPair<WriteVecALUX, [SPRPort00_01], 1, [1], 1, 7>;
446 defm : SPRWriteResPair<WriteVecALUY, [SPRPort00_01], 1, [1], 1, 8>;
447 def : WriteRes<WriteVecALUZ, [SPRPort05]> {
448 let Latency = 3;
449 }
450 defm : X86WriteRes<WriteVecALUZLd, [SPRPort00, SPRPort02_03_10], 9, [1, 1], 2>;
451 defm : X86WriteRes<WriteVecExtract, [SPRPort00, SPRPort01_05], 4, [1, 1], 2>;
452 defm : X86WriteRes<WriteVecExtractSt, [SPRPort01_05, SPRPort04_09, SPRPort07_08], 19, [1, 1, 1], 3>;
453 defm : SPRWriteResPair<WriteVecIMul, [SPRPort00], 5, [1], 1, 8>;
454 defm : SPRWriteResPair<WriteVecIMulX, [SPRPort00_01], 5, [1], 1, 8>;
455 defm : SPRWriteResPair<WriteVecIMulY, [SPRPort00_01], 5, [1], 1, 8>;
456 defm : SPRWriteResPair<WriteVecIMulZ, [SPRPort00], 5, [1], 1, 8>;
457 defm : X86WriteRes<WriteVecInsert, [SPRPort01_05, SPRPort05], 4, [1, 1], 2>;
458 defm : X86WriteRes<WriteVecInsertLd, [SPRPort01_05, SPRPort02_03_10], 8, [1, 1], 2>;
459 def : WriteRes<WriteVecLoad, [SPRPort02_03_10]> {
460 let Latency = 7;
461 }
462 def : WriteRes<WriteVecLoadNT, [SPRPort02_03_10]> {
463 let Latency = 7;
464 }
465 def : WriteRes<WriteVecLoadNTY, [SPRPort02_03_10]> {
466 let Latency = 8;
467 }
468 def : WriteRes<WriteVecLoadX, [SPRPort02_03_10]> {
469 let Latency = 7;
470 }
471 def : WriteRes<WriteVecLoadY, [SPRPort02_03_10]> {
472 let Latency = 8;
473 }
474 defm : SPRWriteResPair<WriteVecLogic, [SPRPort00_05], 1, [1], 1, 8>;
475 defm : SPRWriteResPair<WriteVecLogicX, [SPRPort00_01_05], 1, [1], 1, 7>;
476 defm : SPRWriteResPair<WriteVecLogicY, [SPRPort00_01_05], 1, [1], 1, 8>;
477 defm : SPRWriteResPair<WriteVecLogicZ, [SPRPort00_05], 1, [1], 1, 8>;
478 def : WriteRes<WriteVecMOVMSK, [SPRPort00]> {
479 let Latency = 3;
480 }
481 def : WriteRes<WriteVecMOVMSKY, [SPRPort00]> {
482 let Latency = 4;
483 }
484 defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;
485 defm : X86WriteRes<WriteVecMaskedLoad, [SPRPort00_01_05, SPRPort02_03_10], 8, [1, 1], 2>;
486 defm : X86WriteRes<WriteVecMaskedLoadY, [SPRPort00_01_05, SPRPort02_03_10], 9, [1, 1], 2>;
487 defm : X86WriteRes<WriteVecMaskedStore32, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
488 defm : X86WriteRes<WriteVecMaskedStore32Y, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
489 defm : X86WriteRes<WriteVecMaskedStore64, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
490 defm : X86WriteRes<WriteVecMaskedStore64Y, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
491 def : WriteRes<WriteVecMove, [SPRPort00_05]>;
492 def : WriteRes<WriteVecMoveFromGpr, [SPRPort05]> {
493 let Latency = 3;
494 }
495 def : WriteRes<WriteVecMoveToGpr, [SPRPort00]> {
496 let Latency = 3;
497 }
498 defm : X86WriteRes<WriteVecMoveX, [], 1, [], 0>;
499 def : WriteRes<WriteVecMoveY, [SPRPort00_01_05]>;
500 def : WriteRes<WriteVecMoveZ, [SPRPort00_05]>;
501 defm : SPRWriteResPair<WriteVecShift, [SPRPort00], 1, [1], 1, 8>;
502 def : WriteRes<WriteVecShiftImm, [SPRPort00]>;
503 defm : SPRWriteResPair<WriteVecShiftImmX, [SPRPort00_01], 1, [1], 1, 7>;
504 defm : SPRWriteResPair<WriteVecShiftImmY, [SPRPort00_01], 1, [1], 1, 8>;
505 defm : SPRWriteResPair<WriteVecShiftImmZ, [SPRPort00], 1, [1], 1, 8>;
506 defm : X86WriteRes<WriteVecShiftX, [SPRPort00_01, SPRPort01_05], 2, [1, 1], 2>;
507 defm : X86WriteRes<WriteVecShiftXLd, [SPRPort00_01, SPRPort02_03_10], 8, [1, 1], 2>;
508 defm : X86WriteRes<WriteVecShiftY, [SPRPort00_01, SPRPort05], 4, [1, 1], 2>;
509 defm : X86WriteRes<WriteVecShiftYLd, [SPRPort00_01, SPRPort02_03_10], 9, [1, 1], 2>;
510 defm : X86WriteRes<WriteVecShiftZ, [SPRPort00, SPRPort05], 4, [1, 1], 2>;
511 defm : X86WriteRes<WriteVecShiftZLd, [SPRPort00, SPRPort02_03_10], 9, [1, 1], 2>;
512 defm : X86WriteRes<WriteVecStore, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>;
513 defm : X86WriteRes<WriteVecStoreNT, [SPRPort04_09, SPRPort07_08], 511, [1, 1], 2>;
514 defm : X86WriteRes<WriteVecStoreNTY, [SPRPort04_09, SPRPort07_08], 507, [1, 1], 2>;
515 defm : X86WriteRes<WriteVecStoreX, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>;
516 defm : X86WriteRes<WriteVecStoreY, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>;
517 defm : SPRWriteResPair<WriteVecTest, [SPRPort00, SPRPort05], 4, [1, 1], 2>;
518 defm : SPRWriteResPair<WriteVecTestY, [SPRPort00, SPRPort05], 6, [1, 1], 2, 6>;
519 defm : X86WriteRes<WriteXCHG, [SPRPort00_01_05_06_11], 2, [3], 3>;
520 def : WriteRes<WriteZero, []>;
522 // Infered SchedWriteRes and InstRW definition.
524 def SPRWriteResGroup0 : SchedWriteRes<[SPRPort02_03, SPRPort02_03_10, SPRPort04, SPRPort04_09]> {
525 let Latency = 7;
526 let NumMicroOps = 3;
527 }
528 def : InstRW<[SPRWriteResGroup0], (instregex "^AA(D|N)D64mr$",
529 "^A(X?)OR64mr$")>;
531 def SPRWriteResGroup1 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
532 let ReleaseAtCycles = [2, 1, 1, 1, 1];
533 let Latency = 12;
534 let NumMicroOps = 6;
535 }
536 def : InstRW<[SPRWriteResGroup1, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(16|32|64)mr$")>;
538 def SPRWriteResGroup2 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_10]> {
539 let Latency = 6;
540 let NumMicroOps = 2;
541 }
542 def : InstRW<[SPRWriteResGroup2], (instregex "^RORX(32|64)mi$")>;
543 def : InstRW<[SPRWriteResGroup2, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",
544 "^AD(C|O)X(32|64)rm$")>;
546 def SPRWriteResGroup3 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
547 let Latency = 13;
548 let NumMicroOps = 5;
549 }
550 def : InstRW<[SPRWriteResGroup3], (instregex "^(ADC|SBB)8mi(8?)$")>;
552 def SPRWriteResGroup4 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
553 let ReleaseAtCycles = [2, 1, 1, 1, 1];
554 let Latency = 13;
555 let NumMicroOps = 6;
556 }
557 def : InstRW<[SPRWriteResGroup4, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)8mr$")>;
559 def SPRWriteResGroup5 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> {
560 let Latency = 6;
561 let NumMicroOps = 2;
562 }
563 def : InstRW<[SPRWriteResGroup5], (instregex "^CMP(8|16|32)mi$",
564 "^CMP(8|16|32|64)mi8$",
565 "^MOV(8|16)rm$",
566 "^POP(16|32)r((mr)?)$")>;
567 def : InstRW<[SPRWriteResGroup5], (instrs CMP64mi32,
568 MOV8rm_NOREX,
569 MOVZX16rm8)>;
570 def : InstRW<[SPRWriteResGroup5, ReadAfterLd], (instregex "^(ADD|CMP|SUB)(8|16|32|64)rm$",
571 "^AND(8|16|32)rm$",
572 "^(X?)OR(8|16|32)rm$")>;
573 def : InstRW<[SPRWriteResGroup5, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^CMP(8|16|32|64)mr$")>;
575 def SPRWriteResGroup6 : SchedWriteRes<[]> {
576 let NumMicroOps = 0;
577 }
578 def : InstRW<[SPRWriteResGroup6], (instregex "^(ADD|SUB)64ri8$",
579 "^(DE|IN)C64r$",
580 "^MOV64rr((_REV)?)$",
581 "^VMOV(A|U)P(D|S)Zrr((_REV)?)$",
582 "^VMOVDQA(32|64)Z((256)?)rr((_REV)?)$",
583 "^VMOVDQ(A|U)Yrr((_REV)?)$",
584 "^VMOVDQU(8|16|32|64)Z((256)?)rr((_REV)?)$")>;
585 def : InstRW<[SPRWriteResGroup6], (instrs CLC,
586 JMP_2)>;
588 def SPRWriteResGroup7 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
589 let Latency = 13;
590 let NumMicroOps = 4;
591 }
592 def : InstRW<[SPRWriteResGroup7], (instregex "^A(D|N)D8mi(8?)$",
593 "^(DE|IN)C8m$",
594 "^N(EG|OT)8m$",
595 "^(X?)OR8mi(8?)$",
596 "^SUB8mi(8?)$")>;
597 def : InstRW<[SPRWriteResGroup7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^A(D|N)D8mr$",
598 "^(X?)OR8mr$")>;
599 def : InstRW<[SPRWriteResGroup7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs SUB8mr)>;
601 def SPRWriteResGroup8 : SchedWriteRes<[SPRPort01_05, SPRPort02_03_10]> {
602 let Latency = 10;
603 let NumMicroOps = 2;
604 }
605 def : InstRW<[SPRWriteResGroup8, ReadAfterVecXLd], (instregex "^(V?)(ADD|SUB)PSrm$",
606 "^(V?)ADDSUBPSrm$",
607 "^V(ADD|SUB)PSZ128rm((b|k|bk|kz)?)$",
608 "^V(ADD|SUB)PSZ128rmbkz$")>;
610 def SPRWriteResGroup9 : SchedWriteRes<[SPRPort01_05]> {
611 let Latency = 3;
612 }
613 def : InstRW<[SPRWriteResGroup9], (instregex "^(V?)(ADD|SUB)PSrr$",
614 "^(V?)ADDSUBPSrr$",
615 "^V(ADD|SUB)PSYrr$",
616 "^V(ADD|SUB)PSZ(128|256)rr(k?)$",
617 "^VPMOV(S|Z)XBWZ128rrk(z?)$",
618 "^VPSHUFBZ(128|256)rrk(z?)$",
619 "^VPSHUF(H|L)WZ(128|256)rik(z?)$",
620 "^VPUNPCK(H|L)(BW|WD)Z(128|256)rrk(z?)$")>;
621 def : InstRW<[SPRWriteResGroup9], (instrs VADDSUBPSYrr)>;
623 def SPRWriteResGroup10 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> {
624 let Latency = 10;
625 let NumMicroOps = 2;
626 }
627 def : InstRW<[SPRWriteResGroup10], (instregex "^ADD_F(32|64)m$",
628 "^ILD_F(16|32|64)m$",
629 "^SUB(R?)_F(32|64)m$",
630 "^VPOPCNT(B|D|Q|W)Z128rm$",
631 "^VPOPCNT(D|Q)Z128rm(b|k|kz)$",
632 "^VPOPCNT(D|Q)Z128rmbk(z?)$")>;
633 def : InstRW<[SPRWriteResGroup10, ReadAfterVecXLd], (instregex "^(V?)PACK(S|U)S(DW|WB)rm$",
634 "^(V?)PCMPGTQrm$",
635 "^VFPCLASSP(D|H|S)Z128mbi$",
636 "^VPACK(S|U)S(DW|WB)Z128rm$",
637 "^VPACK(S|U)SDWZ128rmb$",
638 "^VPM(AX|IN)(S|U)QZ128rm((b|k|bk|kz)?)$",
639 "^VPM(AX|IN)(S|U)QZ128rmbkz$",
640 "^VPMULTISHIFTQBZ128rm(b?)$")>;
641 def : InstRW<[SPRWriteResGroup10, ReadAfterVecXLd], (instrs VFPCLASSPHZ128mi)>;
642 def : InstRW<[SPRWriteResGroup10, ReadAfterVecYLd], (instregex "^VFPCLASSP(D|H|S)Z((256)?)mi$",
643 "^VPERM(I|T)2(D|Q|PS)Z128rm((b|k|bk|kz)?)$",
644 "^VPERM(I|T)2(D|Q|PS)Z128rmbkz$",
645 "^VPERM(I|T)2PDZ128rm((b|k|bk|kz)?)$",
646 "^VPERM(I|T)2PDZ128rmbkz$")>;
647 def : InstRW<[SPRWriteResGroup10, ReadAfterVecYLd], (instrs VPERMBZ128rm)>;
649 def SPRWriteResGroup11 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> {
650 let ReleaseAtCycles = [1, 2];
651 let Latency = 13;
652 let NumMicroOps = 3;
653 }
654 def : InstRW<[SPRWriteResGroup11], (instregex "^ADD_FI(16|32)m$",
655 "^SUB(R?)_FI(16|32)m$")>;
656 def : InstRW<[SPRWriteResGroup11, ReadAfterVecXLd], (instrs SHA256MSG2rm)>;
657 def : InstRW<[SPRWriteResGroup11, ReadAfterVecYLd], (instregex "^VPEXPAND(B|W)Z(128|256)rmk(z?)$",
658 "^VPEXPAND(B|W)Zrmk(z?)$")>;
660 def SPRWriteResGroup12 : SchedWriteRes<[SPRPort05]> {
661 let Latency = 3;
662 }
663 def : InstRW<[SPRWriteResGroup12], (instregex "^ADD_F(P?)rST0$",
664 "^KMOV(B|D|W)kr$",
665 "^(V?)PACK(S|U)S(DW|WB)rr$",
666 "^(V?)PCMPGTQrr$",
667 "^SUB(R?)_F(P?)rST0$",
668 "^SUB(R?)_FST0r$",
669 "^VALIGN(D|Q)Z256rri((k|kz)?)$",
670 "^VCMPP(D|H|S)Z(128|256)rri(k?)$",
671 "^VCMPS(D|H|S)Zrri$",
672 "^VCMPS(D|H|S)Zrr(b?)i(k?)_Int$",
673 "^VFPCLASSP(D|H|S)Z(128|256)ri(k?)$",
674 "^VFPCLASSS(D|H|S)Zri(k?)$",
675 "^VPACK(S|U)S(DW|WB)Yrr$",
676 "^VPACK(S|U)S(DW|WB)Z(128|256)rr$",
677 "^VPALIGNRZ(128|256)rrik(z?)$",
678 "^VPBROADCAST(B|W)Z128rrk(z?)$",
679 "^VPCMP(B|D|Q|W|UD|UQ|UW)Z(128|256)rri(k?)$",
680 "^VPCMP(EQ|GT)(B|D|Q|W)Z(128|256)rr(k?)$",
681 "^VPCMPUBZ(128|256)rri(k?)$",
682 "^VPERMBZ(128|256)rr$",
683 "^VPERM(B|D|Q)Zrr$",
684 "^VPERM(D|Q)Z256rr((k|kz)?)$",
685 "^VPERM(D|Q)Zrrk(z?)$",
686 "^VPERM(I|T)2(D|Q)Z(128|256)rr((k|kz)?)$",
687 "^VPERM(I|T)2(D|Q)Zrr((k|kz)?)$",
688 "^VPM(AX|IN)(S|U)QZ(128|256)rr((k|kz)?)$",
689 "^VPMULTISHIFTQBZ(128|256)rr$",
690 "^VPOPCNT(B|D|Q|W)Z(128|256)rr$",
691 "^VPOPCNT(D|Q)Z(128|256)rrk(z?)$",
692 "^VPTEST(N?)M(B|D|Q|W)Z(128|256)rr(k?)$",
693 "^VPTEST(N?)M(B|D|Q|W)Zrr(k?)$")>;
694 def : InstRW<[SPRWriteResGroup12], (instrs ADD_FST0r,
695 VPCMPGTQYrr,
696 VPERMDYrr)>;
698 def SPRWriteResGroup13 : SchedWriteRes<[SPRPort00_01_05_06_11]> {
699 let Latency = 2;
700 }
701 def : InstRW<[SPRWriteResGroup13], (instregex "^AND(8|16|32|64)r(r|i8)$",
702 "^AND(8|16|32|64)rr_REV$",
703 "^(AND|TEST)(32|64)i32$",
704 "^(AND|TEST)(8|32)ri$",
705 "^(AND|TEST)64ri32$",
706 "^(AND|TEST)8i8$",
707 "^(X?)OR(8|16|32|64)r(r|i8)$",
708 "^(X?)OR(8|16|32|64)rr_REV$",
709 "^(X?)OR(32|64)i32$",
710 "^(X?)OR(8|32)ri$",
711 "^(X?)OR64ri32$",
712 "^(X?)OR8i8$",
713 "^TEST(8|16|32|64)rr$")>;
714 def : InstRW<[SPRWriteResGroup13], (instrs XOR8rr_NOREX)>;
716 def SPRWriteResGroup14 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> {
717 let Latency = 7;
718 let NumMicroOps = 2;
719 }
720 def : InstRW<[SPRWriteResGroup14], (instregex "^TEST(8|16|32)mi$")>;
721 def : InstRW<[SPRWriteResGroup14], (instrs TEST64mi32)>;
722 def : InstRW<[SPRWriteResGroup14, ReadAfterLd], (instregex "^(X?)OR64rm$")>;
723 def : InstRW<[SPRWriteResGroup14, ReadAfterLd], (instrs AND64rm)>;
724 def : InstRW<[SPRWriteResGroup14, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^TEST(8|16|32|64)mr$")>;
726 def SPRWriteResGroup15 : SchedWriteRes<[SPRPort01_05_11, SPRPort02_03_10]> {
727 let Latency = 7;
728 let NumMicroOps = 2;
729 }
730 def : InstRW<[SPRWriteResGroup15, ReadAfterLd], (instregex "^ANDN(32|64)rm$")>;
732 def SPRWriteResGroup16 : SchedWriteRes<[SPRPort01_05_11]> {
733 let Latency = 2;
734 }
735 def : InstRW<[SPRWriteResGroup16], (instregex "^ANDN(32|64)rr$")>;
737 def SPRWriteResGroup17 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10]> {
738 let ReleaseAtCycles = [5, 2, 1, 1];
739 let Latency = 10;
740 let NumMicroOps = 9;
741 }
742 def : InstRW<[SPRWriteResGroup17], (instrs BT64mr)>;
744 def SPRWriteResGroup18 : SchedWriteRes<[SPRPort01]> {
745 let Latency = 3;
746 }
747 def : InstRW<[SPRWriteResGroup18], (instregex "^BT((C|R|S)?)64rr$",
748 "^P(DEP|EXT)(32|64)rr$")>;
750 def SPRWriteResGroup19 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
751 let ReleaseAtCycles = [4, 2, 1, 1, 1, 1];
752 let Latency = 17;
753 let NumMicroOps = 10;
754 }
755 def : InstRW<[SPRWriteResGroup19], (instregex "^BT(C|R|S)64mr$")>;
757 def SPRWriteResGroup20 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
758 let Latency = 7;
759 let NumMicroOps = 5;
760 }
761 def : InstRW<[SPRWriteResGroup20], (instregex "^CALL(16|32|64)m((_NT)?)$")>;
763 def SPRWriteResGroup21 : SchedWriteRes<[SPRPort00_06, SPRPort04_09, SPRPort07_08]> {
764 let Latency = 3;
765 let NumMicroOps = 3;
766 }
767 def : InstRW<[SPRWriteResGroup21], (instregex "^CALL(16|32|64)r((_NT)?)$")>;
769 def SPRWriteResGroup22 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
770 let Latency = 3;
771 let NumMicroOps = 2;
772 }
773 def : InstRW<[SPRWriteResGroup22], (instrs CALL64pcrel32,
774 MFENCE)>;
776 def SPRWriteResGroup23 : SchedWriteRes<[SPRPort01_05]>;
777 def : InstRW<[SPRWriteResGroup23], (instregex "^C(DQ|WD)E$",
778 "^(V?)MOVS(H|L)DUPrr$",
779 "^(V?)SHUFP(D|S)rri$",
780 "^VMOVS(H|L)DUPYrr$",
781 "^VMOVS(H|L)DUPZ(128|256)rr((k|kz)?)$",
782 "^VPMOVQDZ128rr((k|kz)?)$",
783 "^VSHUFP(D|S)Yrri$",
784 "^VSHUFP(D|S)Z(128|256)rri((k|kz)?)$")>;
785 def : InstRW<[SPRWriteResGroup23], (instrs CBW,
786 VPBLENDWYrri)>;
788 def SPRWriteResGroup24 : SchedWriteRes<[SPRPort00_06]>;
789 def : InstRW<[SPRWriteResGroup24], (instregex "^C(DQ|QO)$",
790 "^(CL|ST)AC$")>;
792 def SPRWriteResGroup25 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> {
793 let Latency = 3;
794 let NumMicroOps = 2;
795 }
796 def : InstRW<[SPRWriteResGroup25], (instrs CLD)>;
798 def SPRWriteResGroup26 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> {
799 let Latency = 3;
800 let NumMicroOps = 3;
801 }
802 def : InstRW<[SPRWriteResGroup26], (instrs CLDEMOTE)>;
804 def SPRWriteResGroup27 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort04_09, SPRPort07_08]> {
805 let Latency = 2;
806 let NumMicroOps = 4;
807 }
808 def : InstRW<[SPRWriteResGroup27], (instrs CLFLUSH)>;
810 def SPRWriteResGroup28 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> {
811 let Latency = 2;
812 let NumMicroOps = 3;
813 }
814 def : InstRW<[SPRWriteResGroup28], (instrs CLFLUSHOPT)>;
816 def SPRWriteResGroup29 : SchedWriteRes<[SPRPort00_06, SPRPort01]> {
817 let ReleaseAtCycles = [2, 1];
818 let Latency = SapphireRapidsModel.MaxLatency;
819 let NumMicroOps = 3;
820 }
821 def : InstRW<[SPRWriteResGroup29], (instrs CLI)>;
823 def SPRWriteResGroup30 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort05]> {
824 let ReleaseAtCycles = [6, 1, 3];
825 let Latency = SapphireRapidsModel.MaxLatency;
826 let NumMicroOps = 10;
827 }
828 def : InstRW<[SPRWriteResGroup30], (instrs CLTS)>;
830 def SPRWriteResGroup31 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> {
831 let Latency = 5;
832 let NumMicroOps = 3;
833 }
834 def : InstRW<[SPRWriteResGroup31], (instregex "^MOV16o(16|32|64)a$")>;
835 def : InstRW<[SPRWriteResGroup31], (instrs CLWB)>;
837 def SPRWriteResGroup32 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> {
838 let ReleaseAtCycles = [5, 2];
839 let Latency = 6;
840 let NumMicroOps = 7;
841 }
842 def : InstRW<[SPRWriteResGroup32], (instregex "^CMPS(B|L|Q|W)$")>;
844 def SPRWriteResGroup33 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01_05, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
845 let ReleaseAtCycles = [2, 7, 6, 2, 1, 1, 2, 1];
846 let Latency = 32;
847 let NumMicroOps = 22;
848 }
849 def : InstRW<[SPRWriteResGroup33], (instrs CMPXCHG16B)>;
851 def SPRWriteResGroup34 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
852 let ReleaseAtCycles = [4, 7, 2, 1, 1, 1];
853 let Latency = 25;
854 let NumMicroOps = 16;
855 }
856 def : InstRW<[SPRWriteResGroup34], (instrs CMPXCHG8B)>;
858 def SPRWriteResGroup35 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
859 let ReleaseAtCycles = [1, 2, 1, 1, 1];
860 let Latency = 13;
861 let NumMicroOps = 6;
862 }
863 def : InstRW<[SPRWriteResGroup35], (instrs CMPXCHG8rm)>;
865 def SPRWriteResGroup36 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort05, SPRPort07_08]> {
866 let ReleaseAtCycles = [2, 1, 10, 6, 1, 5, 1];
867 let Latency = 18;
868 let NumMicroOps = 26;
869 }
870 def : InstRW<[SPRWriteResGroup36], (instrs CPUID)>;
872 def SPRWriteResGroup37 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
873 let Latency = 12;
874 let NumMicroOps = 3;
875 }
876 def : InstRW<[SPRWriteResGroup37], (instregex "^(V?)CVT(T?)PD2DQrm$",
877 "^VCVT(T?)PD2(U?)DQZ128rm((b|k|bk|kz)?)$",
878 "^VCVT(T?)PD2(U?)DQZ128rmbkz$",
879 "^VCVTPH2PSXZ128rm(b?)$",
880 "^VCVT(U?)QQ2PSZ128rm((b|k|bk|kz)?)$",
881 "^VCVT(U?)QQ2PSZ128rmbkz$")>;
882 def : InstRW<[SPRWriteResGroup37], (instrs CVTSI642SSrm)>;
883 def : InstRW<[SPRWriteResGroup37, ReadAfterVecLd], (instregex "^(V?)CVTSI642SSrm_Int$",
884 "^VCVT(U?)SI642SSZrm((_Int)?)$")>;
885 def : InstRW<[SPRWriteResGroup37, ReadAfterVecLd], (instrs VCVTSI642SSrm)>;
887 def SPRWriteResGroup38 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort02_03_10]> {
888 let Latency = 26;
889 let NumMicroOps = 3;
890 }
891 def : InstRW<[SPRWriteResGroup38], (instregex "^(V?)CVT(T?)SD2SIrm((_Int)?)$")>;
892 def : InstRW<[SPRWriteResGroup38, ReadAfterVecLd], (instregex "^VCVT(T?)SD2SIZrm$",
893 "^VCVT(T?)SD2(U?)SIZrm_Int$")>;
894 def : InstRW<[SPRWriteResGroup38, ReadAfterVecLd], (instrs VCVTTSD2USIZrm)>;
896 def SPRWriteResGroup39 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
897 let Latency = 7;
898 let NumMicroOps = 2;
899 }
900 def : InstRW<[SPRWriteResGroup39], (instregex "^VCVT(T?)PS2(U?)QQZ256rr((k|kz)?)$",
901 "^VCVT(U?)QQ2PSZ256rr((k|kz)?)$")>;
902 def : InstRW<[SPRWriteResGroup39, ReadInt2Fpu], (instrs CVTSI2SSrr)>;
903 def : InstRW<[SPRWriteResGroup39, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI2SSrr_Int$",
904 "^VCVT(U?)SI2SSZrr$",
905 "^VCVT(U?)SI2SSZrr(b?)_Int$")>;
906 def : InstRW<[SPRWriteResGroup39, ReadDefault, ReadInt2Fpu], (instrs VCVTSI2SSrr)>;
908 def SPRWriteResGroup40 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
909 let ReleaseAtCycles = [1, 2];
910 let Latency = 8;
911 let NumMicroOps = 3;
912 }
913 def : InstRW<[SPRWriteResGroup40, ReadInt2Fpu], (instrs CVTSI642SSrr)>;
914 def : InstRW<[SPRWriteResGroup40, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI642SSrr_Int$",
915 "^VCVT(U?)SI642SSZrr$",
916 "^VCVT(U?)SI642SSZrr(b?)_Int$")>;
917 def : InstRW<[SPRWriteResGroup40, ReadDefault, ReadInt2Fpu], (instrs VCVTSI642SSrr)>;
919 def SPRWriteResGroup41 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort05]> {
920 let Latency = 8;
921 let NumMicroOps = 3;
922 }
923 def : InstRW<[SPRWriteResGroup41], (instregex "^(V?)CVT(T?)SS2SI64rr_Int$",
924 "^VCVT(T?)SS2SI64Zrr$",
925 "^VCVT(T?)SS2(U?)SI64Zrr(b?)_Int$")>;
926 def : InstRW<[SPRWriteResGroup41], (instrs VCVTTSS2USI64Zrr)>;
927 def : InstRW<[SPRWriteResGroup41, ReadDefault], (instregex "^(V?)CVT(T?)SS2SI64rr$")>;
929 def SPRWriteResGroup42 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> {
930 let Latency = 2;
931 let NumMicroOps = 2;
932 }
933 def : InstRW<[SPRWriteResGroup42], (instregex "^J(E|R)CXZ$")>;
934 def : InstRW<[SPRWriteResGroup42], (instrs CWD)>;
936 def SPRWriteResGroup43 : SchedWriteRes<[SPRPort00_01_05_06]>;
937 def : InstRW<[SPRWriteResGroup43], (instregex "^(LD|ST)_Frr$",
938 "^MOV16s(m|r)$",
939 "^MOV(32|64)sr$")>;
940 def : InstRW<[SPRWriteResGroup43], (instrs DEC16r_alt,
941 SALC,
942 ST_FPrr,
943 SYSCALL)>;
945 def SPRWriteResGroup44 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
946 let Latency = 7;
947 }
948 def : InstRW<[SPRWriteResGroup44], (instrs DEC32r_alt)>;
950 def SPRWriteResGroup45 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
951 let Latency = 27;
952 let NumMicroOps = 2;
953 }
954 def : InstRW<[SPRWriteResGroup45], (instregex "^DIVR_F(32|64)m$")>;
956 def SPRWriteResGroup46 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
957 let Latency = 30;
958 let NumMicroOps = 3;
959 }
960 def : InstRW<[SPRWriteResGroup46], (instregex "^DIVR_FI(16|32)m$")>;
962 def SPRWriteResGroup47 : SchedWriteRes<[SPRPort00]> {
963 let Latency = 15;
964 }
965 def : InstRW<[SPRWriteResGroup47], (instregex "^DIVR_F(P?)rST0$")>;
966 def : InstRW<[SPRWriteResGroup47], (instrs DIVR_FST0r)>;
968 def SPRWriteResGroup48 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
969 let Latency = 19;
970 let NumMicroOps = 2;
971 }
972 def : InstRW<[SPRWriteResGroup48, ReadAfterVecLd], (instregex "^(V?)DIVSDrm$")>;
973 def : InstRW<[SPRWriteResGroup48, ReadAfterVecLd], (instrs VDIVSDZrm)>;
975 def SPRWriteResGroup49 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
976 let Latency = 22;
977 let NumMicroOps = 2;
978 }
979 def : InstRW<[SPRWriteResGroup49], (instregex "^DIV_F(32|64)m$")>;
980 def : InstRW<[SPRWriteResGroup49, ReadAfterVecLd], (instregex "^VSQRTSHZm((k|kz)?)_Int$")>;
981 def : InstRW<[SPRWriteResGroup49, ReadAfterVecLd], (instrs VSQRTSHZm)>;
983 def SPRWriteResGroup50 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
984 let Latency = 25;
985 let NumMicroOps = 3;
986 }
987 def : InstRW<[SPRWriteResGroup50], (instregex "^DIV_FI(16|32)m$")>;
989 def SPRWriteResGroup51 : SchedWriteRes<[SPRPort00]> {
990 let Latency = 20;
991 }
992 def : InstRW<[SPRWriteResGroup51], (instregex "^DIV_F(P?)rST0$")>;
993 def : InstRW<[SPRWriteResGroup51], (instrs DIV_FST0r)>;
995 def SPRWriteResGroup52 : SchedWriteRes<[SPRPort04, SPRPort04_09]>;
996 def : InstRW<[SPRWriteResGroup52], (instregex "^ENQCMD(S?)(16|32|64)$",
997 "^PUSHA(16|32)$",
998 "^ST_F(32|64)m$")>;
999 def : InstRW<[SPRWriteResGroup52], (instrs PUSHF32)>;
1001 def SPRWriteResGroup53 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1002 let ReleaseAtCycles = [2, 21, 2, 14, 4, 9, 5];
1003 let Latency = 126;
1004 let NumMicroOps = 57;
1005 }
1006 def : InstRW<[SPRWriteResGroup53], (instrs ENTER)>;
1008 def SPRWriteResGroup54 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> {
1009 let Latency = 12;
1010 let NumMicroOps = 3;
1011 }
1012 def : InstRW<[SPRWriteResGroup54], (instregex "^(V?)EXTRACTPSmri$",
1013 "^VPMOVQDZ((256)?)mr$")>;
1014 def : InstRW<[SPRWriteResGroup54], (instrs SMSW16m,
1015 VEXTRACTPSZmri)>;
1017 def SPRWriteResGroup55 : SchedWriteRes<[SPRPort00, SPRPort05]> {
1018 let Latency = 4;
1019 let NumMicroOps = 2;
1020 }
1021 def : InstRW<[SPRWriteResGroup55], (instregex "^(V?)EXTRACTPSrri$")>;
1022 def : InstRW<[SPRWriteResGroup55], (instrs MMX_PEXTRWrri,
1023 VEXTRACTPSZrri,
1024 VPERMWZrr)>;
1026 def SPRWriteResGroup56 : SchedWriteRes<[SPRPort02_03, SPRPort02_03_10, SPRPort04, SPRPort04_09, SPRPort06]> {
1027 let Latency = 7;
1028 let NumMicroOps = 5;
1029 }
1030 def : InstRW<[SPRWriteResGroup56], (instrs FARCALL64m)>;
1032 def SPRWriteResGroup57 : SchedWriteRes<[SPRPort02_03_10, SPRPort06]> {
1033 let Latency = 6;
1034 let NumMicroOps = 2;
1035 }
1036 def : InstRW<[SPRWriteResGroup57], (instrs FARJMP64m,
1037 JMP64m_REX)>;
1039 def SPRWriteResGroup58 : SchedWriteRes<[SPRPort04, SPRPort04_09]> {
1040 let NumMicroOps = 2;
1041 }
1042 def : InstRW<[SPRWriteResGroup58], (instregex "^(V?)MASKMOVDQU((64)?)$",
1043 "^ST_FP(32|64|80)m$")>;
1044 def : InstRW<[SPRWriteResGroup58], (instrs FBSTPm,
1045 VMPTRSTm)>;
1047 def SPRWriteResGroup59 : SchedWriteRes<[SPRPort00_05]> {
1048 let ReleaseAtCycles = [2];
1049 let Latency = 2;
1050 let NumMicroOps = 2;
1051 }
1052 def : InstRW<[SPRWriteResGroup59], (instrs FDECSTP)>;
1054 def SPRWriteResGroup60 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> {
1055 let ReleaseAtCycles = [1, 2];
1056 let Latency = 11;
1057 let NumMicroOps = 3;
1058 }
1059 def : InstRW<[SPRWriteResGroup60], (instregex "^FICOM(P?)(16|32)m$")>;
1060 def : InstRW<[SPRWriteResGroup60, ReadAfterVecYLd], (instregex "^VEXPANDP(D|S)Z((256)?)rm((k|kz)?)$",
1061 "^VPEXPAND(B|D|Q|W)Z((256)?)rm$",
1062 "^VPEXPAND(D|Q)Z((256)?)rmk(z?)$")>;
1064 def SPRWriteResGroup61 : SchedWriteRes<[SPRPort00_05]>;
1065 def : InstRW<[SPRWriteResGroup61], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rr$",
1066 "^VP(ADD|SUB)(B|D|Q|W)Zrr$",
1067 "^VP(ADD|SUB)(D|Q)Zrrk(z?)$",
1068 "^VPTERNLOG(D|Q)Zrri((k|kz)?)$")>;
1069 def : InstRW<[SPRWriteResGroup61], (instrs FINCSTP,
1070 FNOP)>;
1072 def SPRWriteResGroup62 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10]> {
1073 let Latency = 7;
1074 let NumMicroOps = 3;
1075 }
1076 def : InstRW<[SPRWriteResGroup62], (instrs FLDCW16m)>;
1078 def SPRWriteResGroup63 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03, SPRPort02_03_10]> {
1079 let ReleaseAtCycles = [2, 5, 10, 39, 8];
1080 let Latency = 62;
1081 let NumMicroOps = 64;
1082 }
1083 def : InstRW<[SPRWriteResGroup63], (instrs FLDENVm)>;
1085 def SPRWriteResGroup64 : SchedWriteRes<[SPRPort00_01_05_06]> {
1086 let ReleaseAtCycles = [4];
1087 let Latency = 4;
1088 let NumMicroOps = 4;
1089 }
1090 def : InstRW<[SPRWriteResGroup64], (instrs FNCLEX)>;
1092 def SPRWriteResGroup65 : SchedWriteRes<[SPRPort00_01_05_06, SPRPort00_05, SPRPort05]> {
1093 let ReleaseAtCycles = [6, 3, 6];
1094 let Latency = 75;
1095 let NumMicroOps = 15;
1096 }
1097 def : InstRW<[SPRWriteResGroup65], (instrs FNINIT)>;
1099 def SPRWriteResGroup66 : SchedWriteRes<[SPRPort04, SPRPort04_09, SPRPort06]> {
1100 let Latency = 2;
1101 let NumMicroOps = 3;
1102 }
1103 def : InstRW<[SPRWriteResGroup66], (instrs FNSTCW16m)>;
1105 def SPRWriteResGroup67 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06]> {
1106 let Latency = 3;
1107 let NumMicroOps = 2;
1108 }
1109 def : InstRW<[SPRWriteResGroup67], (instrs FNSTSW16r)>;
1111 def SPRWriteResGroup68 : SchedWriteRes<[SPRPort00, SPRPort04, SPRPort04_09]> {
1112 let Latency = 3;
1113 let NumMicroOps = 3;
1114 }
1115 def : InstRW<[SPRWriteResGroup68], (instrs FNSTSWm)>;
1117 def SPRWriteResGroup69 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06, SPRPort00_06, SPRPort01, SPRPort04, SPRPort04_09, SPRPort05, SPRPort06]> {
1118 let ReleaseAtCycles = [9, 11, 21, 1, 30, 11, 16, 1];
1119 let Latency = 106;
1120 let NumMicroOps = 100;
1121 }
1122 def : InstRW<[SPRWriteResGroup69], (instrs FSTENVm)>;
1124 def SPRWriteResGroup70 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort01_05, SPRPort02_03, SPRPort02_03_10, SPRPort06]> {
1125 let ReleaseAtCycles = [4, 1, 2, 1, 47, 33, 2];
1126 let Latency = 63;
1127 let NumMicroOps = 90;
1128 }
1129 def : InstRW<[SPRWriteResGroup70], (instrs FXRSTOR)>;
1131 def SPRWriteResGroup71 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort01_05, SPRPort02_03, SPRPort02_03_10, SPRPort06]> {
1132 let ReleaseAtCycles = [4, 1, 2, 1, 45, 31, 4];
1133 let Latency = 63;
1134 let NumMicroOps = 88;
1135 }
1136 def : InstRW<[SPRWriteResGroup71], (instrs FXRSTOR64)>;
1138 def SPRWriteResGroup72 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1139 let ReleaseAtCycles = [2, 5, 10, 10, 2, 38, 5, 38];
1140 let Latency = SapphireRapidsModel.MaxLatency;
1141 let NumMicroOps = 110;
1142 }
1143 def : InstRW<[SPRWriteResGroup72], (instregex "^FXSAVE((64)?)$")>;
1145 def SPRWriteResGroup73 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> {
1146 let Latency = 12;
1147 let NumMicroOps = 2;
1148 }
1149 def : InstRW<[SPRWriteResGroup73], (instregex "^VPLZCNT(D|Q)Z256rm((b|k|bk|kz)?)$",
1150 "^VPLZCNT(D|Q)Z256rmbkz$")>;
1151 def : InstRW<[SPRWriteResGroup73, ReadAfterVecXLd], (instregex "^(V?)GF2P8AFFINE((INV)?)QBrmi$",
1152 "^(V?)GF2P8MULBrm$",
1153 "^V(ADD|SUB)PHZ128rm((b|k|bk|kz)?)$",
1154 "^V(ADD|SUB)PHZ128rmbkz$",
1155 "^VGETEXPPHZ128m((b|k|bk|kz)?)$",
1156 "^VGETEXPSHZm((k|kz)?)$",
1157 "^VGETMANTPHZ128rm(bi|ik)$",
1158 "^VGETMANTPHZ128rmbik(z?)$",
1159 "^VGETMANTPHZ128rmi((kz)?)$",
1160 "^VGETMANTSHZrmi((k|kz)?)$",
1161 "^VGF2P8AFFINE((INV)?)QBZ128rm(b?)i$",
1162 "^VM(AX|IN)CPHZ128rm((b|k|bk|kz)?)$",
1163 "^VM(AX|IN)CPHZ128rmbkz$",
1164 "^VM(AX|IN|UL)PHZ128rm((b|k|bk|kz)?)$",
1165 "^VM(AX|IN|UL)PHZ128rmbkz$")>;
1166 def : InstRW<[SPRWriteResGroup73, ReadAfterVecXLd], (instrs VGETEXPPHZ128mbkz,
1167 VGF2P8MULBZ128rm)>;
1168 def : InstRW<[SPRWriteResGroup73, ReadAfterVecLd], (instregex "^V(ADD|SUB)SHZrm$",
1169 "^V(ADD|SUB)SHZrm((k|kz)?)_Int$",
1170 "^VCVTSH2SSZrm((_Int)?)$",
1171 "^VM(AX|IN)CSHZrm$",
1172 "^VM(AX|IN|UL)SHZrm$",
1173 "^VM(AX|IN|UL)SHZrm((k|kz)?)_Int$")>;
1174 def : InstRW<[SPRWriteResGroup73, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBYrmi$",
1175 "^VGF2P8AFFINE((INV)?)QBZ256rm(b?)i$",
1176 "^VGF2P8MULB(Y|Z256)rm$")>;
1177 def : InstRW<[SPRWriteResGroup73, ReadAfterVecXLd, ReadAfterVecXLd], (instregex "^VF(N?)M(ADD|SUB)(132|213|231)PHZ128m((b|k|bk|kz)?)$",
1178 "^VF(N?)M(ADD|SUB)(132|213|231)PHZ128mbkz$",
1179 "^VFMADDSUB(132|213|231)PHZ128m((b|k|bk|kz)?)$",
1180 "^VFMADDSUB(132|213|231)PHZ128mbkz$",
1181 "^VFMSUBADD(132|213|231)PHZ128m((b|k|bk|kz)?)$",
1182 "^VFMSUBADD(132|213|231)PHZ128mbkz$")>;
1183 def : InstRW<[SPRWriteResGroup73, ReadAfterVecLd, ReadAfterVecLd], (instregex "^VF(N?)M(ADD|SUB)(132|213|231)SHZm$",
1184 "^VF(N?)M(ADD|SUB)(132|213|231)SHZm((k|kz)?)_Int$")>;
1185 def : InstRW<[SPRWriteResGroup73, ReadAfterVecYLd, ReadAfterVecYLd], (instregex "^VPMADD52(H|L)UQZ256m((b|k|bk|kz)?)$",
1186 "^VPMADD52(H|L)UQZ256mbkz$")>;
1188 def SPRWriteResGroup74 : SchedWriteRes<[SPRPort00_01]> {
1189 let Latency = 5;
1190 }
1191 def : InstRW<[SPRWriteResGroup74], (instregex "^(V?)GF2P8MULBrr$",
1192 "^V(ADD|SUB)PHZ(128|256)rr$",
1193 "^V(ADD|SUB)SHZrr$",
1194 "^V(ADD|SUB)SHZrr(b?)_Int$",
1195 "^VCVT(T?)PH2(U?)WZ(128|256)rr$",
1196 "^VCVTSH2SSZrr(b?)_Int$",
1197 "^VCVT(U?)W2PHZ(128|256)rr$",
1198 "^VF(N?)M(ADD|SUB)(132|213|231)PHZ(128|256)r$",
1199 "^VF(N?)M(ADD|SUB)(132|213|231)SHZr(b?)((_Int)?)$",
1200 "^VFMADDSUB(132|213|231)PHZ(128|256)r$",
1201 "^VFMSUBADD(132|213|231)PHZ(128|256)r$",
1202 "^VGETEXPPHZ(128|256)r$",
1203 "^VGETEXPSHZr(b?)$",
1204 "^VGETMANTPHZ(128|256)rri$",
1205 "^VGETMANTSHZrri(b?)$",
1206 "^VGF2P8MULBZ(128|256)rr$",
1207 "^VM(AX|IN)CPHZ(128|256)rr$",
1208 "^VM(AX|IN)CSHZrr$",
1209 "^VM(AX|IN|UL)PHZ(128|256)rr$",
1210 "^VM(AX|IN|UL)SHZrr$",
1211 "^VM(AX|IN|UL)SHZrr(b?)_Int$")>;
1212 def : InstRW<[SPRWriteResGroup74], (instrs VCVTSH2SSZrr,
1213 VGF2P8MULBYrr)>;
1215 def SPRWriteResGroup75 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10, SPRPort05]> {
1216 let ReleaseAtCycles = [7, 5, 26, 19, 2, 7, 21];
1217 let Latency = 35;
1218 let NumMicroOps = 87;
1219 }
1220 def : InstRW<[SPRWriteResGroup75], (instrs IN16ri)>;
1222 def SPRWriteResGroup76 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10, SPRPort05]> {
1223 let ReleaseAtCycles = [7, 1, 4, 26, 19, 3, 7, 20];
1224 let Latency = 35;
1225 let NumMicroOps = 87;
1226 }
1227 def : InstRW<[SPRWriteResGroup76], (instrs IN16rr)>;
1229 def SPRWriteResGroup77 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10, SPRPort05]> {
1230 let ReleaseAtCycles = [7, 6, 28, 21, 2, 10, 20];
1231 let Latency = 35;
1232 let NumMicroOps = 94;
1233 }
1234 def : InstRW<[SPRWriteResGroup77], (instrs IN32ri)>;
1236 def SPRWriteResGroup78 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10, SPRPort05]> {
1237 let ReleaseAtCycles = [7, 9, 28, 21, 2, 11, 21];
1238 let NumMicroOps = 99;
1239 }
1240 def : InstRW<[SPRWriteResGroup78], (instrs IN32rr)>;
1242 def SPRWriteResGroup79 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10, SPRPort05]> {
1243 let ReleaseAtCycles = [7, 6, 25, 19, 2, 8, 20];
1244 let Latency = 35;
1245 let NumMicroOps = 87;
1246 }
1247 def : InstRW<[SPRWriteResGroup79], (instrs IN8ri)>;
1249 def SPRWriteResGroup80 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10, SPRPort05]> {
1250 let ReleaseAtCycles = [7, 6, 25, 19, 2, 7, 20];
1251 let Latency = 35;
1252 let NumMicroOps = 86;
1253 }
1254 def : InstRW<[SPRWriteResGroup80], (instrs IN8rr)>;
1256 def SPRWriteResGroup81 : SchedWriteRes<[SPRPort00_06]> {
1257 let NumMicroOps = 4;
1258 }
1259 def : InstRW<[SPRWriteResGroup81], (instrs INC16r_alt)>;
1261 def SPRWriteResGroup82 : SchedWriteRes<[SPRPort02_03_10]> {
1262 let Latency = 7;
1263 }
1264 def : InstRW<[SPRWriteResGroup82], (instregex "^LD_F(32|64|80)m$",
1265 "^(V?)MOV(D|SH|SL)DUPrm$",
1266 "^VBROADCASTSS((Z128)?)rm$",
1267 "^VMOV(D|SH|SL)DUPZ128rm$",
1268 "^VPBROADCAST(D|Q)((Z128)?)rm$")>;
1269 def : InstRW<[SPRWriteResGroup82], (instrs INC32r_alt,
1270 VBROADCASTI32X2Z128rm)>;
1272 def SPRWriteResGroup83 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1273 let ReleaseAtCycles = [7, 6, 24, 17, 8, 1, 19, 1];
1274 let Latency = 20;
1275 let NumMicroOps = 83;
1276 }
1277 def : InstRW<[SPRWriteResGroup83], (instrs INSB)>;
1279 def SPRWriteResGroup84 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1280 let ReleaseAtCycles = [7, 1, 5, 1, 27, 17, 11, 1, 21, 1];
1281 let Latency = 20;
1282 let NumMicroOps = 92;
1283 }
1284 def : InstRW<[SPRWriteResGroup84], (instrs INSL)>;
1286 def SPRWriteResGroup85 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1287 let ReleaseAtCycles = [7, 1, 4, 1, 25, 17, 1, 9, 1, 19, 1];
1288 let Latency = 20;
1289 let NumMicroOps = 86;
1290 }
1291 def : InstRW<[SPRWriteResGroup85], (instrs INSW)>;
1293 def SPRWriteResGroup86 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1294 let ReleaseAtCycles = [5, 4, 8, 6, 2, 5, 7, 5];
1295 let Latency = SapphireRapidsModel.MaxLatency;
1296 let NumMicroOps = 42;
1297 }
1298 def : InstRW<[SPRWriteResGroup86], (instrs INVLPG)>;
1300 def SPRWriteResGroup87 : SchedWriteRes<[SPRPort04, SPRPort04_09, SPRPort05]> {
1301 let Latency = 4;
1302 let NumMicroOps = 3;
1303 }
1304 def : InstRW<[SPRWriteResGroup87], (instregex "^IST(T?)_FP(16|32|64)m$",
1305 "^IST_F(16|32)m$")>;
1307 def SPRWriteResGroup88 : SchedWriteRes<[SPRPort00_01_05_06, SPRPort00_06]> {
1308 let Latency = 2;
1309 let NumMicroOps = 2;
1310 }
1311 def : InstRW<[SPRWriteResGroup88], (instrs JCXZ)>;
1313 def SPRWriteResGroup89 : SchedWriteRes<[SPRPort06]>;
1314 def : InstRW<[SPRWriteResGroup89], (instrs JMP64r_REX)>;
1316 def SPRWriteResGroup90 : SchedWriteRes<[]> {
1317 let Latency = 0;
1318 let NumMicroOps = 0;
1319 }
1320 def : InstRW<[SPRWriteResGroup90], (instregex "^JMP_(1|4)$")>;
1321 def : InstRW<[SPRWriteResGroup90], (instrs VZEROUPPER)>;
1323 def SPRWriteResGroup91 : SchedWriteRes<[SPRPort05]> {
1324 let Latency = 4;
1325 }
1326 def : InstRW<[SPRWriteResGroup91], (instregex "^KADD(B|D|Q|W)kk",
1327 "^KSHIFT(LB|RD|RQ|RW)ki$",
1328 "^KSHIFT(LD|RB)ki$",
1329 "^KSHIFTL(Q|W)ki$",
1330 "^KUNPCK(BW|DQ|WD)kk$")>;
1332 def SPRWriteResGroup92 : SchedWriteRes<[SPRPort00]>;
1333 def : InstRW<[SPRWriteResGroup92], (instregex "^KAND(B|D|Q|W|ND|NQ|NW)kk$",
1334 "^KMOV(B|D|Q|W)kk$",
1335 "^KNOT(B|D|Q|W)kk$",
1336 "^K((X|XN)?)OR(B|D|Q|W)kk$",
1337 "^VP(A|SU)BSBZrr$",
1338 "^VPABS(D|Q|W)Zrr$",
1339 "^VPABS(D|Q)Zrrk(z?)$",
1340 "^VPADD(U?)S(B|W)Zrr$",
1341 "^VPAVG(B|W)Zrr$",
1342 "^VPM(AX|IN)(SB|UD|UW)Zrr$",
1343 "^VPM(AX|IN)(SD|UB)Zrr$",
1344 "^VPM(AX|IN)(S|U)DZrrk(z?)$",
1345 "^VPM(AX|IN)SWZrr$",
1346 "^VPSH(L|R)D(D|Q|W)Zrri$",
1347 "^VPSH(L|R)DV(D|Q|W)Zr$",
1348 "^VPSH(L|R)DV(D|Q)Zrk(z?)$",
1349 "^VPSUB(U?)SWZrr$")>;
1350 def : InstRW<[SPRWriteResGroup92], (instrs KANDNBkk,
1351 VPSUBUSBZrr)>;
1353 def SPRWriteResGroup93 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> {
1354 let Latency = 7;
1355 let NumMicroOps = 2;
1356 }
1357 def : InstRW<[SPRWriteResGroup93], (instregex "^KMOV(B|D|Q|W)km$")>;
1359 def SPRWriteResGroup94 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
1360 let Latency = 13;
1361 let NumMicroOps = 2;
1362 }
1363 def : InstRW<[SPRWriteResGroup94], (instregex "^MOV8m(i|r)$")>;
1364 def : InstRW<[SPRWriteResGroup94], (instrs KMOVBmk,
1365 MOV8mr_NOREX)>;
1367 def SPRWriteResGroup95 : SchedWriteRes<[SPRPort05]>;
1368 def : InstRW<[SPRWriteResGroup95], (instregex "^(V?)PALIGNRrri$",
1369 "^VALIGN(D|Q)Z128rri((k|kz)?)$",
1370 "^VBROADCASTSSZ128rr((k|kz)?)$",
1371 "^VPALIGNR(Y|Z)rri$",
1372 "^VPALIGNRZ(128|256)rri$",
1373 "^VPBROADCAST(B|D|Q|W)rr$",
1374 "^VPSHUF(D|HW|LW)Zri$",
1375 "^VPSHUFDZrik(z?)$",
1376 "^VPS(L|R)LDQZri$",
1377 "^VPUNPCK(H|L)(BW|WD)Zrr$",
1378 "^VPUNPCK(H|L|LQ)DQZrr((k|kz)?)$",
1379 "^VPUNPCKHQDQZrr((k|kz)?)$")>;
1380 def : InstRW<[SPRWriteResGroup95], (instrs KMOVQkr,
1381 VPSHUFBZrr)>;
1383 def SPRWriteResGroup96 : SchedWriteRes<[SPRPort00]> {
1384 let Latency = 3;
1385 }
1386 def : InstRW<[SPRWriteResGroup96], (instregex "^K((OR)?)TEST(B|D|Q|W)kk$",
1387 "^VP(A|SU)BS(B|W)Zrrk(z?)$",
1388 "^VPADD(U?)S(B|W)Zrrk(z?)$",
1389 "^VPAVG(B|W)Zrrk(z?)$",
1390 "^VPM(AX|IN)(SB|UW)Zrrk(z?)$",
1391 "^VPM(AX|IN)(SW|UB)Zrrk(z?)$",
1392 "^VPSH(L|R)DVWZrk(z?)$",
1393 "^VPS(L|R)LVWZrrk(z?)$",
1394 "^VPS(L|R)LWZrik(z?)$",
1395 "^VPSRAVWZrrk(z?)$",
1396 "^VPSRAWZrik(z?)$",
1397 "^VPSUBUS(B|W)Zrrk(z?)$")>;
1398 def : InstRW<[SPRWriteResGroup96], (instrs VMOVSDto64Zrr)>;
1400 def SPRWriteResGroup97 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05]> {
1401 let ReleaseAtCycles = [8, 2, 14, 3, 1];
1402 let Latency = 198;
1403 let NumMicroOps = 81;
1404 }
1405 def : InstRW<[SPRWriteResGroup97], (instrs LAR16rm)>;
1407 def SPRWriteResGroup98 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
1408 let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1];
1409 let Latency = 66;
1410 let NumMicroOps = 22;
1411 }
1412 def : InstRW<[SPRWriteResGroup98], (instrs LAR16rr)>;
1414 def SPRWriteResGroup99 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05]> {
1415 let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1];
1416 let Latency = 71;
1417 let NumMicroOps = 85;
1418 }
1419 def : InstRW<[SPRWriteResGroup99], (instrs LAR32rm)>;
1421 def SPRWriteResGroup100 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
1422 let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1];
1423 let Latency = 65;
1424 let NumMicroOps = 22;
1425 }
1426 def : InstRW<[SPRWriteResGroup100], (instregex "^LAR(32|64)rr$")>;
1428 def SPRWriteResGroup101 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05]> {
1429 let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1];
1430 let Latency = 71;
1431 let NumMicroOps = 87;
1432 }
1433 def : InstRW<[SPRWriteResGroup101], (instrs LAR64rm)>;
1435 def SPRWriteResGroup102 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort01]> {
1436 let Latency = 2;
1437 let NumMicroOps = 2;
1438 }
1439 def : InstRW<[SPRWriteResGroup102], (instrs LEA16r)>;
1441 def SPRWriteResGroup103 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> {
1442 let ReleaseAtCycles = [3, 1];
1443 let Latency = 6;
1444 let NumMicroOps = 4;
1445 }
1446 def : InstRW<[SPRWriteResGroup103], (instregex "^LODS(B|W)$",
1447 "^SCAS(B|L|Q|W)$")>;
1448 def : InstRW<[SPRWriteResGroup103], (instrs LEAVE)>;
1450 def SPRWriteResGroup104 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> {
1451 let ReleaseAtCycles = [2, 1];
1452 let Latency = 6;
1453 let NumMicroOps = 3;
1454 }
1455 def : InstRW<[SPRWriteResGroup104], (instrs LEAVE64)>;
1457 def SPRWriteResGroup105 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
1458 let ReleaseAtCycles = [1, 2, 4, 3, 2, 1, 1];
1459 let Latency = SapphireRapidsModel.MaxLatency;
1460 let NumMicroOps = 14;
1461 }
1462 def : InstRW<[SPRWriteResGroup105], (instrs LGDT64m)>;
1464 def SPRWriteResGroup106 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
1465 let ReleaseAtCycles = [1, 1, 5, 3, 2, 1, 1];
1466 let Latency = SapphireRapidsModel.MaxLatency;
1467 let NumMicroOps = 14;
1468 }
1469 def : InstRW<[SPRWriteResGroup106], (instrs LIDT64m)>;
1471 def SPRWriteResGroup107 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
1472 let ReleaseAtCycles = [5, 3, 2, 1, 1];
1473 let Latency = SapphireRapidsModel.MaxLatency;
1474 let NumMicroOps = 12;
1475 }
1476 def : InstRW<[SPRWriteResGroup107], (instrs LLDT16m)>;
1478 def SPRWriteResGroup108 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
1479 let ReleaseAtCycles = [1, 4, 3, 1, 1, 1];
1480 let Latency = SapphireRapidsModel.MaxLatency;
1481 let NumMicroOps = 11;
1482 }
1483 def : InstRW<[SPRWriteResGroup108], (instrs LLDT16r)>;
1485 def SPRWriteResGroup109 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1486 let ReleaseAtCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2];
1487 let Latency = SapphireRapidsModel.MaxLatency;
1488 let NumMicroOps = 27;
1489 }
1490 def : InstRW<[SPRWriteResGroup109], (instrs LMSW16m)>;
1492 def SPRWriteResGroup110 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1493 let ReleaseAtCycles = [5, 7, 1, 2, 5, 2];
1494 let Latency = SapphireRapidsModel.MaxLatency;
1495 let NumMicroOps = 22;
1496 }
1497 def : InstRW<[SPRWriteResGroup110], (instrs LMSW16r)>;
1499 def SPRWriteResGroup111 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> {
1500 let ReleaseAtCycles = [2, 1];
1501 let Latency = 5;
1502 let NumMicroOps = 3;
1503 }
1504 def : InstRW<[SPRWriteResGroup111], (instregex "^LODS(L|Q)$")>;
1506 def SPRWriteResGroup112 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> {
1507 let ReleaseAtCycles = [2, 4, 1];
1508 let Latency = 3;
1509 let NumMicroOps = 7;
1510 }
1511 def : InstRW<[SPRWriteResGroup112], (instrs LOOP)>;
1513 def SPRWriteResGroup113 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> {
1514 let ReleaseAtCycles = [4, 6, 1];
1515 let Latency = 3;
1516 let NumMicroOps = 11;
1517 }
1518 def : InstRW<[SPRWriteResGroup113], (instrs LOOPE)>;
1520 def SPRWriteResGroup114 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> {
1521 let ReleaseAtCycles = [4, 6, 1];
1522 let Latency = 2;
1523 let NumMicroOps = 11;
1524 }
1525 def : InstRW<[SPRWriteResGroup114], (instrs LOOPNE)>;
1527 def SPRWriteResGroup115 : SchedWriteRes<[SPRPort02_03, SPRPort02_03_10, SPRPort06]> {
1528 let Latency = 7;
1529 let NumMicroOps = 3;
1530 }
1531 def : InstRW<[SPRWriteResGroup115], (instrs LRET64)>;
1533 def SPRWriteResGroup116 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05]> {
1534 let ReleaseAtCycles = [1, 5, 3, 3, 1];
1535 let Latency = 70;
1536 let NumMicroOps = 13;
1537 }
1538 def : InstRW<[SPRWriteResGroup116], (instregex "^LSL(16|32|64)rm$")>;
1540 def SPRWriteResGroup117 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05]> {
1541 let ReleaseAtCycles = [1, 4, 4, 3, 2, 1];
1542 let Latency = 63;
1543 let NumMicroOps = 15;
1544 }
1545 def : InstRW<[SPRWriteResGroup117], (instregex "^LSL(16|32|64)rr$")>;
1547 def SPRWriteResGroup118 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
1548 let Latency = 24;
1549 let NumMicroOps = 3;
1550 }
1551 def : InstRW<[SPRWriteResGroup118], (instregex "^MMX_CVT(T?)PD2PIrm$")>;
1553 def SPRWriteResGroup119 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
1554 let Latency = 8;
1555 let NumMicroOps = 2;
1556 }
1557 def : InstRW<[SPRWriteResGroup119], (instregex "^MMX_CVT(T?)PD2PIrr$",
1558 "^VCVT(T?)PH2(U?)DQZ(128|256)rr$",
1559 "^VCVTP(H2PS|S2PH)XZ256rr$")>;
1561 def SPRWriteResGroup120 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
1562 let Latency = 6;
1563 let NumMicroOps = 2;
1564 }
1565 def : InstRW<[SPRWriteResGroup120], (instregex "^VCVTP(H2PS|S2PH)XZ128rr$",
1566 "^VPERMWZ(128|256)rrk(z?)$",
1567 "^VPS(L|R)LWZ256rrk(z?)$",
1568 "^VPSRAWZ256rrk(z?)$")>;
1569 def : InstRW<[SPRWriteResGroup120], (instrs MMX_CVTPI2PDrr)>;
1571 def SPRWriteResGroup121 : SchedWriteRes<[SPRPort00, SPRPort00_01]> {
1572 let Latency = 7;
1573 let NumMicroOps = 2;
1574 }
1575 def : InstRW<[SPRWriteResGroup121], (instrs MMX_CVTPI2PSrr)>;
1577 def SPRWriteResGroup122 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
1578 let Latency = 13;
1579 let NumMicroOps = 2;
1580 }
1581 def : InstRW<[SPRWriteResGroup122], (instregex "^MMX_CVT(T?)PS2PIrm$")>;
1583 def SPRWriteResGroup123 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
1584 let Latency = 9;
1585 let NumMicroOps = 2;
1586 }
1587 def : InstRW<[SPRWriteResGroup123], (instregex "^MMX_CVT(T?)PS2PIrr$")>;
1589 def SPRWriteResGroup124 : SchedWriteRes<[SPRPort00, SPRPort04_09, SPRPort07_08]> {
1590 let ReleaseAtCycles = [2, 1, 1];
1591 let Latency = 12;
1592 let NumMicroOps = 4;
1593 }
1594 def : InstRW<[SPRWriteResGroup124], (instregex "^MMX_MASKMOVQ((64)?)$")>;
1596 def SPRWriteResGroup125 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
1597 let Latency = 18;
1598 let NumMicroOps = 2;
1599 }
1600 def : InstRW<[SPRWriteResGroup125], (instregex "^VMOV(W|SHZ)mr$")>;
1601 def : InstRW<[SPRWriteResGroup125], (instrs MMX_MOVD64mr)>;
1603 def SPRWriteResGroup126 : SchedWriteRes<[SPRPort02_03_10]> {
1604 let Latency = 8;
1605 }
1606 def : InstRW<[SPRWriteResGroup126], (instregex "^MMX_MOV(D|Q)64rm$",
1607 "^VBROADCAST(F|I)128rm$",
1608 "^VBROADCAST(F|I)32X(2|4)Z256rm$",
1609 "^VBROADCAST(F|I)32X(8|2)Zrm$",
1610 "^VBROADCAST(F|I)(32|64)X4Zrm$",
1611 "^VBROADCAST(F|I)64X2(Z|Z256)rm$",
1612 "^VBROADCASTS(DY|SZ)rm$",
1613 "^VBROADCASTS(D|S)Z256rm$",
1614 "^VBROADCASTS(DZ|SY)rm$",
1615 "^VMOV(D|SH|SL)DUP(Y|Z)rm$",
1616 "^VMOV(D|SH|SL)DUPZ256rm$",
1617 "^VPBROADCAST(DY|QZ)rm$",
1618 "^VPBROADCAST(D|Q)Z256rm$",
1619 "^VPBROADCAST(DZ|QY)rm$")>;
1620 def : InstRW<[SPRWriteResGroup126], (instrs MMX_MOVD64to64rm)>;
1622 def SPRWriteResGroup127 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_05]> {
1623 let Latency = 3;
1624 let NumMicroOps = 2;
1625 }
1626 def : InstRW<[SPRWriteResGroup127], (instregex "^MMX_MOV(DQ|FR64)2Qrr$")>;
1628 def SPRWriteResGroup128 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
1629 let Latency = 3;
1630 let NumMicroOps = 2;
1631 }
1632 def : InstRW<[SPRWriteResGroup128], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;
1634 def SPRWriteResGroup129 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> {
1635 let ReleaseAtCycles = [1, 2];
1636 let Latency = 12;
1637 let NumMicroOps = 3;
1638 }
1639 def : InstRW<[SPRWriteResGroup129, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|WB)rm$")>;
1640 def : InstRW<[SPRWriteResGroup129, ReadAfterVecLd], (instrs MMX_PACKUSWBrm)>;
1642 def SPRWriteResGroup130 : SchedWriteRes<[SPRPort05]> {
1643 let ReleaseAtCycles = [2];
1644 let Latency = 4;
1645 let NumMicroOps = 2;
1646 }
1647 def : InstRW<[SPRWriteResGroup130], (instregex "^MMX_PACKSS(DW|WB)rr$",
1648 "^VPMOV(D|Q|W|SQ|SW)BZrr$",
1649 "^VPMOV((S|US)?)(D|Q)WZrr$",
1650 "^VPMOV(U?)S(DB|QD)Zrr$",
1651 "^VPMOV(U?)SQDZrrk(z?)$",
1652 "^VPMOVUS(Q|W)BZrr$")>;
1653 def : InstRW<[SPRWriteResGroup130], (instrs MMX_PACKUSWBrr)>;
1654 def : InstRW<[SPRWriteResGroup130, ReadDefault, ReadInt2Fpu], (instrs MMX_PINSRWrri)>;
1656 def SPRWriteResGroup131 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_10]> {
1657 let Latency = 9;
1658 let NumMicroOps = 2;
1659 }
1660 def : InstRW<[SPRWriteResGroup131], (instregex "^VBROADCAST(F|I)32X(8|2)Zrmk(z?)$",
1661 "^VBROADCAST(F|I)(32|64)X4Zrmk(z?)$",
1662 "^VBROADCAST(F|I)64X2Zrmk(z?)$",
1663 "^VBROADCASTS(D|S)Zrmk(z?)$",
1664 "^VMOV(A|U)P(D|S)Zrmk(z?)$",
1665 "^VMOV(D|SH|SL)DUPZrmk(z?)$",
1666 "^VMOVDQ(A|U)(32|64)Zrmk(z?)$",
1667 "^VPBROADCAST(D|Q)Zrmk(z?)$")>;
1668 def : InstRW<[SPRWriteResGroup131, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>;
1669 def : InstRW<[SPRWriteResGroup131, ReadAfterVecYLd], (instregex "^VINSERT(F|I)(32|64)X4Zrmi((k|kz)?)$",
1670 "^VINSERT(F|I)(32X8|64X2)Zrmi((k|kz)?)$",
1671 "^VP(ADD|SUB)(B|D|Q|W)Zrm$",
1672 "^VP(ADD|SUB)(D|Q)Zrm(b|k|kz)$",
1673 "^VP(ADD|SUB)(D|Q)Zrmbk(z?)$",
1674 "^VPTERNLOG(D|Q)Zrm(bi|ik)$",
1675 "^VPTERNLOG(D|Q)Zrmbik(z?)$",
1676 "^VPTERNLOG(D|Q)Zrmi((kz)?)$")>;
1678 def SPRWriteResGroup132 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
1679 let ReleaseAtCycles = [1, 1, 2];
1680 let Latency = 11;
1681 let NumMicroOps = 4;
1682 }
1683 def : InstRW<[SPRWriteResGroup132, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;
1685 def SPRWriteResGroup133 : SchedWriteRes<[SPRPort00, SPRPort05]> {
1686 let ReleaseAtCycles = [1, 2];
1687 let Latency = 3;
1688 let NumMicroOps = 3;
1689 }
1690 def : InstRW<[SPRWriteResGroup133], (instregex "^MMX_PH(ADD|SUB)SWrr$")>;
1692 def SPRWriteResGroup134 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> {
1693 let Latency = 9;
1694 let NumMicroOps = 2;
1695 }
1696 def : InstRW<[SPRWriteResGroup134], (instregex "^VPBROADCAST(BY|WZ)rm$",
1697 "^VPBROADCAST(B|W)Z256rm$",
1698 "^VPBROADCAST(BZ|WY)rm$")>;
1699 def : InstRW<[SPRWriteResGroup134, ReadAfterLd], (instrs MMX_PINSRWrmi)>;
1700 def : InstRW<[SPRWriteResGroup134, ReadAfterVecXLd], (instregex "^VFPCLASSP(D|S)Z128mi$")>;
1701 def : InstRW<[SPRWriteResGroup134, ReadAfterVecLd], (instregex "^VFPCLASSS(D|H|S)Zmi$")>;
1702 def : InstRW<[SPRWriteResGroup134, ReadAfterVecYLd], (instregex "^VPALIGNR(Y|Z256)rmi$")>;
1703 def : InstRW<[SPRWriteResGroup134, ReadAfterVecYLd], (instrs VPSHUFBZrm)>;
1705 def SPRWriteResGroup135 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> {
1706 let Latency = 5;
1707 let NumMicroOps = 2;
1708 }
1709 def : InstRW<[SPRWriteResGroup135], (instregex "^MOV16ao(16|32|64)$")>;
1711 def SPRWriteResGroup136 : SchedWriteRes<[SPRPort01, SPRPort04_09, SPRPort07_08]> {
1712 let Latency = 12;
1713 let NumMicroOps = 3;
1714 }
1715 def : InstRW<[SPRWriteResGroup136], (instregex "^PUSH(F|G)S(16|32)$")>;
1716 def : InstRW<[SPRWriteResGroup136], (instrs MOV16ms,
1717 MOVBE32mr)>;
1719 def SPRWriteResGroup137 : SchedWriteRes<[SPRPort00_01_05_06_11]>;
1720 def : InstRW<[SPRWriteResGroup137], (instregex "^MOV(8|16|32|64)ri$",
1721 "^MOV(8|16|32)ri_alt$",
1722 "^MOV(8|16)rr((_REV)?)$")>;
1723 def : InstRW<[SPRWriteResGroup137], (instrs MOV64ri32,
1724 MOV8rr_NOREX)>;
1726 def SPRWriteResGroup138 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort01]> {
1727 let NumMicroOps = 2;
1728 }
1729 def : InstRW<[SPRWriteResGroup138], (instregex "^MOV(16|32|64)rs$",
1730 "^S(TR|LDT)16r$")>;
1732 def SPRWriteResGroup139 : SchedWriteRes<[SPRPort02_03_10]>;
1733 def : InstRW<[SPRWriteResGroup139], (instregex "^MOV32ao(16|32|64)$")>;
1734 def : InstRW<[SPRWriteResGroup139], (instrs MOV64ao64)>;
1736 def SPRWriteResGroup140 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> {
1737 let NumMicroOps = 3;
1738 }
1739 def : InstRW<[SPRWriteResGroup140], (instregex "^MOV(8|32)o(16|32)a$",
1740 "^MOV(8|32|64)o64a$")>;
1742 def SPRWriteResGroup141 : SchedWriteRes<[SPRPort00_01_05_06_11]> {
1743 let Latency = 0;
1744 }
1745 def : InstRW<[SPRWriteResGroup141], (instregex "^MOV32rr((_REV)?)$",
1746 "^MOVZX(32|64)rr8$")>;
1747 def : InstRW<[SPRWriteResGroup141], (instrs MOVZX32rr8_NOREX)>;
1749 def SPRWriteResGroup142 : SchedWriteRes<[SPRPort02_03_10]> {
1750 let Latency = 5;
1751 }
1752 def : InstRW<[SPRWriteResGroup142], (instrs MOV64ao32)>;
1754 def SPRWriteResGroup143 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1755 let ReleaseAtCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2];
1756 let Latency = 217;
1757 let NumMicroOps = 48;
1758 }
1759 def : InstRW<[SPRWriteResGroup143], (instrs MOV64dr)>;
1761 def SPRWriteResGroup144 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
1762 let Latency = 12;
1763 let NumMicroOps = 2;
1764 }
1765 def : InstRW<[SPRWriteResGroup144], (instrs MOV64o32a)>;
1767 def SPRWriteResGroup145 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort05]> {
1768 let Latency = SapphireRapidsModel.MaxLatency;
1769 let NumMicroOps = 3;
1770 }
1771 def : InstRW<[SPRWriteResGroup145], (instrs MOV64rc)>;
1773 def SPRWriteResGroup146 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort05]> {
1774 let ReleaseAtCycles = [3, 4, 8, 4, 2, 3];
1775 let Latency = 181;
1776 let NumMicroOps = 24;
1777 }
1778 def : InstRW<[SPRWriteResGroup146], (instrs MOV64rd)>;
1780 def SPRWriteResGroup147 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> {
1781 let NumMicroOps = 2;
1782 }
1783 def : InstRW<[SPRWriteResGroup147], (instregex "^MOV8ao(16|32|64)$")>;
1785 def SPRWriteResGroup148 : SchedWriteRes<[SPRPort00_06, SPRPort04_09, SPRPort07_08]> {
1786 let Latency = 12;
1787 let NumMicroOps = 3;
1788 }
1789 def : InstRW<[SPRWriteResGroup148], (instrs MOVBE16mr)>;
1791 def SPRWriteResGroup149 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort02_03_10]> {
1792 let Latency = 7;
1793 let NumMicroOps = 3;
1794 }
1795 def : InstRW<[SPRWriteResGroup149], (instrs MOVBE16rm)>;
1797 def SPRWriteResGroup150 : SchedWriteRes<[SPRPort01, SPRPort02_03_10]> {
1798 let Latency = 6;
1799 let NumMicroOps = 2;
1800 }
1801 def : InstRW<[SPRWriteResGroup150], (instrs MOVBE32rm)>;
1803 def SPRWriteResGroup151 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort07_08]> {
1804 let Latency = 12;
1805 let NumMicroOps = 4;
1806 }
1807 def : InstRW<[SPRWriteResGroup151], (instrs MOVBE64mr,
1808 PUSHF16,
1809 SLDT16m,
1810 STRm)>;
1812 def SPRWriteResGroup152 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort02_03_10]> {
1813 let Latency = 7;
1814 let NumMicroOps = 3;
1815 }
1816 def : InstRW<[SPRWriteResGroup152], (instrs MOVBE64rm)>;
1818 def SPRWriteResGroup153 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
1819 let NumMicroOps = 4;
1820 }
1821 def : InstRW<[SPRWriteResGroup153], (instregex "^MOVDIR64B(16|32|64)$")>;
1823 def SPRWriteResGroup154 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
1824 let Latency = 511;
1825 let NumMicroOps = 2;
1826 }
1827 def : InstRW<[SPRWriteResGroup154], (instrs MOVDIRI32)>;
1829 def SPRWriteResGroup155 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
1830 let Latency = 514;
1831 let NumMicroOps = 2;
1832 }
1833 def : InstRW<[SPRWriteResGroup155], (instrs MOVDIRI64)>;
1835 def SPRWriteResGroup156 : SchedWriteRes<[SPRPort01_05, SPRPort02_03_10]> {
1836 let Latency = 8;
1837 let NumMicroOps = 2;
1838 }
1839 def : InstRW<[SPRWriteResGroup156, ReadAfterVecXLd], (instregex "^(V?)MOVLP(D|S)rm$",
1840 "^(V?)SHUFP(D|S)rmi$",
1841 "^VMOVLP(D|S)Z128rm$",
1842 "^VSHUFP(D|S)Z128rm(bi|ik)$",
1843 "^VSHUFP(D|S)Z128rmbik(z?)$",
1844 "^VSHUFP(D|S)Z128rmi((kz)?)$")>;
1846 def SPRWriteResGroup157 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
1847 let Latency = 512;
1848 let NumMicroOps = 2;
1849 }
1850 def : InstRW<[SPRWriteResGroup157], (instrs MOVNTDQmr)>;
1852 def SPRWriteResGroup158 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
1853 let Latency = 518;
1854 let NumMicroOps = 2;
1855 }
1856 def : InstRW<[SPRWriteResGroup158], (instrs MOVNTImr)>;
1858 def SPRWriteResGroup159 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
1859 let ReleaseAtCycles = [4, 1, 1, 1];
1860 let Latency = 8;
1861 let NumMicroOps = 7;
1862 }
1863 def : InstRW<[SPRWriteResGroup159], (instrs MOVSB)>;
1865 def SPRWriteResGroup160 : SchedWriteRes<[SPRPort00_01_05]>;
1866 def : InstRW<[SPRWriteResGroup160], (instregex "^(V?)MOVS(D|S)rr((_REV)?)$",
1867 "^(V?)P(ADD|SUB)(B|D|Q|W)rr$",
1868 "^VMOV(A|U)P(D|S)Z(128|256)rrk(z?)((_REV)?)$",
1869 "^VMOVDQ(A|U)(32|64)Z128rrk(z?)((_REV)?)$",
1870 "^VMOVS(D|H|S)Zrr((_REV)?)$",
1871 "^VMOVS(D|S)Zrrk(z?)((_REV)?)$",
1872 "^VP(ADD|SUB)(B|D|Q|W)Yrr$",
1873 "^VP(ADD|SUB)(B|D|Q|W)Z(128|256)rr$",
1874 "^VP(ADD|SUB)(D|Q)Z(128|256)rrk(z?)$",
1875 "^VPMOVM2(D|Q)Z128rk$",
1876 "^VPTERNLOG(D|Q)Z(128|256)rri((k|kz)?)$")>;
1877 def : InstRW<[SPRWriteResGroup160], (instrs VPBLENDDrri)>;
1879 def SPRWriteResGroup161 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
1880 let ReleaseAtCycles = [4, 1, 1, 1];
1881 let Latency = 7;
1882 let NumMicroOps = 7;
1883 }
1884 def : InstRW<[SPRWriteResGroup161], (instregex "^MOVS(L|Q|W)$")>;
1886 def SPRWriteResGroup162 : SchedWriteRes<[SPRPort02_03_10]> {
1887 let Latency = 6;
1888 }
1889 def : InstRW<[SPRWriteResGroup162], (instregex "^MOVSX(16|32|64)rm(16|32)$",
1890 "^MOVSX(32|64)rm8$")>;
1891 def : InstRW<[SPRWriteResGroup162], (instrs MOVSX32rm8_NOREX)>;
1893 def SPRWriteResGroup163 : SchedWriteRes<[SPRPort01_05_11, SPRPort02_03_10]> {
1894 let Latency = 6;
1895 let NumMicroOps = 2;
1896 }
1897 def : InstRW<[SPRWriteResGroup163], (instrs MOVSX16rm8)>;
1899 def SPRWriteResGroup164 : SchedWriteRes<[SPRPort01_05_11]>;
1900 def : InstRW<[SPRWriteResGroup164], (instregex "^MOVSX(16|32|64)rr(8|16|32)$")>;
1901 def : InstRW<[SPRWriteResGroup164], (instrs MOVSX32rr8_NOREX)>;
1903 def SPRWriteResGroup165 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
1904 let Latency = 11;
1905 let NumMicroOps = 2;
1906 }
1907 def : InstRW<[SPRWriteResGroup165], (instregex "^MUL_F(32|64)m$",
1908 "^VPABS(B|W)Zrmk(z?)$",
1909 "^VPS(L|R)LWZmik(z?)$",
1910 "^VPSRAWZmik(z?)$")>;
1911 def : InstRW<[SPRWriteResGroup165, ReadAfterVecYLd], (instregex "^VP(ADD|SUB)(U?)S(B|W)Zrmk(z?)$",
1912 "^VPAVG(B|W)Zrmk(z?)$",
1913 "^VPM(AX|IN)(SB|UW)Zrmk(z?)$",
1914 "^VPM(AX|IN)(SW|UB)Zrmk(z?)$",
1915 "^VPSH(L|R)DVWZmk(z?)$",
1916 "^VPS(L|R)L(V?)WZrmk(z?)$",
1917 "^VPSRA(V?)WZrmk(z?)$")>;
1919 def SPRWriteResGroup166 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
1920 let Latency = 14;
1921 let NumMicroOps = 3;
1922 }
1923 def : InstRW<[SPRWriteResGroup166], (instregex "^MUL_FI(16|32)m$")>;
1925 def SPRWriteResGroup167 : SchedWriteRes<[SPRPort00]> {
1926 let Latency = 4;
1927 }
1928 def : InstRW<[SPRWriteResGroup167], (instregex "^MUL_F(P?)rST0$",
1929 "^V(U?)COMISHZrr(b?)$",
1930 "^V(U?)COMISHZrr_Int$",
1931 "^VCVT(T?)PD2(U?)QQZrr((b|k|bk|kz)?)$",
1932 "^VCVT(T?)PD2(U?)QQZrrbkz$",
1933 "^VCVT(T?)PS2(U?)DQZrr((b|k|bk|kz)?)$",
1934 "^VCVT(T?)PS2(U?)DQZrrbkz$",
1935 "^VM(AX|IN)(C?)PSZrr((k|kz)?)$",
1936 "^VM(AX|IN)PSZrrb((k|kz)?)$",
1937 "^VPLZCNT(D|Q)Zrr((k|kz)?)$",
1938 "^VPMADD52(H|L)UQZr((k|kz)?)$")>;
1939 def : InstRW<[SPRWriteResGroup167], (instrs MUL_FST0r)>;
1941 def SPRWriteResGroup168 : SchedWriteRes<[SPRPort00_01_05_06, SPRPort05, SPRPort06]> {
1942 let ReleaseAtCycles = [7, 1, 2];
1943 let Latency = 20;
1944 let NumMicroOps = 10;
1945 }
1946 def : InstRW<[SPRWriteResGroup168], (instrs MWAITrr)>;
1948 def SPRWriteResGroup169 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1949 let ReleaseAtCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1];
1950 let Latency = 35;
1951 let NumMicroOps = 79;
1952 }
1953 def : InstRW<[SPRWriteResGroup169], (instrs OUT16ir)>;
1955 def SPRWriteResGroup170 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1956 let ReleaseAtCycles = [6, 6, 27, 15, 7, 1, 16, 1];
1957 let Latency = 35;
1958 let NumMicroOps = 79;
1959 }
1960 def : InstRW<[SPRWriteResGroup170], (instrs OUT16rr)>;
1962 def SPRWriteResGroup171 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1963 let ReleaseAtCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1];
1964 let Latency = 35;
1965 let NumMicroOps = 85;
1966 }
1967 def : InstRW<[SPRWriteResGroup171], (instrs OUT32ir)>;
1969 def SPRWriteResGroup172 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1970 let ReleaseAtCycles = [6, 6, 29, 15, 9, 1, 18, 1];
1971 let Latency = 35;
1972 let NumMicroOps = 85;
1973 }
1974 def : InstRW<[SPRWriteResGroup172], (instrs OUT32rr)>;
1976 def SPRWriteResGroup173 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1977 let ReleaseAtCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1];
1978 let Latency = 35;
1979 let NumMicroOps = 73;
1980 }
1981 def : InstRW<[SPRWriteResGroup173], (instrs OUT8ir)>;
1983 def SPRWriteResGroup174 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1984 let ReleaseAtCycles = [5, 5, 26, 15, 5, 1, 15, 1];
1985 let Latency = 35;
1986 let NumMicroOps = 73;
1987 }
1988 def : InstRW<[SPRWriteResGroup174], (instrs OUT8rr)>;
1990 def SPRWriteResGroup175 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1991 let ReleaseAtCycles = [7, 6, 25, 16, 7, 1, 17, 1];
1992 let Latency = SapphireRapidsModel.MaxLatency;
1993 let NumMicroOps = 80;
1994 }
1995 def : InstRW<[SPRWriteResGroup175], (instrs OUTSB)>;
1997 def SPRWriteResGroup176 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1998 let ReleaseAtCycles = [7, 6, 28, 16, 10, 1, 20, 1];
1999 let Latency = SapphireRapidsModel.MaxLatency;
2000 let NumMicroOps = 89;
2001 }
2002 def : InstRW<[SPRWriteResGroup176], (instrs OUTSL)>;
2004 def SPRWriteResGroup177 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
2005 let ReleaseAtCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1];
2006 let Latency = SapphireRapidsModel.MaxLatency;
2007 let NumMicroOps = 83;
2008 }
2009 def : InstRW<[SPRWriteResGroup177], (instrs OUTSW)>;
2011 def SPRWriteResGroup178 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10]> {
2012 let Latency = 8;
2013 let NumMicroOps = 2;
2014 }
2015 def : InstRW<[SPRWriteResGroup178], (instregex "^VBROADCASTI32X2Z128rmk(z?)$",
2016 "^VBROADCASTSSZ128rmk(z?)$",
2017 "^VMOV(A|U)P(D|S)Z128rmk(z?)$",
2018 "^VMOV(D|SH|SL)DUPZ128rmk(z?)$",
2019 "^VMOVDQ(A|U)(32|64)Z128rmk(z?)$",
2020 "^VMOVS(D|S)Zrmk(z?)$",
2021 "^VPBROADCAST(D|Q)Z128rmk(z?)$")>;
2022 def : InstRW<[SPRWriteResGroup178, ReadAfterVecXLd], (instregex "^(V?)P(ADD|SUB)(B|D|Q|W)rm$",
2023 "^VP(ADD|SUB)(B|D|Q|W)Z128rm$",
2024 "^VP(ADD|SUB)(D|Q)Z128rm(b|k|kz)$",
2025 "^VP(ADD|SUB)(D|Q)Z128rmbk(z?)$",
2026 "^VPTERNLOG(D|Q)Z128rm(bi|ik)$",
2027 "^VPTERNLOG(D|Q)Z128rmbik(z?)$",
2028 "^VPTERNLOG(D|Q)Z128rmi((kz)?)$")>;
2029 def : InstRW<[SPRWriteResGroup178, ReadAfterVecXLd], (instrs VPBLENDDrmi)>;
2031 def SPRWriteResGroup179 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> {
2032 let Latency = 8;
2033 let NumMicroOps = 2;
2034 }
2035 def : InstRW<[SPRWriteResGroup179], (instregex "^VPBROADCAST(B|W)((Z128)?)rm$")>;
2036 def : InstRW<[SPRWriteResGroup179, ReadAfterVecXLd], (instregex "^(V?)PALIGNRrmi$",
2037 "^VALIGN(D|Q)Z128rm(bi|ik)$",
2038 "^VALIGN(D|Q)Z128rmbik(z?)$",
2039 "^VALIGN(D|Q)Z128rmi((kz)?)$")>;
2040 def : InstRW<[SPRWriteResGroup179, ReadAfterVecXLd], (instrs VPALIGNRZ128rmi)>;
2042 def SPRWriteResGroup180 : SchedWriteRes<[SPRPort00_06, SPRPort05]> {
2043 let Latency = 140;
2044 let NumMicroOps = 2;
2045 }
2046 def : InstRW<[SPRWriteResGroup180], (instrs PAUSE)>;
2048 def SPRWriteResGroup181 : SchedWriteRes<[SPRPort01, SPRPort02_03_10]> {
2049 let Latency = 8;
2050 let NumMicroOps = 2;
2051 }
2052 def : InstRW<[SPRWriteResGroup181, ReadAfterLd], (instregex "^P(DEP|EXT)(32|64)rm$")>;
2054 def SPRWriteResGroup182 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort07_08]> {
2055 let Latency = 12;
2056 let NumMicroOps = 3;
2057 }
2058 def : InstRW<[SPRWriteResGroup182], (instregex "^(V?)PEXTR(D|Q)mri$",
2059 "^VPEXTR(D|Q)Zmri$",
2060 "^VPMOVQDZ128mr(k?)$")>;
2062 def SPRWriteResGroup183 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10]> {
2063 let ReleaseAtCycles = [1, 2, 1];
2064 let Latency = 9;
2065 let NumMicroOps = 4;
2066 }
2067 def : InstRW<[SPRWriteResGroup183, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;
2069 def SPRWriteResGroup184 : SchedWriteRes<[SPRPort00_01, SPRPort01_05]> {
2070 let ReleaseAtCycles = [1, 2];
2071 let Latency = 2;
2072 let NumMicroOps = 3;
2073 }
2074 def : InstRW<[SPRWriteResGroup184], (instregex "^(V?)PH(ADD|SUB)SWrr$",
2075 "^VPH(ADD|SUB)SWYrr$")>;
2077 def SPRWriteResGroup185 : SchedWriteRes<[SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
2078 let Latency = 12;
2079 let NumMicroOps = 3;
2080 }
2081 def : InstRW<[SPRWriteResGroup185], (instregex "^POP(16|32|64)rmm$",
2082 "^PUSH(16|32)rmm$")>;
2084 def SPRWriteResGroup186 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10]> {
2085 let ReleaseAtCycles = [6, 2, 1, 1];
2086 let Latency = 5;
2087 let NumMicroOps = 10;
2088 }
2089 def : InstRW<[SPRWriteResGroup186], (instrs POPF16)>;
2091 def SPRWriteResGroup187 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort02_03_10]> {
2092 let ReleaseAtCycles = [2, 1, 1];
2093 let Latency = 5;
2094 let NumMicroOps = 7;
2095 }
2096 def : InstRW<[SPRWriteResGroup187], (instrs POPF64)>;
2098 def SPRWriteResGroup188 : SchedWriteRes<[SPRPort02_03_10]> {
2099 let Latency = 0;
2100 }
2101 def : InstRW<[SPRWriteResGroup188], (instregex "^PREFETCHT(0|1|2)$")>;
2102 def : InstRW<[SPRWriteResGroup188], (instrs PREFETCHNTA)>;
2104 def SPRWriteResGroup189 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10, SPRPort06]> {
2105 let ReleaseAtCycles = [1, 1, 2];
2106 let Latency = SapphireRapidsModel.MaxLatency;
2107 let NumMicroOps = 4;
2108 }
2109 def : InstRW<[SPRWriteResGroup189], (instregex "^PTWRITE((64)?)m$")>;
2111 def SPRWriteResGroup190 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort06]> {
2112 let ReleaseAtCycles = [1, 2];
2113 let Latency = SapphireRapidsModel.MaxLatency;
2114 let NumMicroOps = 3;
2115 }
2116 def : InstRW<[SPRWriteResGroup190], (instrs PTWRITE64r)>;
2118 def SPRWriteResGroup191 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort06]> {
2119 let ReleaseAtCycles = [2, 2];
2120 let Latency = SapphireRapidsModel.MaxLatency;
2121 let NumMicroOps = 4;
2122 }
2123 def : InstRW<[SPRWriteResGroup191], (instrs PTWRITEr)>;
2125 def SPRWriteResGroup192 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
2126 let NumMicroOps = 2;
2127 }
2128 def : InstRW<[SPRWriteResGroup192], (instregex "^PUSH64r((mr)?)$")>;
2130 def SPRWriteResGroup193 : SchedWriteRes<[SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
2131 let NumMicroOps = 3;
2132 }
2133 def : InstRW<[SPRWriteResGroup193], (instrs PUSH64rmm)>;
2135 def SPRWriteResGroup194 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort07_08]> {
2136 let Latency = 4;
2137 let NumMicroOps = 4;
2138 }
2139 def : InstRW<[SPRWriteResGroup194], (instrs PUSHF64)>;
2141 def SPRWriteResGroup195 : SchedWriteRes<[SPRPort01, SPRPort04_09, SPRPort07_08]> {
2142 let NumMicroOps = 3;
2143 }
2144 def : InstRW<[SPRWriteResGroup195], (instregex "^PUSH(F|G)S64$")>;
2146 def SPRWriteResGroup196 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> {
2147 let ReleaseAtCycles = [2, 3, 2];
2148 let Latency = 8;
2149 let NumMicroOps = 7;
2150 }
2151 def : InstRW<[SPRWriteResGroup196], (instregex "^RC(L|R)(16|32|64)rCL$")>;
2153 def SPRWriteResGroup197 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> {
2154 let ReleaseAtCycles = [1, 2];
2155 let Latency = 13;
2156 let NumMicroOps = 3;
2157 }
2158 def : InstRW<[SPRWriteResGroup197, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;
2160 def SPRWriteResGroup198 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> {
2161 let ReleaseAtCycles = [1, 5, 2];
2162 let Latency = 20;
2163 let NumMicroOps = 8;
2164 }
2165 def : InstRW<[SPRWriteResGroup198, WriteRMW], (instrs RCL8mCL)>;
2167 def SPRWriteResGroup199 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> {
2168 let ReleaseAtCycles = [2, 5, 2];
2169 let Latency = 7;
2170 let NumMicroOps = 9;
2171 }
2172 def : InstRW<[SPRWriteResGroup199], (instrs RCL8rCL)>;
2174 def SPRWriteResGroup200 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> {
2175 let ReleaseAtCycles = [2, 4, 3];
2176 let Latency = 20;
2177 let NumMicroOps = 9;
2178 }
2179 def : InstRW<[SPRWriteResGroup200, WriteRMW], (instrs RCR8mCL)>;
2181 def SPRWriteResGroup201 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> {
2182 let ReleaseAtCycles = [3, 4, 3];
2183 let Latency = 9;
2184 let NumMicroOps = 10;
2185 }
2186 def : InstRW<[SPRWriteResGroup201], (instrs RCR8rCL)>;
2188 def SPRWriteResGroup202 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort01_05_11, SPRPort05]> {
2189 let ReleaseAtCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2];
2190 let Latency = SapphireRapidsModel.MaxLatency;
2191 let NumMicroOps = 54;
2192 }
2193 def : InstRW<[SPRWriteResGroup202], (instrs RDMSR)>;
2195 def SPRWriteResGroup203 : SchedWriteRes<[SPRPort01]> {
2196 let Latency = SapphireRapidsModel.MaxLatency;
2197 }
2198 def : InstRW<[SPRWriteResGroup203], (instrs RDPID64)>;
2200 def SPRWriteResGroup204 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> {
2201 let Latency = SapphireRapidsModel.MaxLatency;
2202 let NumMicroOps = 3;
2203 }
2204 def : InstRW<[SPRWriteResGroup204], (instrs RDPKRUr)>;
2206 def SPRWriteResGroup205 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort05]> {
2207 let ReleaseAtCycles = [9, 6, 2, 1];
2208 let Latency = SapphireRapidsModel.MaxLatency;
2209 let NumMicroOps = 18;
2210 }
2211 def : InstRW<[SPRWriteResGroup205], (instrs RDPMC)>;
2213 def SPRWriteResGroup206 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
2214 let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2];
2215 let Latency = 1386;
2216 let NumMicroOps = 25;
2217 }
2218 def : InstRW<[SPRWriteResGroup206], (instrs RDRAND16r)>;
2220 def SPRWriteResGroup207 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
2221 let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2];
2222 let Latency = SapphireRapidsModel.MaxLatency;
2223 let NumMicroOps = 25;
2224 }
2225 def : InstRW<[SPRWriteResGroup207], (instregex "^RDRAND(32|64)r$")>;
2227 def SPRWriteResGroup208 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05]> {
2228 let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4];
2229 let Latency = 1381;
2230 let NumMicroOps = 25;
2231 }
2232 def : InstRW<[SPRWriteResGroup208], (instrs RDSEED16r)>;
2234 def SPRWriteResGroup209 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05]> {
2235 let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4];
2236 let Latency = SapphireRapidsModel.MaxLatency;
2237 let NumMicroOps = 25;
2238 }
2239 def : InstRW<[SPRWriteResGroup209], (instregex "^RDSEED(32|64)r$")>;
2241 def SPRWriteResGroup210 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort05]> {
2242 let ReleaseAtCycles = [5, 6, 3, 1];
2243 let Latency = 18;
2244 let NumMicroOps = 15;
2245 }
2246 def : InstRW<[SPRWriteResGroup210], (instrs RDTSC)>;
2248 def SPRWriteResGroup211 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort05]> {
2249 let ReleaseAtCycles = [2, 2, 1, 2, 7, 4, 3];
2250 let Latency = 42;
2251 let NumMicroOps = 21;
2252 }
2253 def : InstRW<[SPRWriteResGroup211], (instrs RDTSCP)>;
2255 def SPRWriteResGroup212 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_10]> {
2256 let Latency = 7;
2257 let NumMicroOps = 2;
2258 }
2259 def : InstRW<[SPRWriteResGroup212], (instrs RET64)>;
2261 def SPRWriteResGroup213 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_10]> {
2262 let ReleaseAtCycles = [2, 1];
2263 let Latency = 6;
2264 let NumMicroOps = 3;
2265 }
2266 def : InstRW<[SPRWriteResGroup213], (instregex "^RETI(16|32|64)$")>;
2268 def SPRWriteResGroup214 : SchedWriteRes<[]>;
2269 def : InstRW<[SPRWriteResGroup214], (instrs REX64_PREFIX)>;
2271 def SPRWriteResGroup215 : SchedWriteRes<[SPRPort00_06]> {
2272 let ReleaseAtCycles = [2];
2273 let Latency = 12;
2274 let NumMicroOps = 2;
2275 }
2276 def : InstRW<[SPRWriteResGroup215, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>;
2278 def SPRWriteResGroup216 : SchedWriteRes<[SPRPort00_06]> {
2279 let ReleaseAtCycles = [2];
2280 let NumMicroOps = 2;
2281 }
2282 def : InstRW<[SPRWriteResGroup216], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>;
2284 def SPRWriteResGroup217 : SchedWriteRes<[SPRPort00_06]> {
2285 let ReleaseAtCycles = [2];
2286 let Latency = 13;
2287 let NumMicroOps = 2;
2288 }
2289 def : InstRW<[SPRWriteResGroup217, WriteRMW], (instregex "^RO(L|R)8m(1|i)$",
2290 "^(RO|SH)L8mCL$",
2291 "^(RO|SA|SH)R8mCL$")>;
2293 def SPRWriteResGroup218 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> {
2294 let ReleaseAtCycles = [2, 1];
2295 let Latency = 15;
2296 let NumMicroOps = 3;
2297 }
2298 def : InstRW<[SPRWriteResGroup218], (instregex "^(V?)ROUNDP(D|S)mi$")>;
2299 def : InstRW<[SPRWriteResGroup218, ReadAfterVecXLd], (instregex "^(V?)ROUNDS(D|S)mi((_Int)?)$",
2300 "^VRNDSCALEP(D|S)Z128rm(bi|ik)$",
2301 "^VRNDSCALEP(D|S)Z128rmbik(z?)$",
2302 "^VRNDSCALEP(D|S)Z128rmi((kz)?)$",
2303 "^VRNDSCALES(D|S)Zrmi$",
2304 "^VRNDSCALES(D|S)Zrmi((k|kz)?)_Int$")>;
2306 def SPRWriteResGroup219 : SchedWriteRes<[SPRPort00_01]> {
2307 let ReleaseAtCycles = [2];
2308 let Latency = 8;
2309 let NumMicroOps = 2;
2310 }
2311 def : InstRW<[SPRWriteResGroup219], (instregex "^(V?)ROUND(PD|SS)ri$",
2312 "^(V?)ROUND(PS|SD)ri$",
2313 "^(V?)ROUNDS(D|S)ri_Int$",
2314 "^VRNDSCALEP(D|S)Z(128|256)rri((k|kz)?)$",
2315 "^VRNDSCALES(D|S)Zrri$",
2316 "^VRNDSCALES(D|S)Zrri(b?)((k|kz)?)_Int$",
2317 "^VROUNDP(D|S)Yri$")>;
2319 def SPRWriteResGroup220 : SchedWriteRes<[SPRPort00_06]> {
2320 let ReleaseAtCycles = [2];
2321 let Latency = 4;
2322 let NumMicroOps = 2;
2323 }
2324 def : InstRW<[SPRWriteResGroup220], (instrs SAHF)>;
2326 def SPRWriteResGroup221 : SchedWriteRes<[SPRPort00_06]> {
2327 let Latency = 13;
2328 }
2329 def : InstRW<[SPRWriteResGroup221, WriteRMW], (instregex "^S(A|H)R8m(1|i)$",
2330 "^SHL8m(1|i)$")>;
2332 def SPRWriteResGroup222 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_10]> {
2333 let Latency = 8;
2334 let NumMicroOps = 2;
2335 }
2336 def : InstRW<[SPRWriteResGroup222, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^S(A|H)RX(32|64)rm$",
2337 "^SHLX(32|64)rm$")>;
2339 def SPRWriteResGroup223 : SchedWriteRes<[SPRPort00_06]> {
2340 let Latency = 3;
2341 }
2342 def : InstRW<[SPRWriteResGroup223], (instregex "^S(A|H)RX(32|64)rr$",
2343 "^SHLX(32|64)rr$")>;
2345 def SPRWriteResGroup224 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort07_08]> {
2346 let ReleaseAtCycles = [2, 2, 1, 1, 1];
2347 let Latency = SapphireRapidsModel.MaxLatency;
2348 let NumMicroOps = 7;
2349 }
2350 def : InstRW<[SPRWriteResGroup224], (instrs SERIALIZE)>;
2352 def SPRWriteResGroup225 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
2353 let Latency = 2;
2354 let NumMicroOps = 2;
2355 }
2356 def : InstRW<[SPRWriteResGroup225], (instrs SFENCE)>;
2358 def SPRWriteResGroup226 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort01, SPRPort04_09, SPRPort07_08]> {
2359 let ReleaseAtCycles = [1, 2, 2, 2];
2360 let Latency = 21;
2361 let NumMicroOps = 7;
2362 }
2363 def : InstRW<[SPRWriteResGroup226], (instregex "^S(G|I)DT64m$")>;
2365 def SPRWriteResGroup227 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> {
2366 let Latency = 9;
2367 let NumMicroOps = 3;
2368 }
2369 def : InstRW<[SPRWriteResGroup227, ReadAfterVecXLd], (instrs SHA1MSG1rm)>;
2371 def SPRWriteResGroup228 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
2372 let Latency = 2;
2373 let NumMicroOps = 2;
2374 }
2375 def : InstRW<[SPRWriteResGroup228], (instrs SHA1MSG1rr)>;
2377 def SPRWriteResGroup229 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort01_05, SPRPort02_03_10]> {
2378 let ReleaseAtCycles = [2, 2, 1, 2, 1];
2379 let Latency = 13;
2380 let NumMicroOps = 8;
2381 }
2382 def : InstRW<[SPRWriteResGroup229, ReadAfterVecXLd], (instrs SHA1MSG2rm)>;
2384 def SPRWriteResGroup230 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort01_05]> {
2385 let ReleaseAtCycles = [2, 2, 1, 2];
2386 let Latency = 6;
2387 let NumMicroOps = 7;
2388 }
2389 def : InstRW<[SPRWriteResGroup230], (instrs SHA1MSG2rr)>;
2391 def SPRWriteResGroup231 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10]> {
2392 let Latency = 8;
2393 let NumMicroOps = 4;
2394 }
2395 def : InstRW<[SPRWriteResGroup231, ReadAfterVecXLd], (instrs SHA1NEXTErm)>;
2397 def SPRWriteResGroup232 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05]> {
2398 let Latency = 3;
2399 let NumMicroOps = 3;
2400 }
2401 def : InstRW<[SPRWriteResGroup232], (instrs SHA1NEXTErr)>;
2403 def SPRWriteResGroup233 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> {
2404 let Latency = 13;
2405 let NumMicroOps = 2;
2406 }
2407 def : InstRW<[SPRWriteResGroup233], (instregex "^VPMOV(S|Z)XBWZ((256)?)rmk(z?)$",
2408 "^VPOPCNT(B|W)Z(128|256)rmk(z?)$",
2409 "^VPOPCNT(B|W)Zrmk(z?)$")>;
2410 def : InstRW<[SPRWriteResGroup233, ReadAfterVecXLd], (instregex "^VDBPSADBWZ128rmik(z?)$",
2411 "^VPACK(S|U)SDWZ128rm(bk|kz)$",
2412 "^VPACK(S|U)SDWZ128rmbkz$",
2413 "^VPACK(S|U)S(DW|WB)Z128rmk$",
2414 "^VPACK(S|U)SWBZ128rmkz$",
2415 "^VPMULTISHIFTQBZ128rm(bk|kz)$",
2416 "^VPMULTISHIFTQBZ128rm(k|bkz)$")>;
2417 def : InstRW<[SPRWriteResGroup233, ReadAfterVecXLd], (instrs SHA1RNDS4rmi,
2418 SHA256RNDS2rm)>;
2419 def : InstRW<[SPRWriteResGroup233, ReadAfterVecYLd], (instregex "^VDBPSADBWZ((256)?)rmik(z?)$",
2420 "^VPACK(S|U)SDWZ((256)?)rm(bk|kz)$",
2421 "^VPACK(S|U)SDWZ((256)?)rmbkz$",
2422 "^VPACK(S|U)S(DW|WB)Z((256)?)rmk$",
2423 "^VPACK(S|U)SWBZ((256)?)rmkz$",
2424 "^VPERMBZ(128|256)rmk(z?)$",
2425 "^VPERMBZrmk(z?)$",
2426 "^VPMULTISHIFTQBZ((256)?)rm(bk|kz)$",
2427 "^VPMULTISHIFTQBZ((256)?)rm(k|bkz)$")>;
2429 def SPRWriteResGroup234 : SchedWriteRes<[SPRPort05]> {
2430 let Latency = 6;
2431 }
2432 def : InstRW<[SPRWriteResGroup234], (instrs SHA1RNDS4rri,
2433 SHA256RNDS2rr)>;
2435 def SPRWriteResGroup235 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
2436 let ReleaseAtCycles = [3, 2, 1, 1, 1];
2437 let Latency = 12;
2438 let NumMicroOps = 8;
2439 }
2440 def : InstRW<[SPRWriteResGroup235, ReadAfterVecXLd], (instrs SHA256MSG1rm)>;
2442 def SPRWriteResGroup236 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
2443 let ReleaseAtCycles = [3, 2, 1, 1];
2444 let Latency = 5;
2445 let NumMicroOps = 7;
2446 }
2447 def : InstRW<[SPRWriteResGroup236], (instrs SHA256MSG1rr)>;
2449 def SPRWriteResGroup237 : SchedWriteRes<[SPRPort05]> {
2450 let ReleaseAtCycles = [2];
2451 let Latency = 6;
2452 let NumMicroOps = 2;
2453 }
2454 def : InstRW<[SPRWriteResGroup237], (instregex "^VPMOV(D|Q|W|SQ|SW)BZrrk(z?)$",
2455 "^VPMOV((S|US)?)(D|Q)WZrrk(z?)$",
2456 "^VPMOV(U?)SDBZrrk(z?)$",
2457 "^VPMOVUS(Q|W)BZrrk(z?)$")>;
2458 def : InstRW<[SPRWriteResGroup237], (instrs SHA256MSG2rr)>;
2460 def SPRWriteResGroup238 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> {
2461 let Latency = 13;
2462 let NumMicroOps = 5;
2463 }
2464 def : InstRW<[SPRWriteResGroup238], (instrs SHRD16mri8)>;
2466 def SPRWriteResGroup239 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort01]> {
2467 let Latency = 6;
2468 let NumMicroOps = 2;
2469 }
2470 def : InstRW<[SPRWriteResGroup239], (instregex "^SLDT(32|64)r$")>;
2472 def SPRWriteResGroup240 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort05]> {
2473 let NumMicroOps = 2;
2474 }
2475 def : InstRW<[SPRWriteResGroup240], (instrs SMSW16r)>;
2477 def SPRWriteResGroup241 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort05]> {
2478 let Latency = SapphireRapidsModel.MaxLatency;
2479 let NumMicroOps = 2;
2480 }
2481 def : InstRW<[SPRWriteResGroup241], (instregex "^SMSW(32|64)r$")>;
2483 def SPRWriteResGroup242 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
2484 let Latency = 24;
2485 let NumMicroOps = 2;
2486 }
2487 def : InstRW<[SPRWriteResGroup242, ReadAfterVecLd], (instregex "^(V?)SQRTSDm_Int$")>;
2488 def : InstRW<[SPRWriteResGroup242, ReadAfterVecLd], (instrs VSQRTSDZm_Int)>;
2490 def SPRWriteResGroup243 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> {
2491 let Latency = 6;
2492 let NumMicroOps = 2;
2493 }
2494 def : InstRW<[SPRWriteResGroup243], (instrs STD)>;
2496 def SPRWriteResGroup244 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> {
2497 let ReleaseAtCycles = [1, 4, 1];
2498 let Latency = SapphireRapidsModel.MaxLatency;
2499 let NumMicroOps = 6;
2500 }
2501 def : InstRW<[SPRWriteResGroup244], (instrs STI)>;
2503 def SPRWriteResGroup245 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> {
2504 let ReleaseAtCycles = [2, 1, 1];
2505 let Latency = 8;
2506 let NumMicroOps = 4;
2507 }
2508 def : InstRW<[SPRWriteResGroup245], (instrs STOSB)>;
2510 def SPRWriteResGroup246 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> {
2511 let ReleaseAtCycles = [2, 1, 1];
2512 let Latency = 7;
2513 let NumMicroOps = 4;
2514 }
2515 def : InstRW<[SPRWriteResGroup246], (instregex "^STOS(L|Q|W)$")>;
2517 def SPRWriteResGroup247 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort01]> {
2518 let Latency = 5;
2519 let NumMicroOps = 2;
2520 }
2521 def : InstRW<[SPRWriteResGroup247], (instregex "^STR(32|64)r$")>;
2523 def SPRWriteResGroup248 : SchedWriteRes<[SPRPort00]> {
2524 let Latency = 2;
2525 }
2526 def : InstRW<[SPRWriteResGroup248], (instregex "^(TST|XAM)_F$")>;
2527 def : InstRW<[SPRWriteResGroup248], (instrs UCOM_FPPr)>;
2529 def SPRWriteResGroup249 : SchedWriteRes<[SPRPort01_05]> {
2530 let Latency = 4;
2531 }
2532 def : InstRW<[SPRWriteResGroup249], (instregex "^V(ADD|SUB)P(D|S)Z(128|256)rrkz$",
2533 "^V(ADD|SUB)S(D|S)Zrr(b?)kz_Int$")>;
2535 def SPRWriteResGroup250 : SchedWriteRes<[SPRPort00_05]> {
2536 let Latency = 3;
2537 }
2538 def : InstRW<[SPRWriteResGroup250], (instregex "^V(ADD|SUB)P(D|S)Zrr(b?)$",
2539 "^VMOVDQU(8|16)Zrrk(z?)((_REV)?)$",
2540 "^VP(ADD|SUB)(B|W)Zrrk(z?)$",
2541 "^VPBLENDM(B|W)Zrrk(z?)$",
2542 "^VPMOVM2(B|W)Zrk$")>;
2544 def SPRWriteResGroup251 : SchedWriteRes<[SPRPort00_01]> {
2545 let Latency = 6;
2546 }
2547 def : InstRW<[SPRWriteResGroup251], (instregex "^V(ADD|SUB)PHZ(128|256)rrk(z?)$",
2548 "^V(ADD|SUB)SHZrr(b?)k(z?)_Int$",
2549 "^VCVT(T?)PH2(U?)WZ(128|256)rrk(z?)$",
2550 "^VCVT(U?)W2PHZ(128|256)rrk(z?)$",
2551 "^VF(N?)M(ADD|SUB)(132|213|231)PHZ(128|256)rk(z?)$",
2552 "^VF(N?)M(ADD|SUB)(132|213|231)SHZr(b?)k(z?)_Int$",
2553 "^VFMADDSUB(132|213|231)PHZ(128|256)rk(z?)$",
2554 "^VFMSUBADD(132|213|231)PHZ(128|256)rk(z?)$",
2555 "^VGETEXPPHZ(128|256)rk(z?)$",
2556 "^VGETEXPSHZr(bk|kz)$",
2557 "^VGETEXPSHZr(k|bkz)$",
2558 "^VGETMANTPHZ(128|256)rrik(z?)$",
2559 "^VGETMANTSHZrri(bk|kz)$",
2560 "^VGETMANTSHZrri(k|bkz)$",
2561 "^VM(AX|IN)CPHZ(128|256)rrk(z?)$",
2562 "^VM(AX|IN|UL)PHZ(128|256)rrk(z?)$",
2563 "^VM(AX|IN|UL)SHZrr(b?)k(z?)_Int$")>;
2565 def SPRWriteResGroup252 : SchedWriteRes<[SPRPort00]> {
2566 let Latency = 5;
2567 }
2568 def : InstRW<[SPRWriteResGroup252], (instregex "^V(ADD|SUB)PHZrr(b?)$",
2569 "^VAES(DE|EN)C((LAST)?)Zrr$",
2570 "^VCVT(T?)PH2(U?)WZrr(b?)$",
2571 "^VCVT(U?)W2PHZrr(b?)$",
2572 "^VF(N?)M(ADD|SUB)(132|213|231)PHZr(b?)$",
2573 "^VFMADDSUB(132|213|231)PHZr(b?)$",
2574 "^VFMSUBADD(132|213|231)PHZr(b?)$",
2575 "^VGETEXPPHZr(b?)$",
2576 "^VGETMANTPHZrri(b?)$",
2577 "^VM(AX|IN)CPHZrr$",
2578 "^VM(AX|IN|UL)PHZrr(b?)$",
2579 "^VMOVMSKP(D|S)Yrr$")>;
2580 def : InstRW<[SPRWriteResGroup252], (instrs VGF2P8MULBZrr)>;
2582 def SPRWriteResGroup253 : SchedWriteRes<[SPRPort00]> {
2583 let Latency = 6;
2584 }
2585 def : InstRW<[SPRWriteResGroup253], (instregex "^V(ADD|SUB)PHZrr(bk|kz)$",
2586 "^V(ADD|SUB)PHZrr(k|bkz)$",
2587 "^VCVT(T?)PH2(U?)WZrr(bk|kz)$",
2588 "^VCVT(T?)PH2(U?)WZrr(k|bkz)$",
2589 "^VCVT(U?)W2PHZrr(bk|kz)$",
2590 "^VCVT(U?)W2PHZrr(k|bkz)$",
2591 "^VF(N?)M(ADD|SUB)(132|213|231)PHZr(bk|kz)$",
2592 "^VF(N?)M(ADD|SUB)(132|213|231)PHZr(k|bkz)$",
2593 "^VFMADDSUB(132|213|231)PHZr(bk|kz)$",
2594 "^VFMADDSUB(132|213|231)PHZr(k|bkz)$",
2595 "^VFMSUBADD(132|213|231)PHZr(bk|kz)$",
2596 "^VFMSUBADD(132|213|231)PHZr(k|bkz)$",
2597 "^VGETEXPPHZr(bk|kz)$",
2598 "^VGETEXPPHZr(k|bkz)$",
2599 "^VGETMANTPHZrri(bk|kz)$",
2600 "^VGETMANTPHZrri(k|bkz)$",
2601 "^VM(AX|IN)CPHZrrk(z?)$",
2602 "^VM(AX|IN|UL)PHZrr(bk|kz)$",
2603 "^VM(AX|IN|UL)PHZrr(k|bkz)$")>;
2605 def SPRWriteResGroup254 : SchedWriteRes<[SPRPort01_05, SPRPort02_03_10]> {
2606 let Latency = 11;
2607 let NumMicroOps = 2;
2608 }
2609 def : InstRW<[SPRWriteResGroup254], (instregex "^VPMOV(S|Z)XBWZ128rmk(z?)$",
2610 "^VPSHUF(H|L)WZ(128|256)mik(z?)$")>;
2611 def : InstRW<[SPRWriteResGroup254, ReadAfterVecYLd], (instregex "^V(ADD|SUB)PSYrm$",
2612 "^V(ADD|SUB)PSZ256rm((b|k|bk|kz)?)$",
2613 "^V(ADD|SUB)PSZ256rmbkz$",
2614 "^VPSHUFBZ256rmk(z?)$",
2615 "^VPUNPCK(H|L)(BW|WD)Z256rmk(z?)$")>;
2616 def : InstRW<[SPRWriteResGroup254, ReadAfterVecYLd], (instrs VADDSUBPSYrm)>;
2617 def : InstRW<[SPRWriteResGroup254, ReadAfterVecXLd], (instregex "^VPSHUFBZ128rmk(z?)$",
2618 "^VPUNPCK(H|L)(BW|WD)Z128rmk(z?)$")>;
2620 def SPRWriteResGroup255 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_10]> {
2621 let Latency = 11;
2622 let NumMicroOps = 2;
2623 }
2624 def : InstRW<[SPRWriteResGroup255], (instregex "^VMOVDQU(8|16)Zrmk(z?)$")>;
2625 def : InstRW<[SPRWriteResGroup255, ReadAfterVecYLd], (instregex "^V(ADD|SUB)PSZrm((b|k|bk|kz)?)$",
2626 "^V(ADD|SUB)PSZrmbkz$",
2627 "^VP(ADD|SUB)(B|W)Zrmk(z?)$",
2628 "^VPBLENDM(B|W)Zrmk(z?)$")>;
2630 def SPRWriteResGroup256 : SchedWriteRes<[SPRPort00_05]> {
2631 let Latency = 4;
2632 }
2633 def : InstRW<[SPRWriteResGroup256], (instregex "^V(ADD|SUB)PSZrr(bk|kz)$",
2634 "^V(ADD|SUB)PSZrr(k|bkz)$")>;
2636 def SPRWriteResGroup257 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
2637 let Latency = 12;
2638 let NumMicroOps = 2;
2639 }
2640 def : InstRW<[SPRWriteResGroup257], (instregex "^VCVT(T?)PS2(U?)DQZrm((b|k|bk|kz)?)$",
2641 "^VCVT(T?)PS2(U?)DQZrmbkz$",
2642 "^VPLZCNT(D|Q)Zrm((b|k|bk|kz)?)$",
2643 "^VPLZCNT(D|Q)Zrmbkz$")>;
2644 def : InstRW<[SPRWriteResGroup257, ReadAfterVecXLd], (instregex "^VAES(DE|EN)C((LAST)?)Zrm$")>;
2645 def : InstRW<[SPRWriteResGroup257, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBZrm(b?)i$")>;
2646 def : InstRW<[SPRWriteResGroup257, ReadAfterVecYLd], (instrs VGF2P8MULBZrm)>;
2647 def : InstRW<[SPRWriteResGroup257, ReadAfterVecYLd, ReadAfterVecYLd], (instregex "^VPMADD52(H|L)UQZm((b|k|bk|kz)?)$",
2648 "^VPMADD52(H|L)UQZmbkz$")>;
2650 def SPRWriteResGroup258 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> {
2651 let Latency = 11;
2652 let NumMicroOps = 2;
2653 }
2654 def : InstRW<[SPRWriteResGroup258], (instregex "^VPBROADCAST(B|W)Z128rmk(z?)$",
2655 "^VPOPCNT(B|D|Q|W)Z((256)?)rm$",
2656 "^VPOPCNT(D|Q)Z((256)?)rm(b|k|kz)$",
2657 "^VPOPCNT(D|Q)Z((256)?)rmbk(z?)$",
2658 "^VPSHUF(H|L)WZmik(z?)$")>;
2659 def : InstRW<[SPRWriteResGroup258, ReadAfterVecYLd], (instregex "^VALIGN(D|Q)Z((256)?)rm(bi|ik)$",
2660 "^VALIGN(D|Q)Z((256)?)rmbik(z?)$",
2661 "^VALIGN(D|Q)Z((256)?)rmi((kz)?)$",
2662 "^VFPCLASSP(D|H|S)Z((256)?)mbi$",
2663 "^VPACK(S|U)S(DW|WB)(Y|Z)rm$",
2664 "^VPACK(S|U)S(DW|WB)Z256rm$",
2665 "^VPACK(S|U)SDWZ((256)?)rmb$",
2666 "^VPALIGNRZ((256)?)rmik(z?)$",
2667 "^VPM(AX|IN)(S|U)QZ((256)?)rm((b|k|bk|kz)?)$",
2668 "^VPM(AX|IN)(S|U)QZ((256)?)rmbkz$",
2669 "^VPMULTISHIFTQBZ((256)?)rm(b?)$",
2670 "^VPUNPCK(H|L)(BW|WD)Zrmk(z?)$")>;
2671 def : InstRW<[SPRWriteResGroup258, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>;
2672 def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instregex "^VPALIGNRZ128rmik(z?)$",
2673 "^VPCLMULQDQ(Y|Z)rmi$")>;
2674 def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instrs VPCLMULQDQZ256rmi)>;
2676 def SPRWriteResGroup259 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10]> {
2677 let ReleaseAtCycles = [3, 1];
2678 let Latency = 10;
2679 let NumMicroOps = 4;
2680 }
2681 def : InstRW<[SPRWriteResGroup259, ReadAfterVecYLd, ReadAfterVecYLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)Yrmr$")>;
2682 def : InstRW<[SPRWriteResGroup259, ReadAfterVecYLd, ReadAfterVecYLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBYrmr)>;
2684 def SPRWriteResGroup260 : SchedWriteRes<[SPRPort00_01_05]> {
2685 let ReleaseAtCycles = [3];
2686 let Latency = 3;
2687 let NumMicroOps = 3;
2688 }
2689 def : InstRW<[SPRWriteResGroup260], (instregex "^VBLENDVP(S|DY)rrr$",
2690 "^VBLENDVP(D|SY)rrr$",
2691 "^VPBLENDVB(Y?)rrr$")>;
2693 def SPRWriteResGroup261 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10]> {
2694 let ReleaseAtCycles = [3, 1];
2695 let Latency = 9;
2696 let NumMicroOps = 4;
2697 }
2698 def : InstRW<[SPRWriteResGroup261, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rmr$")>;
2699 def : InstRW<[SPRWriteResGroup261, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrmr)>;
2701 def SPRWriteResGroup262 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10]> {
2702 let Latency = 9;
2703 let NumMicroOps = 2;
2704 }
2705 def : InstRW<[SPRWriteResGroup262], (instregex "^VBROADCAST(F|I)32X(2|4)Z256rmk(z?)$",
2706 "^VBROADCAST(F|I)64X2Z256rmk(z?)$",
2707 "^VBROADCASTS(D|S)Z256rmk(z?)$",
2708 "^VMOV(A|U)P(D|S)Z256rmk(z?)$",
2709 "^VMOV(D|SH|SL)DUPZ256rmk(z?)$",
2710 "^VMOVDQ(A|U)(32|64)Z256rmk(z?)$",
2711 "^VPBROADCAST(D|Q)Z256rmk(z?)$")>;
2712 def : InstRW<[SPRWriteResGroup262, ReadAfterVecYLd], (instregex "^VINSERT(F|I)128rmi$",
2713 "^VINSERT(F|I)(32X4|64X2)Z256rmi((k|kz)?)$",
2714 "^VP(ADD|SUB)(B|D|Q|W)(Y|Z256)rm$",
2715 "^VP(ADD|SUB)(D|Q)Z256rm(b|k|kz)$",
2716 "^VP(ADD|SUB)(D|Q)Z256rmbk(z?)$",
2717 "^VPTERNLOG(D|Q)Z256rm(bi|ik)$",
2718 "^VPTERNLOG(D|Q)Z256rmbik(z?)$",
2719 "^VPTERNLOG(D|Q)Z256rmi((kz)?)$")>;
2721 def SPRWriteResGroup263 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> {
2722 let Latency = 3;
2723 let NumMicroOps = 2;
2724 }
2725 def : InstRW<[SPRWriteResGroup263, ReadAfterVecXLd], (instregex "^VCMPP(D|H|S)Z128rm(bi|ik)$",
2726 "^VCMPP(D|H|S)Z128rm(i|bik)$",
2727 "^VFPCLASSP(D|H|S)Z128m(b?)ik$",
2728 "^VPCMP(B|D|Q|W|UD|UQ|UW)Z128rmi(k?)$",
2729 "^VPCMP(D|Q|UQ)Z128rmbi(k?)$",
2730 "^VPCMP(EQ|GT)(B|D|Q|W)Z128rm(k?)$",
2731 "^VPCMP(EQ|GT)(D|Q)Z128rmb(k?)$",
2732 "^VPCMPUBZ128rmi(k?)$",
2733 "^VPCMPUDZ128rmbi(k?)$",
2734 "^VPTEST(N?)M(B|D|Q|W)Z128rm(k?)$",
2735 "^VPTEST(N?)M(D|Q)Z128rmb(k?)$")>;
2736 def : InstRW<[SPRWriteResGroup263, ReadAfterVecYLd], (instregex "^VCMPP(D|H|S)Z((256)?)rm(bi|ik)$",
2737 "^VCMPP(D|H|S)Z((256)?)rm(i|bik)$",
2738 "^VFPCLASSP(D|H|S)Z((256)?)m(b?)ik$",
2739 "^VPCMP(B|D|Q|W|UD|UQ|UW)Z((256)?)rmi(k?)$",
2740 "^VPCMP(D|Q|UQ)Z((256)?)rmbi(k?)$",
2741 "^VPCMP(EQ|GT)(B|D|Q|W)Z((256)?)rm(k?)$",
2742 "^VPCMP(EQ|GT)(D|Q)Z((256)?)rmb(k?)$",
2743 "^VPCMPUBZ((256)?)rmi(k?)$",
2744 "^VPCMPUDZ((256)?)rmbi(k?)$",
2745 "^VPTEST(N?)M(B|D|Q|W)Z((256)?)rm(k?)$",
2746 "^VPTEST(N?)M(D|Q)Z((256)?)rmb(k?)$")>;
2747 def : InstRW<[SPRWriteResGroup263, ReadAfterVecLd], (instregex "^VCMPS(D|H|S)Zrmi$",
2748 "^VCMPS(D|H|S)Zrmi(k?)_Int$",
2749 "^VFPCLASSS(D|H|S)Zmik$")>;
2751 def SPRWriteResGroup264 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
2752 let Latency = 10;
2753 let NumMicroOps = 2;
2754 }
2755 def : InstRW<[SPRWriteResGroup264, ReadAfterVecLd], (instregex "^V(U?)COMISHZrm((_Int)?)$")>;
2757 def SPRWriteResGroup265 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> {
2758 let ReleaseAtCycles = [1, 2, 1];
2759 let Latency = 12;
2760 let NumMicroOps = 4;
2761 }
2762 def : InstRW<[SPRWriteResGroup265], (instregex "^VCOMPRESSP(D|S)Z(128|256)mr$",
2763 "^VCOMPRESSP(D|S)Zmr$",
2764 "^VPCOMPRESS(D|Q)Z(128|256)mr$",
2765 "^VPCOMPRESS(D|Q)Zmr$",
2766 "^VPMOV(D|Q|W|SQ|SW)BZmr$",
2767 "^VPMOV((S|US)?)(D|Q)WZmr$",
2768 "^VPMOV(U?)S(DB|QD)Zmr$",
2769 "^VPMOVUS(Q|W)BZmr$")>;
2771 def SPRWriteResGroup266 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> {
2772 let ReleaseAtCycles = [1, 2, 1];
2773 let Latency = 15;
2774 let NumMicroOps = 4;
2775 }
2776 def : InstRW<[SPRWriteResGroup266], (instregex "^VCOMPRESSP(D|S)Z(128|256)mrk$",
2777 "^VCOMPRESSP(D|S)Zmrk$",
2778 "^VPCOMPRESS(D|Q)Z(128|256)mrk$",
2779 "^VPCOMPRESS(D|Q)Zmrk$",
2780 "^VPMOV(D|Q|W|SQ|SW)BZmrk$",
2781 "^VPMOV((S|US)?)(D|Q)WZmrk$",
2782 "^VPMOV(U?)S(DB|QD)Zmrk$",
2783 "^VPMOVUS(Q|W)BZmrk$")>;
2785 def SPRWriteResGroup267 : SchedWriteRes<[SPRPort05]> {
2786 let ReleaseAtCycles = [2];
2787 let Latency = 3;
2788 let NumMicroOps = 2;
2789 }
2790 def : InstRW<[SPRWriteResGroup267], (instregex "^VCOMPRESSP(D|S)Z(128|256)rr$",
2791 "^VCOMPRESSP(D|S)Zrr$",
2792 "^VEXPANDP(D|S)Z(128|256)rr$",
2793 "^VEXPANDP(D|S)Zrr$",
2794 "^VPCOMPRESS(B|D|Q|W)Z(128|256)rr$",
2795 "^VPCOMPRESS(B|D|Q|W)Zrr$",
2796 "^VPEXPAND(B|D|Q|W)Z(128|256)rr$",
2797 "^VPEXPAND(B|D|Q|W)Zrr$")>;
2799 def SPRWriteResGroup268 : SchedWriteRes<[SPRPort00, SPRPort05]> {
2800 let Latency = 7;
2801 let NumMicroOps = 2;
2802 }
2803 def : InstRW<[SPRWriteResGroup268], (instregex "^VCVT(U?)DQ2PDZrr((k|kz)?)$",
2804 "^VCVT(T?)PS2(U?)QQZrr((b|k|bk|kz)?)$",
2805 "^VCVT(T?)PS2(U?)QQZrrbkz$",
2806 "^VCVT(U?)QQ2PSZrr((b|k|bk|kz)?)$",
2807 "^VCVT(U?)QQ2PSZrrbkz$")>;
2809 def SPRWriteResGroup269 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
2810 let Latency = 15;
2811 let NumMicroOps = 4;
2812 }
2813 def : InstRW<[SPRWriteResGroup269], (instregex "^VCVT(U?)DQ2PHZ128rm(b?)$",
2814 "^VCVTNEPS2BF16Z128rm(b?)$")>;
2816 def SPRWriteResGroup270 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
2817 let Latency = 19;
2818 let NumMicroOps = 4;
2819 }
2820 def : InstRW<[SPRWriteResGroup270], (instregex "^VCVT(U?)DQ2PHZ128rm(bk|kz)$",
2821 "^VCVT(U?)DQ2PHZ128rm(k|bkz)$")>;
2823 def SPRWriteResGroup271 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2824 let Latency = 7;
2825 let NumMicroOps = 3;
2826 }
2827 def : InstRW<[SPRWriteResGroup271], (instregex "^VCVT(U?)DQ2PHZ128rr$")>;
2829 def SPRWriteResGroup272 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2830 let Latency = 12;
2831 let NumMicroOps = 3;
2832 }
2833 def : InstRW<[SPRWriteResGroup272], (instregex "^VCVT(U?)DQ2PHZ128rrk(z?)$")>;
2835 def SPRWriteResGroup273 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
2836 let Latency = 17;
2837 let NumMicroOps = 4;
2838 }
2839 def : InstRW<[SPRWriteResGroup273], (instregex "^VCVT(U?)DQ2PHZ256rm(b?)$",
2840 "^VCVTNEPS2BF16Z128rm(bk|kz)$",
2841 "^VCVTNEPS2BF16Z128rm(k|bkz)$")>;
2843 def SPRWriteResGroup274 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
2844 let Latency = 21;
2845 let NumMicroOps = 4;
2846 }
2847 def : InstRW<[SPRWriteResGroup274], (instregex "^VCVT(U?)DQ2PHZ256rm(bk|kz)$",
2848 "^VCVT(U?)DQ2PHZ256rm(k|bkz)$")>;
2850 def SPRWriteResGroup275 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2851 let Latency = 9;
2852 let NumMicroOps = 3;
2853 }
2854 def : InstRW<[SPRWriteResGroup275], (instregex "^VCVT(U?)DQ2PHZ256rr$")>;
2856 def SPRWriteResGroup276 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2857 let Latency = 14;
2858 let NumMicroOps = 3;
2859 }
2860 def : InstRW<[SPRWriteResGroup276], (instregex "^VCVT(U?)DQ2PHZ256rrk(z?)$")>;
2862 def SPRWriteResGroup277 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
2863 let ReleaseAtCycles = [1, 1, 2];
2864 let Latency = 17;
2865 let NumMicroOps = 4;
2866 }
2867 def : InstRW<[SPRWriteResGroup277], (instregex "^VCVT(U?)DQ2PHZrm(b?)$")>;
2869 def SPRWriteResGroup278 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
2870 let ReleaseAtCycles = [1, 1, 2];
2871 let Latency = 21;
2872 let NumMicroOps = 4;
2873 }
2874 def : InstRW<[SPRWriteResGroup278], (instregex "^VCVT(U?)DQ2PHZrm(bk|kz)$",
2875 "^VCVT(U?)DQ2PHZrm(k|bkz)$")>;
2877 def SPRWriteResGroup279 : SchedWriteRes<[SPRPort00, SPRPort05]> {
2878 let ReleaseAtCycles = [1, 2];
2879 let Latency = 9;
2880 let NumMicroOps = 3;
2881 }
2882 def : InstRW<[SPRWriteResGroup279], (instregex "^VCVT(U?)DQ2PHZrr(b?)$")>;
2884 def SPRWriteResGroup280 : SchedWriteRes<[SPRPort00, SPRPort05]> {
2885 let ReleaseAtCycles = [1, 2];
2886 let Latency = 14;
2887 let NumMicroOps = 3;
2888 }
2889 def : InstRW<[SPRWriteResGroup280], (instregex "^VCVT(U?)DQ2PHZrr(bk|kz)$",
2890 "^VCVT(U?)DQ2PHZrr(k|bkz)$")>;
2892 def SPRWriteResGroup281 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
2893 let ReleaseAtCycles = [2, 1, 1, 1];
2894 let Latency = 15;
2895 let NumMicroOps = 5;
2896 }
2897 def : InstRW<[SPRWriteResGroup281, ReadAfterVecXLd], (instregex "^VCVTNE2PS2BF16Z128rm(b?)$")>;
2899 def SPRWriteResGroup282 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
2900 let ReleaseAtCycles = [2, 1, 1, 1];
2901 let Latency = 17;
2902 let NumMicroOps = 5;
2903 }
2904 def : InstRW<[SPRWriteResGroup282, ReadAfterVecXLd], (instregex "^VCVTNE2PS2BF16Z128rm(bk|kz)$",
2905 "^VCVTNE2PS2BF16Z128rm(k|bkz)$")>;
2907 def SPRWriteResGroup283 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2908 let ReleaseAtCycles = [2, 1, 1];
2909 let Latency = 8;
2910 let NumMicroOps = 4;
2911 }
2912 def : InstRW<[SPRWriteResGroup283], (instregex "^VCVTNE2PS2BF16Z(128|256)rr$")>;
2914 def SPRWriteResGroup284 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2915 let ReleaseAtCycles = [2, 1, 1];
2916 let Latency = 10;
2917 let NumMicroOps = 4;
2918 }
2919 def : InstRW<[SPRWriteResGroup284], (instregex "^VCVTNE2PS2BF16Z(128|256)rrk(z?)$")>;
2921 def SPRWriteResGroup285 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
2922 let ReleaseAtCycles = [2, 1, 1, 1];
2923 let Latency = 16;
2924 let NumMicroOps = 5;
2925 }
2926 def : InstRW<[SPRWriteResGroup285, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Z256rm(b?)$")>;
2928 def SPRWriteResGroup286 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
2929 let ReleaseAtCycles = [2, 1, 1, 1];
2930 let Latency = 18;
2931 let NumMicroOps = 5;
2932 }
2933 def : InstRW<[SPRWriteResGroup286, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Z256rm(bk|kz)$",
2934 "^VCVTNE2PS2BF16Z256rm(k|bkz)$")>;
2936 def SPRWriteResGroup287 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
2937 let ReleaseAtCycles = [2, 1, 2];
2938 let Latency = 16;
2939 let NumMicroOps = 5;
2940 }
2941 def : InstRW<[SPRWriteResGroup287, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Zrm(b?)$",
2942 "^VDPBF16PSZm((b|k|bk|kz)?)$")>;
2943 def : InstRW<[SPRWriteResGroup287, ReadAfterVecYLd], (instrs VDPBF16PSZmbkz)>;
2945 def SPRWriteResGroup288 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
2946 let ReleaseAtCycles = [2, 1, 2];
2947 let Latency = 18;
2948 let NumMicroOps = 5;
2949 }
2950 def : InstRW<[SPRWriteResGroup288, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Zrm(bk|kz)$",
2951 "^VCVTNE2PS2BF16Zrm(k|bkz)$")>;
2953 def SPRWriteResGroup289 : SchedWriteRes<[SPRPort00, SPRPort05]> {
2954 let ReleaseAtCycles = [2, 2];
2955 let Latency = 8;
2956 let NumMicroOps = 4;
2957 }
2958 def : InstRW<[SPRWriteResGroup289], (instregex "^VDPBF16PSZr((k|kz)?)$")>;
2959 def : InstRW<[SPRWriteResGroup289], (instrs VCVTNE2PS2BF16Zrr)>;
2961 def SPRWriteResGroup290 : SchedWriteRes<[SPRPort00, SPRPort05]> {
2962 let ReleaseAtCycles = [2, 2];
2963 let Latency = 10;
2964 let NumMicroOps = 4;
2965 }
2966 def : InstRW<[SPRWriteResGroup290], (instregex "^VCVTNE2PS2BF16Zrrk(z?)$")>;
2968 def SPRWriteResGroup291 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2969 let Latency = 8;
2970 let NumMicroOps = 3;
2971 }
2972 def : InstRW<[SPRWriteResGroup291], (instregex "^VCVTNEPS2BF16Z(128|256)rr$")>;
2974 def SPRWriteResGroup292 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2975 let Latency = 10;
2976 let NumMicroOps = 3;
2977 }
2978 def : InstRW<[SPRWriteResGroup292], (instregex "^VCVTNEPS2BF16Z(128|256)rrk(z?)$")>;
2980 def SPRWriteResGroup293 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
2981 let Latency = 16;
2982 let NumMicroOps = 4;
2983 }
2984 def : InstRW<[SPRWriteResGroup293], (instregex "^VCVTNEPS2BF16Z256rm(b?)$")>;
2986 def SPRWriteResGroup294 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
2987 let Latency = 18;
2988 let NumMicroOps = 4;
2989 }
2990 def : InstRW<[SPRWriteResGroup294], (instregex "^VCVTNEPS2BF16Z256rm(bk|kz)$",
2991 "^VCVTNEPS2BF16Z256rm(k|bkz)$")>;
2993 def SPRWriteResGroup295 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
2994 let ReleaseAtCycles = [1, 1, 2];
2995 let Latency = 16;
2996 let NumMicroOps = 4;
2997 }
2998 def : InstRW<[SPRWriteResGroup295], (instregex "^VCVTNEPS2BF16Zrm(b?)$")>;
3000 def SPRWriteResGroup296 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
3001 let ReleaseAtCycles = [1, 1, 2];
3002 let Latency = 18;
3003 let NumMicroOps = 4;
3004 }
3005 def : InstRW<[SPRWriteResGroup296], (instregex "^VCVTNEPS2BF16Zrm(bk|kz)$",
3006 "^VCVTNEPS2BF16Zrm(k|bkz)$")>;
3008 def SPRWriteResGroup297 : SchedWriteRes<[SPRPort00, SPRPort05]> {
3009 let ReleaseAtCycles = [1, 2];
3010 let Latency = 8;
3011 let NumMicroOps = 3;
3012 }
3013 def : InstRW<[SPRWriteResGroup297], (instrs VCVTNEPS2BF16Zrr)>;
3015 def SPRWriteResGroup298 : SchedWriteRes<[SPRPort00, SPRPort05]> {
3016 let ReleaseAtCycles = [1, 2];
3017 let Latency = 10;
3018 let NumMicroOps = 3;
3019 }
3020 def : InstRW<[SPRWriteResGroup298], (instregex "^VCVTNEPS2BF16Zrrk(z?)$")>;
3022 def SPRWriteResGroup299 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
3023 let Latency = 15;
3024 let NumMicroOps = 3;
3025 }
3026 def : InstRW<[SPRWriteResGroup299], (instregex "^VCVT(T?)PD2DQYrm$",
3027 "^VCVT(T?)P(D|H)2(U?)DQZ256rm(b?)$",
3028 "^VCVT(T?)PD2(U?)DQZ256rm(bk|kz)$",
3029 "^VCVT(T?)PD2(U?)DQZ256rm(k|bkz)$",
3030 "^VCVTPH2PSXZ128rm(bk|kz)$",
3031 "^VCVTPH2PSXZ128rm(k|bkz)$",
3032 "^VCVTPH2PSXZ256rm(b?)$",
3033 "^VCVT(U?)QQ2PSZ256rm((b|k|bk|kz)?)$",
3034 "^VCVT(U?)QQ2PSZ256rmbkz$")>;
3036 def SPRWriteResGroup300 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
3037 let Latency = 15;
3038 let NumMicroOps = 3;
3039 }
3040 def : InstRW<[SPRWriteResGroup300], (instregex "^VCVT(T?)P(D|H)2(U?)DQZrm(b?)$",
3041 "^VCVT(T?)PD2(U?)DQZrm(bk|kz)$",
3042 "^VCVT(T?)PD2(U?)DQZrm(k|bkz)$",
3043 "^VCVTPH2PSXZrm(b?)$",
3044 "^VCVT(U?)QQ2PSZrm((b|k|bk|kz)?)$",
3045 "^VCVT(U?)QQ2PSZrmbkz$")>;
3047 def SPRWriteResGroup301 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
3048 let ReleaseAtCycles = [2, 1, 1, 1, 2];
3049 let Latency = 19;
3050 let NumMicroOps = 7;
3051 }
3052 def : InstRW<[SPRWriteResGroup301], (instregex "^VCVTPD2PHZ128rm(b?)$")>;
3054 def SPRWriteResGroup302 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
3055 let ReleaseAtCycles = [2, 1, 1, 1, 2];
3056 let Latency = 22;
3057 let NumMicroOps = 7;
3058 }
3059 def : InstRW<[SPRWriteResGroup302], (instregex "^VCVTPD2PHZ128rm(bk|kz)$",
3060 "^VCVTPD2PHZ128rm(k|bkz)$")>;
3062 def SPRWriteResGroup303 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
3063 let ReleaseAtCycles = [2, 1, 2];
3064 let Latency = 12;
3065 let NumMicroOps = 5;
3066 }
3067 def : InstRW<[SPRWriteResGroup303], (instrs VCVTPD2PHZ128rr)>;
3069 def SPRWriteResGroup304 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
3070 let ReleaseAtCycles = [2, 1, 2];
3071 let Latency = 15;
3072 let NumMicroOps = 5;
3073 }
3074 def : InstRW<[SPRWriteResGroup304], (instregex "^VCVTPD2PHZ128rrk(z?)$")>;
3076 def SPRWriteResGroup305 : SchedWriteRes<[SPRPort00_01, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
3077 let ReleaseAtCycles = [2, 1, 1, 2];
3078 let Latency = 21;
3079 let NumMicroOps = 6;
3080 }
3081 def : InstRW<[SPRWriteResGroup305], (instregex "^VCVTPD2PHZ256rm(b?)$")>;
3083 def SPRWriteResGroup306 : SchedWriteRes<[SPRPort00_01, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
3084 let ReleaseAtCycles = [2, 1, 1, 2];
3085 let Latency = 24;
3086 let NumMicroOps = 6;
3087 }
3088 def : InstRW<[SPRWriteResGroup306], (instregex "^VCVTPD2PHZ256rm(bk|kz)$",
3089 "^VCVTPD2PHZ256rm(k|bkz)$")>;
3091 def SPRWriteResGroup307 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3092 let ReleaseAtCycles = [2, 2];
3093 let Latency = 13;
3094 let NumMicroOps = 4;
3095 }
3096 def : InstRW<[SPRWriteResGroup307], (instrs VCVTPD2PHZ256rr)>;
3098 def SPRWriteResGroup308 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3099 let ReleaseAtCycles = [2, 2];
3100 let Latency = 16;
3101 let NumMicroOps = 4;
3102 }
3103 def : InstRW<[SPRWriteResGroup308], (instregex "^VCVTPD2PHZ256rrk(z?)$")>;
3105 def SPRWriteResGroup309 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
3106 let ReleaseAtCycles = [2, 1, 1, 2];
3107 let Latency = 23;
3108 let NumMicroOps = 6;
3109 }
3110 def : InstRW<[SPRWriteResGroup309], (instregex "^VCVTP(D2PH|H2PD)Zrm(b?)$")>;
3112 def SPRWriteResGroup310 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
3113 let ReleaseAtCycles = [2, 1, 1, 2];
3114 let Latency = 26;
3115 let NumMicroOps = 6;
3116 }
3117 def : InstRW<[SPRWriteResGroup310], (instregex "^VCVTP(D2PH|H2PD)Zrm(bk|kz)$",
3118 "^VCVTP(D2PH|H2PD)Zrm(k|bkz)$")>;
3120 def SPRWriteResGroup311 : SchedWriteRes<[SPRPort00, SPRPort05]> {
3121 let ReleaseAtCycles = [2, 2];
3122 let Latency = 15;
3123 let NumMicroOps = 4;
3124 }
3125 def : InstRW<[SPRWriteResGroup311], (instregex "^VCVTP(D2PH|H2PD)Zrr(b?)$")>;
3127 def SPRWriteResGroup312 : SchedWriteRes<[SPRPort00, SPRPort05]> {
3128 let ReleaseAtCycles = [2, 2];
3129 let Latency = 18;
3130 let NumMicroOps = 4;
3131 }
3132 def : InstRW<[SPRWriteResGroup312], (instregex "^VCVTP(D2PH|H2PD)Zrr(bk|kz)$",
3133 "^VCVTP(D2PH|H2PD)Zrr(k|bkz)$")>;
3135 def SPRWriteResGroup313 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> {
3136 let Latency = 11;
3137 let NumMicroOps = 2;
3138 }
3139 def : InstRW<[SPRWriteResGroup313], (instregex "^VCVT(T?)PD2(U?)QQZ128rm((b|k|bk|kz)?)$",
3140 "^VCVT(T?)PD2(U?)QQZ128rmbkz$",
3141 "^VPABS(B|W)Z(128|256)rmk(z?)$",
3142 "^VPLZCNT(D|Q)Z128rm((b|k|bk|kz)?)$",
3143 "^VPLZCNT(D|Q)Z128rmbkz$",
3144 "^VPS(L|R)LWZ(128|256)mik(z?)$",
3145 "^VPSRAWZ(128|256)mik(z?)$")>;
3146 def : InstRW<[SPRWriteResGroup313, ReadAfterVecLd], (instregex "^VFIXUPIMMS(D|S)Zrmi((k|kz)?)$",
3147 "^VSCALEFS(D|S)Zrm((k|kz)?)$")>;
3148 def : InstRW<[SPRWriteResGroup313, ReadAfterVecXLd], (instregex "^VP(ADD|SUB)(U?)S(B|W)Z128rmk(z?)$",
3149 "^VPAVG(B|W)Z128rmk(z?)$",
3150 "^VPM(AX|IN)(SB|UW)Z128rmk(z?)$",
3151 "^VPM(AX|IN)(SW|UB)Z128rmk(z?)$",
3152 "^VPSH(L|R)DVWZ128mk(z?)$",
3153 "^VPS(L|R)L(V?)WZ128rmk(z?)$",
3154 "^VPSRA(V?)WZ128rmk(z?)$")>;
3155 def : InstRW<[SPRWriteResGroup313, ReadAfterVecYLd], (instregex "^VP(ADD|SUB)(U?)S(B|W)Z256rmk(z?)$",
3156 "^VPAVG(B|W)Z256rmk(z?)$",
3157 "^VPM(AX|IN)(SB|UW)Z256rmk(z?)$",
3158 "^VPM(AX|IN)(SW|UB)Z256rmk(z?)$",
3159 "^VPSH(L|R)DVWZ256mk(z?)$",
3160 "^VPS(L|R)L(V?)WZ256rmk(z?)$",
3161 "^VPSRA(V?)WZ256rmk(z?)$")>;
3162 def : InstRW<[SPRWriteResGroup313, ReadAfterVecXLd, ReadAfterVecXLd], (instregex "^VPMADD52(H|L)UQZ128m((b|k|bk|kz)?)$",
3163 "^VPMADD52(H|L)UQZ128mbkz$")>;
3165 def SPRWriteResGroup314 : SchedWriteRes<[SPRPort00_01]> {
3166 let Latency = 4;
3167 }
3168 def : InstRW<[SPRWriteResGroup314], (instregex "^VCVT(T?)PD2(U?)QQZ(128|256)rr((k|kz)?)$",
3169 "^VCVT(U?)QQ2PDZ(128|256)rr((k|kz)?)$",
3170 "^VFIXUPIMMS(D|S)Zrri((k|kz)?)$",
3171 "^VPLZCNT(D|Q)Z(128|256)rr((k|kz)?)$",
3172 "^VPMADD52(H|L)UQZ(128|256)r((k|kz)?)$",
3173 "^VSCALEFS(D|S)Zrr((k|kz)?)$",
3174 "^VSCALEFS(D|S)Zrrb((k|kz)?)_Int$")>;
3175 def : InstRW<[SPRWriteResGroup314, ReadAfterVecLd], (instregex "^VFIXUPIMMS(D|S)Zrrib((k|kz)?)$")>;
3177 def SPRWriteResGroup315 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
3178 let Latency = 14;
3179 let NumMicroOps = 3;
3180 }
3181 def : InstRW<[SPRWriteResGroup315], (instregex "^VCVT(T?)PH2(U?)DQZ128rm(b?)$",
3182 "^VCVTPS2PHXZ128rm(b?)$")>;
3184 def SPRWriteResGroup316 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
3185 let Latency = 17;
3186 let NumMicroOps = 3;
3187 }
3188 def : InstRW<[SPRWriteResGroup316], (instregex "^VCVT(T?)PH2(U?)DQZ128rm(bk|kz)$",
3189 "^VCVT(T?)PH2(U?)DQZ128rm(k|bkz)$")>;
3191 def SPRWriteResGroup317 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3192 let Latency = 11;
3193 let NumMicroOps = 2;
3194 }
3195 def : InstRW<[SPRWriteResGroup317], (instregex "^VCVT(T?)PH2(U?)DQZ(128|256)rrk(z?)$",
3196 "^VCVTP(H2PS|S2PH)(X?)Z256rrk(z?)$")>;
3198 def SPRWriteResGroup318 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
3199 let Latency = 18;
3200 let NumMicroOps = 3;
3201 }
3202 def : InstRW<[SPRWriteResGroup318], (instregex "^VCVT(T?)PH2(U?)DQZ256rm(bk|kz)$",
3203 "^VCVT(T?)PH2(U?)DQZ256rm(k|bkz)$",
3204 "^VCVTP(H2PS|S2PH)XZ256rm(bk|kz)$",
3205 "^VCVTP(H2PS|S2PH)XZ256rm(k|bkz)$")>;
3207 def SPRWriteResGroup319 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
3208 let Latency = 18;
3209 let NumMicroOps = 3;
3210 }
3211 def : InstRW<[SPRWriteResGroup319], (instregex "^VCVT(T?)PH2(U?)DQZrm(bk|kz)$",
3212 "^VCVT(T?)PH2(U?)DQZrm(k|bkz)$",
3213 "^VCVTP(H2PS|S2PH)XZrm(bk|kz)$",
3214 "^VCVTP(H2PS|S2PH)XZrm(k|bkz)$")>;
3216 def SPRWriteResGroup320 : SchedWriteRes<[SPRPort00, SPRPort05]> {
3217 let Latency = 8;
3218 let NumMicroOps = 2;
3219 }
3220 def : InstRW<[SPRWriteResGroup320], (instregex "^VCVT(T?)PH2(U?)DQZrr(b?)$",
3221 "^VCVTP(H2PS|S2PH)(X?)Zrr(b?)$",
3222 "^VPSHUFBITQMBZ(128|256)rrk$")>;
3223 def : InstRW<[SPRWriteResGroup320], (instrs VPSHUFBITQMBZrrk)>;
3225 def SPRWriteResGroup321 : SchedWriteRes<[SPRPort00, SPRPort05]> {
3226 let Latency = 11;
3227 let NumMicroOps = 2;
3228 }
3229 def : InstRW<[SPRWriteResGroup321], (instregex "^VCVT(T?)PH2(U?)DQZrr(bk|kz)$",
3230 "^VCVT(T?)PH2(U?)DQZrr(k|bkz)$",
3231 "^VCVTP(H2PS|S2PH)XZrr(bk|kz)$",
3232 "^VCVTP(H2PS|S2PH)XZrr(k|bkz)$")>;
3234 def SPRWriteResGroup322 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
3235 let ReleaseAtCycles = [2, 1, 1, 1, 2];
3236 let Latency = 23;
3237 let NumMicroOps = 7;
3238 }
3239 def : InstRW<[SPRWriteResGroup322], (instregex "^VCVTPH2PDZ128rm(b?)$")>;
3241 def SPRWriteResGroup323 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
3242 let ReleaseAtCycles = [2, 1, 1, 1, 2];
3243 let Latency = 26;
3244 let NumMicroOps = 7;
3245 }
3246 def : InstRW<[SPRWriteResGroup323], (instregex "^VCVTPH2PDZ128rm(bk|kz)$",
3247 "^VCVTPH2PDZ128rm(k|bkz)$")>;
3249 def SPRWriteResGroup324 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
3250 let ReleaseAtCycles = [2, 1, 1, 2];
3251 let Latency = 16;
3252 let NumMicroOps = 6;
3253 }
3254 def : InstRW<[SPRWriteResGroup324], (instrs VCVTPH2PDZ128rr)>;
3256 def SPRWriteResGroup325 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
3257 let ReleaseAtCycles = [2, 1, 1, 2];
3258 let Latency = 19;
3259 let NumMicroOps = 6;
3260 }
3261 def : InstRW<[SPRWriteResGroup325], (instregex "^VCVTPH2PDZ128rrk(z?)$")>;
3263 def SPRWriteResGroup326 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
3264 let ReleaseAtCycles = [2, 1, 2];
3265 let Latency = 22;
3266 let NumMicroOps = 5;
3267 }
3268 def : InstRW<[SPRWriteResGroup326], (instregex "^VCVTPH2PDZ256rm(b?)$")>;
3270 def SPRWriteResGroup327 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
3271 let ReleaseAtCycles = [2, 1, 2];
3272 let Latency = 25;
3273 let NumMicroOps = 5;
3274 }
3275 def : InstRW<[SPRWriteResGroup327], (instregex "^VCVTPH2PDZ256rm(bk|kz)$",
3276 "^VCVTPH2PDZ256rm(k|bkz)$")>;
3278 def SPRWriteResGroup328 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3279 let ReleaseAtCycles = [2, 2];
3280 let Latency = 15;
3281 let NumMicroOps = 4;
3282 }
3283 def : InstRW<[SPRWriteResGroup328], (instrs VCVTPH2PDZ256rr)>;
3285 def SPRWriteResGroup329 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3286 let ReleaseAtCycles = [2, 2];
3287 let Latency = 18;
3288 let NumMicroOps = 4;
3289 }
3290 def : InstRW<[SPRWriteResGroup329], (instregex "^VCVTPH2PDZ256rrk(z?)$")>;
3292 def SPRWriteResGroup330 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3293 let Latency = 9;
3294 let NumMicroOps = 2;
3295 }
3296 def : InstRW<[SPRWriteResGroup330], (instregex "^VCVTP(H2PS|S2PH)(X?)Z128rrk(z?)$")>;
3298 def SPRWriteResGroup331 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> {
3299 let Latency = 14;
3300 let NumMicroOps = 2;
3301 }
3302 def : InstRW<[SPRWriteResGroup331], (instregex "^VCVTPH2PSZ(128|256)rmk(z?)$")>;
3303 def : InstRW<[SPRWriteResGroup331, ReadAfterVecLd], (instregex "^VCVTSH2SSZrmk(z?)_Int$")>;
3304 def : InstRW<[SPRWriteResGroup331, ReadAfterVecXLd], (instregex "^VPMADDUBSWZ128rmk(z?)$",
3305 "^VPMULH((U|RS)?)WZ128rmk(z?)$",
3306 "^VPMULLWZ128rmk(z?)$")>;
3307 def : InstRW<[SPRWriteResGroup331, ReadAfterVecYLd], (instregex "^VPMADDUBSWZ256rmk(z?)$",
3308 "^VPMULH((U|RS)?)WZ256rmk(z?)$",
3309 "^VPMULLWZ256rmk(z?)$")>;
3311 def SPRWriteResGroup332 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
3312 let Latency = 13;
3313 let NumMicroOps = 3;
3314 }
3315 def : InstRW<[SPRWriteResGroup332], (instregex "^VCVT(T?)PS2(U?)QQZrm((b|k|bk|kz)?)$",
3316 "^VCVT(T?)PS2(U?)QQZrmbkz$")>;
3317 def : InstRW<[SPRWriteResGroup332], (instrs VCVTPH2PSZrm)>;
3318 def : InstRW<[SPRWriteResGroup332, ReadAfterVecYLd], (instregex "^VPERMWZrmk(z?)$")>;
3320 def SPRWriteResGroup333 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
3321 let ReleaseAtCycles = [1, 2, 1, 1, 1];
3322 let Latency = 17;
3323 let NumMicroOps = 6;
3324 }
3325 def : InstRW<[SPRWriteResGroup333], (instregex "^VCVT(T?)PH2(U?)QQZ128rm((b|k|bk|kz)?)$",
3326 "^VCVT(T?)PH2(U?)QQZ128rmbkz$")>;
3328 def SPRWriteResGroup334 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
3329 let ReleaseAtCycles = [1, 2, 1];
3330 let Latency = 10;
3331 let NumMicroOps = 4;
3332 }
3333 def : InstRW<[SPRWriteResGroup334], (instregex "^VCVT(T?)PH2(U?)QQZ(128|256)rr((k|kz)?)$")>;
3335 def SPRWriteResGroup335 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
3336 let ReleaseAtCycles = [1, 2, 1, 1, 1];
3337 let Latency = 18;
3338 let NumMicroOps = 6;
3339 }
3340 def : InstRW<[SPRWriteResGroup335], (instregex "^VCVT(T?)PH2(U?)QQZ256rm((b|k|bk|kz)?)$",
3341 "^VCVT(T?)PH2(U?)QQZ256rmbkz$")>;
3343 def SPRWriteResGroup336 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
3344 let Latency = 16;
3345 let NumMicroOps = 3;
3346 }
3347 def : InstRW<[SPRWriteResGroup336], (instregex "^VCVTPS2PHXZ128rm(bk|kz)$",
3348 "^VCVTPS2PHXZ128rm(k|bkz)$",
3349 "^VCVTPS2PHXZ256rm(b?)$")>;
3351 def SPRWriteResGroup337 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
3352 let Latency = 16;
3353 let NumMicroOps = 3;
3354 }
3355 def : InstRW<[SPRWriteResGroup337], (instregex "^VCVTPS2PHXZrm(b?)$")>;
3357 def SPRWriteResGroup338 : SchedWriteRes<[SPRPort00_01, SPRPort04_09, SPRPort07_08]> {
3358 let Latency = 16;
3359 let NumMicroOps = 3;
3360 }
3361 def : InstRW<[SPRWriteResGroup338], (instregex "^VCVTPS2PHZ(128|256)mrk$")>;
3363 def SPRWriteResGroup339 : SchedWriteRes<[SPRPort00, SPRPort04_09, SPRPort07_08]> {
3364 let Latency = 16;
3365 let NumMicroOps = 3;
3366 }
3367 def : InstRW<[SPRWriteResGroup339], (instrs VCVTPS2PHZmrk)>;
3369 def SPRWriteResGroup340 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3370 let Latency = 5;
3371 let NumMicroOps = 2;
3372 }
3373 def : InstRW<[SPRWriteResGroup340], (instregex "^VCVT(T?)PS2(U?)QQZ128rr((k|kz)?)$",
3374 "^VCVT(U?)QQ2PSZ128rr((k|kz)?)$")>;
3376 def SPRWriteResGroup341 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
3377 let Latency = 15;
3378 let NumMicroOps = 5;
3379 }
3380 def : InstRW<[SPRWriteResGroup341], (instregex "^VCVT(U?)QQ2PHZ128rm(b?)$")>;
3382 def SPRWriteResGroup342 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
3383 let Latency = 17;
3384 let NumMicroOps = 5;
3385 }
3386 def : InstRW<[SPRWriteResGroup342], (instregex "^VCVT(U?)QQ2PHZ128rm(bk|kz)$",
3387 "^VCVT(U?)QQ2PHZ128rm(k|bkz)$")>;
3389 def SPRWriteResGroup343 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort05]> {
3390 let Latency = 8;
3391 let NumMicroOps = 4;
3392 }
3393 def : InstRW<[SPRWriteResGroup343], (instregex "^VCVT(U?)QQ2PHZ128rr$")>;
3395 def SPRWriteResGroup344 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort05]> {
3396 let Latency = 10;
3397 let NumMicroOps = 4;
3398 }
3399 def : InstRW<[SPRWriteResGroup344], (instregex "^VCVT(U?)QQ2PHZ128rrk(z?)$",
3400 "^VCVT(U?)QQ2PHZ256rr$")>;
3402 def SPRWriteResGroup345 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
3403 let Latency = 18;
3404 let NumMicroOps = 5;
3405 }
3406 def : InstRW<[SPRWriteResGroup345], (instregex "^VCVT(U?)QQ2PHZ256rm(b?)$")>;
3408 def SPRWriteResGroup346 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
3409 let Latency = 20;
3410 let NumMicroOps = 5;
3411 }
3412 def : InstRW<[SPRWriteResGroup346], (instregex "^VCVT(U?)QQ2PHZ256rm(bk|kz)$",
3413 "^VCVT(U?)QQ2PHZ256rm(k|bkz)$")>;
3415 def SPRWriteResGroup347 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort05]> {
3416 let Latency = 12;
3417 let NumMicroOps = 4;
3418 }
3419 def : InstRW<[SPRWriteResGroup347], (instregex "^VCVT(U?)QQ2PHZ256rrk(z?)$")>;
3421 def SPRWriteResGroup348 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10, SPRPort05]> {
3422 let ReleaseAtCycles = [1, 1, 1, 2];
3423 let Latency = 18;
3424 let NumMicroOps = 5;
3425 }
3426 def : InstRW<[SPRWriteResGroup348], (instregex "^VCVT(U?)QQ2PHZrm(b?)$")>;
3428 def SPRWriteResGroup349 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10, SPRPort05]> {
3429 let ReleaseAtCycles = [1, 1, 1, 2];
3430 let Latency = 20;
3431 let NumMicroOps = 5;
3432 }
3433 def : InstRW<[SPRWriteResGroup349], (instregex "^VCVT(U?)QQ2PHZrm(bk|kz)$",
3434 "^VCVT(U?)QQ2PHZrm(k|bkz)$")>;
3436 def SPRWriteResGroup350 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
3437 let ReleaseAtCycles = [1, 1, 2];
3438 let Latency = 10;
3439 let NumMicroOps = 4;
3440 }
3441 def : InstRW<[SPRWriteResGroup350], (instregex "^VCVT(U?)QQ2PHZrr(b?)$")>;
3443 def SPRWriteResGroup351 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
3444 let ReleaseAtCycles = [1, 1, 2];
3445 let Latency = 12;
3446 let NumMicroOps = 4;
3447 }
3448 def : InstRW<[SPRWriteResGroup351], (instregex "^VCVT(U?)QQ2PHZrr(bk|kz)$",
3449 "^VCVT(U?)QQ2PHZrr(k|bkz)$")>;
3451 def SPRWriteResGroup352 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
3452 let ReleaseAtCycles = [2, 2, 1, 1, 1];
3453 let Latency = 18;
3454 let NumMicroOps = 7;
3455 }
3456 def : InstRW<[SPRWriteResGroup352, ReadAfterVecLd], (instregex "^VCVTSD2SHZrm((_Int)?)$")>;
3458 def SPRWriteResGroup353 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
3459 let ReleaseAtCycles = [2, 2, 1, 1, 1];
3460 let Latency = 21;
3461 let NumMicroOps = 7;
3462 }
3463 def : InstRW<[SPRWriteResGroup353, ReadAfterVecLd], (instregex "^VCVTSD2SHZrmk(z?)_Int$")>;
3465 def SPRWriteResGroup354 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
3466 let ReleaseAtCycles = [2, 1, 1];
3467 let Latency = 11;
3468 let NumMicroOps = 4;
3469 }
3470 def : InstRW<[SPRWriteResGroup354], (instregex "^VCVTSD2SHZrr(b?)_Int$")>;
3471 def : InstRW<[SPRWriteResGroup354], (instrs VCVTSD2SHZrr)>;
3473 def SPRWriteResGroup355 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
3474 let ReleaseAtCycles = [2, 1, 1];
3475 let Latency = 14;
3476 let NumMicroOps = 4;
3477 }
3478 def : InstRW<[SPRWriteResGroup355], (instregex "^VCVTSD2SHZrr(b?)k(z?)_Int$")>;
3480 def SPRWriteResGroup356 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
3481 let ReleaseAtCycles = [2, 1, 1];
3482 let Latency = 18;
3483 let NumMicroOps = 4;
3484 }
3485 def : InstRW<[SPRWriteResGroup356, ReadAfterVecLd], (instregex "^VCVTSH2SDZrm((_Int)?)$")>;
3487 def SPRWriteResGroup357 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
3488 let ReleaseAtCycles = [2, 1, 1];
3489 let Latency = 20;
3490 let NumMicroOps = 4;
3491 }
3492 def : InstRW<[SPRWriteResGroup357, ReadAfterVecLd], (instregex "^VCVTSH2SDZrmk(z?)_Int$")>;
3494 def SPRWriteResGroup358 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3495 let ReleaseAtCycles = [2, 1];
3496 let Latency = 10;
3497 let NumMicroOps = 3;
3498 }
3499 def : InstRW<[SPRWriteResGroup358], (instregex "^VCVTSH2SDZrr(b?)_Int$")>;
3500 def : InstRW<[SPRWriteResGroup358], (instrs VCVTSH2SDZrr)>;
3502 def SPRWriteResGroup359 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3503 let ReleaseAtCycles = [2, 1];
3504 let Latency = 13;
3505 let NumMicroOps = 3;
3506 }
3507 def : InstRW<[SPRWriteResGroup359], (instregex "^VCVTSH2SDZrr(b?)k(z?)_Int$")>;
3509 def SPRWriteResGroup360 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort02_03_10]> {
3510 let Latency = 13;
3511 let NumMicroOps = 3;
3512 }
3513 def : InstRW<[SPRWriteResGroup360, ReadAfterVecLd], (instregex "^VCVT(T?)SH2(U?)SI((64)?)Zrm_Int$",
3514 "^VCVTTSH2(U?)SI((64)?)Zrm$")>;
3516 def SPRWriteResGroup361 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05]> {
3517 let Latency = 8;
3518 let NumMicroOps = 3;
3519 }
3520 def : InstRW<[SPRWriteResGroup361], (instregex "^VCVT(T?)SH2(U?)SI((64)?)Zrr(b?)_Int$",
3521 "^VCVTTSH2(U?)SI((64)?)Zrr$")>;
3523 def SPRWriteResGroup362 : SchedWriteRes<[SPRPort00_01]> {
3524 let Latency = 8;
3525 }
3526 def : InstRW<[SPRWriteResGroup362], (instregex "^VCVTSH2SSZrr(b?)k(z?)_Int$")>;
3528 def SPRWriteResGroup363 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10]> {
3529 let Latency = 14;
3530 let NumMicroOps = 3;
3531 }
3532 def : InstRW<[SPRWriteResGroup363, ReadAfterVecLd], (instregex "^VCVT(U?)SI((64)?)2SHZrm((_Int)?)$",
3533 "^VCVTSS2SHZrm((_Int)?)$")>;
3535 def SPRWriteResGroup364 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10]> {
3536 let Latency = 16;
3537 let NumMicroOps = 3;
3538 }
3539 def : InstRW<[SPRWriteResGroup364, ReadAfterVecLd], (instregex "^VCVTSS2SHZrmk(z?)_Int$")>;
3541 def SPRWriteResGroup365 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05]> {
3542 let Latency = 6;
3543 let NumMicroOps = 2;
3544 }
3545 def : InstRW<[SPRWriteResGroup365], (instregex "^VCVTSS2SHZrr(b?)_Int$")>;
3546 def : InstRW<[SPRWriteResGroup365], (instrs VCVTSS2SHZrr)>;
3548 def SPRWriteResGroup366 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05]> {
3549 let Latency = 9;
3550 let NumMicroOps = 2;
3551 }
3552 def : InstRW<[SPRWriteResGroup366], (instregex "^VCVTSS2SHZrr(b?)k(z?)_Int$")>;
3554 def SPRWriteResGroup367 : SchedWriteRes<[SPRPort05]> {
3555 let Latency = 5;
3556 }
3557 def : InstRW<[SPRWriteResGroup367], (instregex "^VDBPSADBWZ(128|256)rrik(z?)$",
3558 "^VDBPSADBWZrrik(z?)$",
3559 "^VPACK(S|U)S(DW|WB)Z(128|256)rrk(z?)$",
3560 "^VPACK(S|U)S(DW|WB)Zrrk(z?)$",
3561 "^VPBROADCAST(B|W|Dr|Qr|Wr)Z((256)?)rrk(z?)$",
3562 "^VPBROADCAST(B|D|Q|W)rZ(128|256)rr$",
3563 "^VPBROADCASTBrZ(128|256)rrk(z?)$",
3564 "^VPBROADCAST(B|D|Q|W)rZrr$",
3565 "^VPBROADCASTBrZrrk(z?)$",
3566 "^VPBROADCAST(D|Q|W)rZ128rrk(z?)$",
3567 "^VPERMBZ(128|256)rrk(z?)$",
3568 "^VPERMBZrrk(z?)$",
3569 "^VPMOV(S|Z)XBWZ((256)?)rrk(z?)$",
3570 "^VPMULTISHIFTQBZ(128|256)rrk(z?)$",
3571 "^VPMULTISHIFTQBZrrk(z?)$",
3572 "^VPOPCNT(B|W)Z(128|256)rrk(z?)$",
3573 "^VPOPCNT(B|W)Zrrk(z?)$")>;
3575 def SPRWriteResGroup368 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_10]> {
3576 let ReleaseAtCycles = [2, 1, 1];
3577 let Latency = 36;
3578 let NumMicroOps = 4;
3579 }
3580 def : InstRW<[SPRWriteResGroup368, ReadAfterVecXLd], (instregex "^VDIVPHZ128rm(b?)$")>;
3582 def SPRWriteResGroup369 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_10]> {
3583 let ReleaseAtCycles = [2, 1, 1];
3584 let Latency = 38;
3585 let NumMicroOps = 4;
3586 }
3587 def : InstRW<[SPRWriteResGroup369, ReadAfterVecXLd], (instregex "^VDIVPHZ128rm(bk|kz)$",
3588 "^VDIVPHZ128rm(k|bkz)$")>;
3590 def SPRWriteResGroup370 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
3591 let ReleaseAtCycles = [2, 1];
3592 let Latency = 31;
3593 let NumMicroOps = 3;
3594 }
3595 def : InstRW<[SPRWriteResGroup370], (instregex "^VDIVPHZ(128|256)rr$")>;
3597 def SPRWriteResGroup371 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
3598 let ReleaseAtCycles = [2, 1];
3599 let Latency = 33;
3600 let NumMicroOps = 3;
3601 }
3602 def : InstRW<[SPRWriteResGroup371], (instregex "^VDIVPHZ(128|256)rrk$",
3603 "^VSQRTPHZ(128|256)r$")>;
3604 def : InstRW<[SPRWriteResGroup371], (instrs VDIVPHZ128rrkz)>;
3606 def SPRWriteResGroup372 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_10]> {
3607 let ReleaseAtCycles = [2, 1, 1];
3608 let Latency = 37;
3609 let NumMicroOps = 4;
3610 }
3611 def : InstRW<[SPRWriteResGroup372, ReadAfterVecYLd], (instregex "^VDIVPHZ256rm(b?)$")>;
3613 def SPRWriteResGroup373 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_10]> {
3614 let ReleaseAtCycles = [2, 1, 1];
3615 let Latency = 39;
3616 let NumMicroOps = 4;
3617 }
3618 def : InstRW<[SPRWriteResGroup373, ReadAfterVecYLd], (instregex "^VDIVPHZ256rm(bk|kz)$",
3619 "^VDIVPHZ256rm(k|bkz)$")>;
3620 def : InstRW<[SPRWriteResGroup373, ReadAfterVecXLd], (instregex "^VSQRTPHZ128m(b?)$")>;
3622 def SPRWriteResGroup374 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
3623 let ReleaseAtCycles = [2, 1];
3624 let Latency = 11;
3625 let NumMicroOps = 3;
3626 }
3627 def : InstRW<[SPRWriteResGroup374], (instrs VDIVPHZ256rrkz)>;
3629 def SPRWriteResGroup375 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
3630 let ReleaseAtCycles = [4, 2, 1, 1, 1];
3631 let Latency = 49;
3632 let NumMicroOps = 9;
3633 }
3634 def : InstRW<[SPRWriteResGroup375, ReadAfterVecYLd], (instregex "^VDIVPHZrm(b?)$")>;
3636 def SPRWriteResGroup376 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
3637 let ReleaseAtCycles = [4, 2, 1, 1, 1];
3638 let Latency = 51;
3639 let NumMicroOps = 9;
3640 }
3641 def : InstRW<[SPRWriteResGroup376, ReadAfterVecYLd], (instregex "^VDIVPHZrm(bk|kz)$",
3642 "^VDIVPHZrm(k|bkz)$")>;
3644 def SPRWriteResGroup377 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
3645 let ReleaseAtCycles = [4, 1, 1];
3646 let Latency = 41;
3647 let NumMicroOps = 6;
3648 }
3649 def : InstRW<[SPRWriteResGroup377], (instregex "^VDIVPHZrr(b?)$")>;
3651 def SPRWriteResGroup378 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
3652 let ReleaseAtCycles = [4, 1, 1];
3653 let Latency = 43;
3654 let NumMicroOps = 6;
3655 }
3656 def : InstRW<[SPRWriteResGroup378], (instregex "^VDIVPHZrr(bk|kz)$",
3657 "^VDIVPHZrr(k|bkz)$")>;
3659 def SPRWriteResGroup379 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
3660 let ReleaseAtCycles = [2, 1];
3661 let Latency = 17;
3662 let NumMicroOps = 3;
3663 }
3664 def : InstRW<[SPRWriteResGroup379], (instrs VDIVPSZrr)>;
3666 def SPRWriteResGroup380 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
3667 let Latency = 21;
3668 let NumMicroOps = 2;
3669 }
3670 def : InstRW<[SPRWriteResGroup380, ReadAfterVecLd], (instregex "^VDIVSHZrm((k|kz)?)_Int$")>;
3671 def : InstRW<[SPRWriteResGroup380, ReadAfterVecLd], (instrs VDIVSHZrm)>;
3673 def SPRWriteResGroup381 : SchedWriteRes<[SPRPort00]> {
3674 let Latency = 14;
3675 }
3676 def : InstRW<[SPRWriteResGroup381], (instrs VDIVSHZrr_Int,
3677 VSQRTSHZr_Int)>;
3679 def SPRWriteResGroup382 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
3680 let ReleaseAtCycles = [2, 1, 2];
3681 let Latency = 15;
3682 let NumMicroOps = 5;
3683 }
3684 def : InstRW<[SPRWriteResGroup382, ReadAfterVecXLd], (instregex "^VDPBF16PSZ128m((b|k|bk|kz)?)$")>;
3685 def : InstRW<[SPRWriteResGroup382, ReadAfterVecXLd], (instrs VDPBF16PSZ128mbkz)>;
3687 def SPRWriteResGroup383 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3688 let ReleaseAtCycles = [2, 2];
3689 let Latency = 8;
3690 let NumMicroOps = 4;
3691 }
3692 def : InstRW<[SPRWriteResGroup383], (instregex "^VDPBF16PSZ(128|256)r((k|kz)?)$")>;
3694 def SPRWriteResGroup384 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
3695 let ReleaseAtCycles = [2, 1, 2];
3696 let Latency = 16;
3697 let NumMicroOps = 5;
3698 }
3699 def : InstRW<[SPRWriteResGroup384, ReadAfterVecYLd], (instregex "^VDPBF16PSZ256m((b|k|bk|kz)?)$")>;
3700 def : InstRW<[SPRWriteResGroup384, ReadAfterVecYLd], (instrs VDPBF16PSZ256mbkz)>;
3702 def SPRWriteResGroup385 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_10]> {
3703 let ReleaseAtCycles = [6, 7, 18];
3704 let Latency = 81;
3705 let NumMicroOps = 31;
3706 }
3707 def : InstRW<[SPRWriteResGroup385], (instrs VERRm)>;
3709 def SPRWriteResGroup386 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_10]> {
3710 let ReleaseAtCycles = [6, 7, 17];
3711 let Latency = 74;
3712 let NumMicroOps = 30;
3713 }
3714 def : InstRW<[SPRWriteResGroup386], (instrs VERRr)>;
3716 def SPRWriteResGroup387 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_10]> {
3717 let ReleaseAtCycles = [5, 8, 21];
3718 let Latency = 81;
3719 let NumMicroOps = 34;
3720 }
3721 def : InstRW<[SPRWriteResGroup387], (instrs VERWm)>;
3723 def SPRWriteResGroup388 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_10]> {
3724 let ReleaseAtCycles = [5, 8, 20];
3725 let Latency = 74;
3726 let NumMicroOps = 33;
3727 }
3728 def : InstRW<[SPRWriteResGroup388], (instrs VERWr)>;
3730 def SPRWriteResGroup389 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> {
3731 let ReleaseAtCycles = [1, 2];
3732 let Latency = 10;
3733 let NumMicroOps = 3;
3734 }
3735 def : InstRW<[SPRWriteResGroup389, ReadAfterVecYLd], (instregex "^VEXPANDP(D|S)Z128rm((k|kz)?)$",
3736 "^VPEXPAND(B|D|Q|W)Z128rm$",
3737 "^VPEXPAND(D|Q)Z128rmk(z?)$")>;
3739 def SPRWriteResGroup390 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> {
3740 let ReleaseAtCycles = [2, 1];
3741 let Latency = 16;
3742 let NumMicroOps = 3;
3743 }
3744 def : InstRW<[SPRWriteResGroup390], (instregex "^VF(C?)MADDCPHZ(128|256)m(b?)$",
3745 "^VROUNDP(D|S)Ymi$")>;
3746 def : InstRW<[SPRWriteResGroup390, ReadAfterVecXLd], (instregex "^VF(C?)MADDCSHZm$",
3747 "^VF(C?)MULCPHZ128rm(b?)$",
3748 "^VF(C?)MULCSHZrm$",
3749 "^VRNDSCALEPHZ128rm(b?)i$",
3750 "^VRNDSCALESHZrmi((_Int)?)$",
3751 "^VSCALEFPHZ128rm(b?)$")>;
3752 def : InstRW<[SPRWriteResGroup390, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZ256rm(b?)$",
3753 "^VRNDSCALEP(D|H|S)Z256rm(b?)i$",
3754 "^VRNDSCALEP(D|S)Z256rm(b?)ik(z?)$",
3755 "^VSCALEFPHZ256rm(b?)$")>;
3756 def : InstRW<[SPRWriteResGroup390, ReadAfterVecLd], (instrs VSCALEFSHZrm)>;
3758 def SPRWriteResGroup391 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> {
3759 let ReleaseAtCycles = [2, 1];
3760 let Latency = 21;
3761 let NumMicroOps = 3;
3762 }
3763 def : InstRW<[SPRWriteResGroup391], (instregex "^VF(C?)MADDCPHZ(128|256)m(bk|kz)$",
3764 "^VF(C?)MADDCPHZ(128|256)m(k|bkz)$")>;
3765 def : InstRW<[SPRWriteResGroup391, ReadAfterVecXLd], (instregex "^VF(C?)MADDCSHZmk(z?)$",
3766 "^VF(C?)MULCPHZ128rm(bk|kz)$",
3767 "^VF(C?)MULCPHZ128rm(k|bkz)$",
3768 "^VF(C?)MULCSHZrmk(z?)$")>;
3769 def : InstRW<[SPRWriteResGroup391, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZ256rm(bk|kz)$",
3770 "^VF(C?)MULCPHZ256rm(k|bkz)$")>;
3772 def SPRWriteResGroup392 : SchedWriteRes<[SPRPort00_01]> {
3773 let ReleaseAtCycles = [2];
3774 let Latency = 9;
3775 let NumMicroOps = 2;
3776 }
3777 def : InstRW<[SPRWriteResGroup392], (instregex "^VF(C?)MADDCPHZ(128|256)r$",
3778 "^VF(C?)MADDCSHZr(b?)$",
3779 "^VF(C?)MULCPHZ(128|256)rr$",
3780 "^VF(C?)MULCSHZrr(b?)$",
3781 "^VRNDSCALEPHZ(128|256)rri$",
3782 "^VRNDSCALESHZrri(b?)_Int$",
3783 "^VSCALEFPHZ(128|256)rr$")>;
3784 def : InstRW<[SPRWriteResGroup392], (instrs VRNDSCALESHZrri,
3785 VSCALEFSHZrr,
3786 VSCALEFSHZrrb_Int)>;
3788 def SPRWriteResGroup393 : SchedWriteRes<[SPRPort00_01]> {
3789 let ReleaseAtCycles = [2];
3790 let Latency = 15;
3791 let NumMicroOps = 2;
3792 }
3793 def : InstRW<[SPRWriteResGroup393], (instregex "^VF(C?)MADDCPHZ(128|256)rk(z?)$",
3794 "^VF(C?)MADDCSHZr(bk|kz)$",
3795 "^VF(C?)MADDCSHZr(k|bkz)$",
3796 "^VF(C?)MULCPHZ(128|256)rrk(z?)$",
3797 "^VF(C?)MULCSHZrr(bk|kz)$",
3798 "^VF(C?)MULCSHZrr(k|bkz)$")>;
3800 def SPRWriteResGroup394 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
3801 let ReleaseAtCycles = [2, 1];
3802 let Latency = 16;
3803 let NumMicroOps = 3;
3804 }
3805 def : InstRW<[SPRWriteResGroup394], (instregex "^VF(C?)MADDCPHZm(b?)$")>;
3806 def : InstRW<[SPRWriteResGroup394, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZrm(b?)$",
3807 "^VRNDSCALEP(D|H|S)Zrm(b?)i$",
3808 "^VRNDSCALEP(D|S)Zrm(b?)ik(z?)$",
3809 "^VSCALEFPHZrm(b?)$")>;
3811 def SPRWriteResGroup395 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
3812 let ReleaseAtCycles = [2, 1];
3813 let Latency = 21;
3814 let NumMicroOps = 3;
3815 }
3816 def : InstRW<[SPRWriteResGroup395], (instregex "^VF(C?)MADDCPHZm(bk|kz)$",
3817 "^VF(C?)MADDCPHZm(k|bkz)$")>;
3818 def : InstRW<[SPRWriteResGroup395, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZrm(bk|kz)$",
3819 "^VF(C?)MULCPHZrm(k|bkz)$")>;
3821 def SPRWriteResGroup396 : SchedWriteRes<[SPRPort00]> {
3822 let ReleaseAtCycles = [2];
3823 let Latency = 9;
3824 let NumMicroOps = 2;
3825 }
3826 def : InstRW<[SPRWriteResGroup396], (instregex "^VF(C?)MADDCPHZr(b?)$",
3827 "^VF(C?)MULCPHZrr(b?)$",
3828 "^VRNDSCALEPHZrri(b?)$",
3829 "^VSCALEFPHZrr(b?)$")>;
3831 def SPRWriteResGroup397 : SchedWriteRes<[SPRPort00]> {
3832 let ReleaseAtCycles = [2];
3833 let Latency = 15;
3834 let NumMicroOps = 2;
3835 }
3836 def : InstRW<[SPRWriteResGroup397], (instregex "^VF(C?)MADDCPHZr(bk|kz)$",
3837 "^VF(C?)MADDCPHZr(k|bkz)$",
3838 "^VF(C?)MULCPHZrr(bk|kz)$",
3839 "^VF(C?)MULCPHZrr(k|bkz)$")>;
3841 def SPRWriteResGroup398 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10]> {
3842 let ReleaseAtCycles = [1, 1, 2, 4];
3843 let Latency = 29;
3844 let NumMicroOps = 8;
3845 }
3846 def : InstRW<[SPRWriteResGroup398, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDYrm$",
3847 "^VPGATHER(D|Q)QYrm$")>;
3848 def : InstRW<[SPRWriteResGroup398, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSYrm,
3849 VPGATHERQDYrm)>;
3851 def SPRWriteResGroup399 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_10]> {
3852 let ReleaseAtCycles = [1, 1, 2];
3853 let Latency = 20;
3854 let NumMicroOps = 4;
3855 }
3856 def : InstRW<[SPRWriteResGroup399, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDZ128rm$",
3857 "^VPGATHER(D|Q)QZ128rm$")>;
3858 def : InstRW<[SPRWriteResGroup399, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSZ128rm,
3859 VPGATHERQDZ128rm)>;
3861 def SPRWriteResGroup400 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_10]> {
3862 let ReleaseAtCycles = [1, 2, 4];
3863 let Latency = 28;
3864 let NumMicroOps = 7;
3865 }
3866 def : InstRW<[SPRWriteResGroup400, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDZ256rm$",
3867 "^VPGATHER(D|Q)QZ256rm$")>;
3868 def : InstRW<[SPRWriteResGroup400, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSZ256rm,
3869 VPGATHERQDZ256rm)>;
3871 def SPRWriteResGroup401 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
3872 let ReleaseAtCycles = [1, 8, 2];
3873 let Latency = 28;
3874 let NumMicroOps = 11;
3875 }
3876 def : InstRW<[SPRWriteResGroup401, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDZrm$",
3877 "^VPGATHER(D|Q)QZrm$")>;
3878 def : InstRW<[SPRWriteResGroup401, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSZrm,
3879 VPGATHERQDZrm)>;
3881 def SPRWriteResGroup402 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10]> {
3882 let ReleaseAtCycles = [1, 1, 1, 2];
3883 let Latency = 20;
3884 let NumMicroOps = 5;
3885 }
3886 def : InstRW<[SPRWriteResGroup402, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDrm$",
3887 "^VPGATHER(D|Q)Qrm$")>;
3888 def : InstRW<[SPRWriteResGroup402, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSrm,
3889 VPGATHERQDrm)>;
3891 def SPRWriteResGroup403 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10]> {
3892 let ReleaseAtCycles = [1, 1, 2, 8];
3893 let Latency = 30;
3894 let NumMicroOps = 12;
3895 }
3896 def : InstRW<[SPRWriteResGroup403, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSYrm,
3897 VPGATHERDDYrm)>;
3899 def SPRWriteResGroup404 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_10]> {
3900 let ReleaseAtCycles = [1, 2, 4];
3901 let Latency = 27;
3902 let NumMicroOps = 7;
3903 }
3904 def : InstRW<[SPRWriteResGroup404, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSZ128rm,
3905 VPGATHERDDZ128rm)>;
3907 def SPRWriteResGroup405 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_10]> {
3908 let ReleaseAtCycles = [1, 2, 8];
3909 let Latency = 29;
3910 let NumMicroOps = 11;
3911 }
3912 def : InstRW<[SPRWriteResGroup405, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSZ256rm,
3913 VPGATHERDDZ256rm)>;
3915 def SPRWriteResGroup406 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
3916 let ReleaseAtCycles = [1, 16, 2];
3917 let Latency = 30;
3918 let NumMicroOps = 19;
3919 }
3920 def : InstRW<[SPRWriteResGroup406, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSZrm,
3921 VPGATHERDDZrm)>;
3923 def SPRWriteResGroup407 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10]> {
3924 let ReleaseAtCycles = [1, 1, 2, 4];
3925 let Latency = 28;
3926 let NumMicroOps = 8;
3927 }
3928 def : InstRW<[SPRWriteResGroup407, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSrm,
3929 VPGATHERDDrm)>;
3931 def SPRWriteResGroup408 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> {
3932 let Latency = 15;
3933 let NumMicroOps = 2;
3934 }
3935 def : InstRW<[SPRWriteResGroup408, ReadAfterVecXLd], (instregex "^VGF2P8AFFINE((INV)?)QBZ128rm(b?)ik(z?)$",
3936 "^VGF2P8MULBZ128rmk(z?)$")>;
3937 def : InstRW<[SPRWriteResGroup408, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBZ256rm(b?)ik(z?)$",
3938 "^VGF2P8MULBZ256rmk(z?)$")>;
3940 def SPRWriteResGroup409 : SchedWriteRes<[SPRPort00_01]> {
3941 let Latency = 9;
3942 }
3943 def : InstRW<[SPRWriteResGroup409], (instregex "^VGF2P8AFFINE((INV)?)QBZ(128|256)rrik$",
3944 "^VGF2P8MULBZ(128|256)rrk$")>;
3946 def SPRWriteResGroup410 : SchedWriteRes<[SPRPort00_01]> {
3947 let Latency = 10;
3948 }
3949 def : InstRW<[SPRWriteResGroup410], (instregex "^VGF2P8AFFINE((INV)?)QBZ(128|256)rrikz$",
3950 "^VGF2P8MULBZ(128|256)rrkz$")>;
3952 def SPRWriteResGroup411 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
3953 let Latency = 15;
3954 let NumMicroOps = 2;
3955 }
3956 def : InstRW<[SPRWriteResGroup411, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBZrm(b?)ik(z?)$",
3957 "^VGF2P8MULBZrmk(z?)$")>;
3959 def SPRWriteResGroup412 : SchedWriteRes<[SPRPort00]> {
3960 let Latency = 9;
3961 }
3962 def : InstRW<[SPRWriteResGroup412], (instregex "^VGF2P8AFFINE((INV)?)QBZrrik$")>;
3963 def : InstRW<[SPRWriteResGroup412], (instrs VGF2P8MULBZrrk)>;
3965 def SPRWriteResGroup413 : SchedWriteRes<[SPRPort00]> {
3966 let Latency = 10;
3967 }
3968 def : InstRW<[SPRWriteResGroup413], (instregex "^VGF2P8AFFINE((INV)?)QBZrrikz$")>;
3969 def : InstRW<[SPRWriteResGroup413], (instrs VGF2P8MULBZrrkz)>;
3971 def SPRWriteResGroup414 : SchedWriteRes<[SPRPort01_05, SPRPort05]> {
3972 let ReleaseAtCycles = [1, 2];
3973 let Latency = 5;
3974 let NumMicroOps = 3;
3975 }
3976 def : InstRW<[SPRWriteResGroup414], (instregex "^VH(ADD|SUB)P(D|S)rr$")>;
3978 def SPRWriteResGroup415 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort02_03_10]> {
3979 let Latency = 7;
3980 let NumMicroOps = 3;
3981 }
3982 def : InstRW<[SPRWriteResGroup415], (instrs VLDMXCSR)>;
3984 def SPRWriteResGroup416 : SchedWriteRes<[SPRPort01, SPRPort01_05, SPRPort02_03, SPRPort02_03_10, SPRPort04, SPRPort04_09, SPRPort05, SPRPort06]> {
3985 let ReleaseAtCycles = [1, 1, 1, 8, 1, 1, 2, 3];
3986 let Latency = 40;
3987 let NumMicroOps = 18;
3988 }
3989 def : InstRW<[SPRWriteResGroup416], (instrs VMCLEARm)>;
3991 def SPRWriteResGroup417 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10]> {
3992 let Latency = 11;
3993 let NumMicroOps = 2;
3994 }
3995 def : InstRW<[SPRWriteResGroup417], (instregex "^VMOVDQU(8|16)Z(128|256)rmk(z?)$",
3996 "^VMOVSHZrmk(z?)$")>;
3997 def : InstRW<[SPRWriteResGroup417, ReadAfterVecXLd], (instregex "^VP(ADD|SUB)(B|W)Z128rmk(z?)$",
3998 "^VPBLENDM(B|W)Z128rmk(z?)$")>;
3999 def : InstRW<[SPRWriteResGroup417, ReadAfterVecYLd], (instregex "^VP(ADD|SUB)(B|W)Z256rmk(z?)$",
4000 "^VPBLENDM(B|W)Z256rmk(z?)$")>;
4002 def SPRWriteResGroup418 : SchedWriteRes<[SPRPort00_01_05]> {
4003 let Latency = 3;
4004 }
4005 def : InstRW<[SPRWriteResGroup418], (instregex "^VMOVDQU(8|16)Z(128|256)rrk(z?)((_REV)?)$",
4006 "^VMOVSHZrrk(z?)((_REV)?)$",
4007 "^VP(ADD|SUB)(B|W)Z(128|256)rrk(z?)$",
4008 "^VPBLENDM(B|W)Z(128|256)rrk(z?)$",
4009 "^VPMOVM2(B|W)Z(128|256)rk$")>;
4011 def SPRWriteResGroup419 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> {
4012 let ReleaseAtCycles = [1, 2, 2];
4013 let Latency = 12;
4014 let NumMicroOps = 5;
4015 }
4016 def : InstRW<[SPRWriteResGroup419], (instrs VMOVDQU8Zmrk)>;
4018 def SPRWriteResGroup420 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4019 let Latency = 477;
4020 let NumMicroOps = 2;
4021 }
4022 def : InstRW<[SPRWriteResGroup420], (instrs VMOVNTDQZ128mr)>;
4024 def SPRWriteResGroup421 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4025 let Latency = 470;
4026 let NumMicroOps = 2;
4027 }
4028 def : InstRW<[SPRWriteResGroup421], (instrs VMOVNTDQZ256mr,
4029 VMOVNTPSmr)>;
4031 def SPRWriteResGroup422 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4032 let Latency = 473;
4033 let NumMicroOps = 2;
4034 }
4035 def : InstRW<[SPRWriteResGroup422], (instregex "^VMOVNT(PD|DQZ)mr$")>;
4037 def SPRWriteResGroup423 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4038 let Latency = 521;
4039 let NumMicroOps = 2;
4040 }
4041 def : InstRW<[SPRWriteResGroup423], (instrs VMOVNTDQmr)>;
4043 def SPRWriteResGroup424 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4044 let Latency = 550;
4045 let NumMicroOps = 2;
4046 }
4047 def : InstRW<[SPRWriteResGroup424], (instrs VMOVNTPDZ128mr)>;
4049 def SPRWriteResGroup425 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4050 let Latency = 474;
4051 let NumMicroOps = 2;
4052 }
4053 def : InstRW<[SPRWriteResGroup425], (instrs VMOVNTPDZ256mr)>;
4055 def SPRWriteResGroup426 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4056 let Latency = 464;
4057 let NumMicroOps = 2;
4058 }
4059 def : InstRW<[SPRWriteResGroup426], (instrs VMOVNTPDZmr)>;
4061 def SPRWriteResGroup427 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4062 let Latency = 494;
4063 let NumMicroOps = 2;
4064 }
4065 def : InstRW<[SPRWriteResGroup427], (instrs VMOVNTPSYmr)>;
4067 def SPRWriteResGroup428 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4068 let Latency = 475;
4069 let NumMicroOps = 2;
4070 }
4071 def : InstRW<[SPRWriteResGroup428], (instrs VMOVNTPSZ128mr)>;
4073 def SPRWriteResGroup429 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4074 let Latency = 476;
4075 let NumMicroOps = 2;
4076 }
4077 def : InstRW<[SPRWriteResGroup429], (instrs VMOVNTPSZ256mr)>;
4079 def SPRWriteResGroup430 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4080 let Latency = 471;
4081 let NumMicroOps = 2;
4082 }
4083 def : InstRW<[SPRWriteResGroup430], (instrs VMOVNTPSZmr)>;
4085 def SPRWriteResGroup431 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> {
4086 let ReleaseAtCycles = [3, 1, 8];
4087 let Latency = 10;
4088 let NumMicroOps = 12;
4089 }
4090 def : InstRW<[SPRWriteResGroup431, ReadAfterVecXLd], (instregex "^VP2INTERSECTDZ128rm(b?)$")>;
4091 def : InstRW<[SPRWriteResGroup431, ReadAfterVecYLd], (instregex "^VP2INTERSECTQZ256rm(b?)$")>;
4093 def SPRWriteResGroup432 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
4094 let ReleaseAtCycles = [4, 8];
4095 let Latency = 10;
4096 let NumMicroOps = 12;
4097 }
4098 def : InstRW<[SPRWriteResGroup432], (instrs VP2INTERSECTDZ128rr,
4099 VP2INTERSECTQZ256rr)>;
4101 def SPRWriteResGroup433 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10, SPRPort05]> {
4102 let ReleaseAtCycles = [1, 8, 7, 2, 1, 11];
4103 let Latency = 27;
4104 let NumMicroOps = 30;
4105 }
4106 def : InstRW<[SPRWriteResGroup433, ReadAfterVecYLd], (instregex "^VP2INTERSECTDZ256rm(b?)$")>;
4108 def SPRWriteResGroup434 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort05]> {
4109 let ReleaseAtCycles = [1, 8, 8, 2, 11];
4110 let Latency = 27;
4111 let NumMicroOps = 30;
4112 }
4113 def : InstRW<[SPRWriteResGroup434], (instrs VP2INTERSECTDZ256rr)>;
4115 def SPRWriteResGroup435 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10, SPRPort05]> {
4116 let ReleaseAtCycles = [13, 9, 1, 23];
4117 let Latency = 40;
4118 let NumMicroOps = 46;
4119 }
4120 def : InstRW<[SPRWriteResGroup435, ReadAfterVecYLd], (instregex "^VP2INTERSECTDZrm(b?)$")>;
4122 def SPRWriteResGroup436 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
4123 let ReleaseAtCycles = [13, 10, 23];
4124 let Latency = 40;
4125 let NumMicroOps = 46;
4126 }
4127 def : InstRW<[SPRWriteResGroup436], (instrs VP2INTERSECTDZrr)>;
4129 def SPRWriteResGroup437 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> {
4130 let ReleaseAtCycles = [1, 4];
4131 let Latency = 6;
4132 let NumMicroOps = 5;
4133 }
4134 def : InstRW<[SPRWriteResGroup437, ReadAfterVecXLd], (instregex "^VP2INTERSECTQZ128rm(b?)$")>;
4136 def SPRWriteResGroup438 : SchedWriteRes<[SPRPort05]> {
4137 let ReleaseAtCycles = [4];
4138 let Latency = 6;
4139 let NumMicroOps = 4;
4140 }
4141 def : InstRW<[SPRWriteResGroup438], (instrs VP2INTERSECTQZ128rr)>;
4143 def SPRWriteResGroup439 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10, SPRPort05]> {
4144 let ReleaseAtCycles = [8, 7, 1, 14];
4145 let Latency = 29;
4146 let NumMicroOps = 30;
4147 }
4148 def : InstRW<[SPRWriteResGroup439, ReadAfterVecYLd], (instregex "^VP2INTERSECTQZrm(b?)$")>;
4150 def SPRWriteResGroup440 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
4151 let ReleaseAtCycles = [8, 8, 14];
4152 let Latency = 30;
4153 let NumMicroOps = 30;
4154 }
4155 def : InstRW<[SPRWriteResGroup440], (instrs VP2INTERSECTQZrr)>;
4157 def SPRWriteResGroup441 : SchedWriteRes<[SPRPort00_01]> {
4158 let Latency = 3;
4159 }
4160 def : InstRW<[SPRWriteResGroup441], (instregex "^VP(A|SU)BS(B|W)Z(128|256)rrk(z?)$",
4161 "^VPADD(U?)S(B|W)Z(128|256)rrk(z?)$",
4162 "^VPAVG(B|W)Z(128|256)rrk(z?)$",
4163 "^VPM(AX|IN)(SB|UW)Z(128|256)rrk(z?)$",
4164 "^VPM(AX|IN)(SW|UB)Z(128|256)rrk(z?)$",
4165 "^VPSH(L|R)DVWZ(128|256)rk(z?)$",
4166 "^VPS(L|R)LVWZ(128|256)rrk(z?)$",
4167 "^VPS(L|R)LWZ(128|256)rik(z?)$",
4168 "^VPSRAVWZ(128|256)rrk(z?)$",
4169 "^VPSRAWZ(128|256)rik(z?)$",
4170 "^VPSUBUS(B|W)Z(128|256)rrk(z?)$")>;
4172 def SPRWriteResGroup442 : SchedWriteRes<[SPRPort01_05, SPRPort02_03_10]> {
4173 let Latency = 9;
4174 let NumMicroOps = 2;
4175 }
4176 def : InstRW<[SPRWriteResGroup442, ReadAfterVecYLd], (instregex "^VSHUFP(D|S)Yrmi$",
4177 "^VSHUFP(D|S)Z256rm(bi|ik)$",
4178 "^VSHUFP(D|S)Z256rmbik(z?)$",
4179 "^VSHUFP(D|S)Z256rmi((kz)?)$")>;
4180 def : InstRW<[SPRWriteResGroup442, ReadAfterVecYLd], (instrs VPBLENDWYrmi)>;
4182 def SPRWriteResGroup443 : SchedWriteRes<[SPRPort00, SPRPort05]> {
4183 let Latency = 6;
4184 let NumMicroOps = 2;
4185 }
4186 def : InstRW<[SPRWriteResGroup443], (instregex "^VPBROADCASTM(B2Q|W2D)Z(128|256)rr$",
4187 "^VPBROADCASTM(B2Q|W2D)Zrr$",
4188 "^VP(ERM|SRA)WZrrk(z?)$",
4189 "^VPSHUFBITQMBZ(128|256)rr$",
4190 "^VPS(L|R)LWZrrk(z?)$")>;
4191 def : InstRW<[SPRWriteResGroup443], (instrs VPSHUFBITQMBZrr)>;
4193 def SPRWriteResGroup444 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4194 let ReleaseAtCycles = [1, 1, 1, 2, 1];
4195 let Latency = 12;
4196 let NumMicroOps = 6;
4197 }
4198 def : InstRW<[SPRWriteResGroup444], (instregex "^VPCOMPRESS(B|W)Z(128|256)mr$")>;
4199 def : InstRW<[SPRWriteResGroup444], (instrs VPCOMPRESSWZmr)>;
4201 def SPRWriteResGroup445 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4202 let ReleaseAtCycles = [1, 1, 1, 2, 1];
4203 let Latency = 14;
4204 let NumMicroOps = 6;
4205 }
4206 def : InstRW<[SPRWriteResGroup445], (instregex "^VPCOMPRESS(B|W)Z(128|256)mrk$")>;
4207 def : InstRW<[SPRWriteResGroup445], (instrs VPCOMPRESSWZmrk)>;
4209 def SPRWriteResGroup446 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4210 let ReleaseAtCycles = [1, 1, 2, 2, 2];
4211 let Latency = 12;
4212 let NumMicroOps = 8;
4213 }
4214 def : InstRW<[SPRWriteResGroup446], (instrs VPCOMPRESSBZmr)>;
4216 def SPRWriteResGroup447 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4217 let ReleaseAtCycles = [1, 1, 2, 2, 2];
4218 let Latency = 14;
4219 let NumMicroOps = 8;
4220 }
4221 def : InstRW<[SPRWriteResGroup447], (instrs VPCOMPRESSBZmrk)>;
4223 def SPRWriteResGroup448 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> {
4224 let ReleaseAtCycles = [5, 4, 1, 5];
4225 let Latency = 17;
4226 let NumMicroOps = 15;
4227 }
4228 def : InstRW<[SPRWriteResGroup448], (instregex "^VPCONFLICTDZ128rm((b|k|bk|kz)?)$")>;
4229 def : InstRW<[SPRWriteResGroup448], (instrs VPCONFLICTDZ128rmbkz)>;
4231 def SPRWriteResGroup449 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
4232 let ReleaseAtCycles = [5, 5, 5];
4233 let Latency = 12;
4234 let NumMicroOps = 15;
4235 }
4236 def : InstRW<[SPRWriteResGroup449], (instregex "^VPCONFLICTDZ128rr((k|kz)?)$")>;
4238 def SPRWriteResGroup450 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
4239 let ReleaseAtCycles = [7, 5, 1, 1, 9];
4240 let Latency = 24;
4241 let NumMicroOps = 23;
4242 }
4243 def : InstRW<[SPRWriteResGroup450], (instregex "^VPCONFLICTDZ256rm((b|k|bk|kz)?)$")>;
4244 def : InstRW<[SPRWriteResGroup450], (instrs VPCONFLICTDZ256rmbkz)>;
4246 def SPRWriteResGroup451 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
4247 let ReleaseAtCycles = [7, 6, 1, 9];
4248 let Latency = 17;
4249 let NumMicroOps = 23;
4250 }
4251 def : InstRW<[SPRWriteResGroup451], (instregex "^VPCONFLICTDZ256rr((k|kz)?)$")>;
4253 def SPRWriteResGroup452 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10, SPRPort05]> {
4254 let ReleaseAtCycles = [11, 8, 1, 17];
4255 let Latency = 33;
4256 let NumMicroOps = 37;
4257 }
4258 def : InstRW<[SPRWriteResGroup452], (instregex "^VPCONFLICTDZrm((b|k|bk|kz)?)$")>;
4259 def : InstRW<[SPRWriteResGroup452], (instrs VPCONFLICTDZrmbkz)>;
4261 def SPRWriteResGroup453 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
4262 let ReleaseAtCycles = [11, 9, 17];
4263 let Latency = 26;
4264 let NumMicroOps = 37;
4265 }
4266 def : InstRW<[SPRWriteResGroup453], (instregex "^VPCONFLICTDZrr((kz)?)$")>;
4268 def SPRWriteResGroup454 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
4269 let ReleaseAtCycles = [11, 9, 17];
4270 let Latency = 25;
4271 let NumMicroOps = 37;
4272 }
4273 def : InstRW<[SPRWriteResGroup454], (instrs VPCONFLICTDZrrk)>;
4275 def SPRWriteResGroup455 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> {
4276 let ReleaseAtCycles = [1, 1, 2];
4277 let Latency = 11;
4278 let NumMicroOps = 4;
4279 }
4280 def : InstRW<[SPRWriteResGroup455], (instregex "^VPCONFLICTQZ128rm((b|k|bk|kz)?)$")>;
4281 def : InstRW<[SPRWriteResGroup455], (instrs VPCONFLICTQZ128rmbkz)>;
4282 def : InstRW<[SPRWriteResGroup455, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZ128rm$")>;
4284 def SPRWriteResGroup456 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
4285 let ReleaseAtCycles = [1, 2];
4286 let Latency = 4;
4287 let NumMicroOps = 3;
4288 }
4289 def : InstRW<[SPRWriteResGroup456], (instregex "^VPCONFLICTQZ128rr((k|kz)?)$")>;
4291 def SPRWriteResGroup457 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> {
4292 let ReleaseAtCycles = [5, 4, 1, 5];
4293 let Latency = 20;
4294 let NumMicroOps = 15;
4295 }
4296 def : InstRW<[SPRWriteResGroup457], (instregex "^VPCONFLICTQZ256rm((b|k|bk|kz)?)$")>;
4297 def : InstRW<[SPRWriteResGroup457], (instrs VPCONFLICTQZ256rmbkz)>;
4299 def SPRWriteResGroup458 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
4300 let ReleaseAtCycles = [5, 5, 5];
4301 let Latency = 13;
4302 let NumMicroOps = 15;
4303 }
4304 def : InstRW<[SPRWriteResGroup458], (instregex "^VPCONFLICTQZ256rr((k|kz)?)$")>;
4306 def SPRWriteResGroup459 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10, SPRPort05]> {
4307 let ReleaseAtCycles = [7, 5, 1, 9];
4308 let Latency = 23;
4309 let NumMicroOps = 22;
4310 }
4311 def : InstRW<[SPRWriteResGroup459], (instregex "^VPCONFLICTQZrm((b|k|bk|kz)?)$")>;
4312 def : InstRW<[SPRWriteResGroup459], (instrs VPCONFLICTQZrmbkz)>;
4314 def SPRWriteResGroup460 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
4315 let ReleaseAtCycles = [7, 6, 9];
4316 let Latency = 17;
4317 let NumMicroOps = 22;
4318 }
4319 def : InstRW<[SPRWriteResGroup460], (instregex "^VPCONFLICTQZrr((kz)?)$")>;
4321 def SPRWriteResGroup461 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
4322 let ReleaseAtCycles = [7, 6, 9];
4323 let Latency = 16;
4324 let NumMicroOps = 22;
4325 }
4326 def : InstRW<[SPRWriteResGroup461], (instrs VPCONFLICTQZrrk)>;
4328 def SPRWriteResGroup462 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> {
4329 let ReleaseAtCycles = [1, 1, 2];
4330 let Latency = 13;
4331 let NumMicroOps = 4;
4332 }
4333 def : InstRW<[SPRWriteResGroup462, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZ128rmk(z?)$")>;
4334 def : InstRW<[SPRWriteResGroup462, ReadAfterVecYLd], (instrs VPERMT2WZ128rm)>;
4336 def SPRWriteResGroup463 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
4337 let ReleaseAtCycles = [1, 2];
4338 let Latency = 5;
4339 let NumMicroOps = 3;
4340 }
4341 def : InstRW<[SPRWriteResGroup463], (instregex "^VPERM(I|T)2BZ(128|256)rr$")>;
4343 def SPRWriteResGroup464 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
4344 let ReleaseAtCycles = [1, 2];
4345 let Latency = 7;
4346 let NumMicroOps = 3;
4347 }
4348 def : InstRW<[SPRWriteResGroup464], (instregex "^VPERM(I|T)2BZ(128|256)rrk(z?)$",
4349 "^VPERM(I|T)2WZ(128|256)rr$")>;
4351 def SPRWriteResGroup465 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> {
4352 let ReleaseAtCycles = [1, 1, 2];
4353 let Latency = 12;
4354 let NumMicroOps = 4;
4355 }
4356 def : InstRW<[SPRWriteResGroup465, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZ256rm$")>;
4358 def SPRWriteResGroup466 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> {
4359 let ReleaseAtCycles = [1, 1, 2];
4360 let Latency = 14;
4361 let NumMicroOps = 4;
4362 }
4363 def : InstRW<[SPRWriteResGroup466, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZ256rmk(z?)$")>;
4364 def : InstRW<[SPRWriteResGroup466, ReadAfterVecYLd], (instrs VPERMI2WZ128rm,
4365 VPERMT2WZ256rm)>;
4367 def SPRWriteResGroup467 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_10, SPRPort05]> {
4368 let ReleaseAtCycles = [1, 1, 2];
4369 let Latency = 12;
4370 let NumMicroOps = 4;
4371 }
4372 def : InstRW<[SPRWriteResGroup467, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZrm$")>;
4374 def SPRWriteResGroup468 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_10, SPRPort05]> {
4375 let ReleaseAtCycles = [1, 1, 2];
4376 let Latency = 14;
4377 let NumMicroOps = 4;
4378 }
4379 def : InstRW<[SPRWriteResGroup468, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZrmk(z?)$")>;
4380 def : InstRW<[SPRWriteResGroup468, ReadAfterVecYLd], (instrs VPERMT2WZrm)>;
4382 def SPRWriteResGroup469 : SchedWriteRes<[SPRPort00_05, SPRPort05]> {
4383 let ReleaseAtCycles = [1, 2];
4384 let Latency = 5;
4385 let NumMicroOps = 3;
4386 }
4387 def : InstRW<[SPRWriteResGroup469], (instregex "^VPERM(I|T)2BZrr$")>;
4389 def SPRWriteResGroup470 : SchedWriteRes<[SPRPort00_05, SPRPort05]> {
4390 let ReleaseAtCycles = [1, 2];
4391 let Latency = 7;
4392 let NumMicroOps = 3;
4393 }
4394 def : InstRW<[SPRWriteResGroup470], (instregex "^VPERM(I|T)2BZrrk(z?)$",
4395 "^VPERM(I|T)2WZrr$")>;
4397 def SPRWriteResGroup471 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> {
4398 let ReleaseAtCycles = [1, 1, 2];
4399 let Latency = 16;
4400 let NumMicroOps = 4;
4401 }
4402 def : InstRW<[SPRWriteResGroup471, ReadAfterVecYLd], (instregex "^VPERMI2WZ128rmk(z?)$",
4403 "^VPERMT2WZ256rmk(z?)$")>;
4405 def SPRWriteResGroup472 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
4406 let ReleaseAtCycles = [1, 2];
4407 let Latency = 9;
4408 let NumMicroOps = 3;
4409 }
4410 def : InstRW<[SPRWriteResGroup472], (instregex "^VPERM(I|T)2WZ(128|256)rrk(z?)$")>;
4412 def SPRWriteResGroup473 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> {
4413 let ReleaseAtCycles = [1, 1, 2];
4414 let Latency = 15;
4415 let NumMicroOps = 4;
4416 }
4417 def : InstRW<[SPRWriteResGroup473, ReadAfterVecYLd], (instregex "^VPERMT2WZ128rmk(z?)$")>;
4418 def : InstRW<[SPRWriteResGroup473, ReadAfterVecYLd], (instrs VPERMI2WZ256rm)>;
4420 def SPRWriteResGroup474 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> {
4421 let ReleaseAtCycles = [1, 1, 2];
4422 let Latency = 17;
4423 let NumMicroOps = 4;
4424 }
4425 def : InstRW<[SPRWriteResGroup474, ReadAfterVecYLd], (instregex "^VPERMI2WZ256rmk(z?)$")>;
4427 def SPRWriteResGroup475 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_10, SPRPort05]> {
4428 let ReleaseAtCycles = [1, 1, 2];
4429 let Latency = 15;
4430 let NumMicroOps = 4;
4431 }
4432 def : InstRW<[SPRWriteResGroup475, ReadAfterVecYLd], (instrs VPERMI2WZrm)>;
4434 def SPRWriteResGroup476 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_10, SPRPort05]> {
4435 let ReleaseAtCycles = [1, 1, 2];
4436 let Latency = 17;
4437 let NumMicroOps = 4;
4438 }
4439 def : InstRW<[SPRWriteResGroup476, ReadAfterVecYLd], (instregex "^VPERMI2WZrmk(z?)$")>;
4441 def SPRWriteResGroup477 : SchedWriteRes<[SPRPort00_05, SPRPort05]> {
4442 let ReleaseAtCycles = [1, 2];
4443 let Latency = 9;
4444 let NumMicroOps = 3;
4445 }
4446 def : InstRW<[SPRWriteResGroup477], (instregex "^VPERM(I|T)2WZrrk(z?)$")>;
4448 def SPRWriteResGroup478 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_10, SPRPort05]> {
4449 let ReleaseAtCycles = [1, 1, 2];
4450 let Latency = 16;
4451 let NumMicroOps = 4;
4452 }
4453 def : InstRW<[SPRWriteResGroup478, ReadAfterVecYLd], (instregex "^VPERMT2WZrmk(z?)$")>;
4455 def SPRWriteResGroup479 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
4456 let Latency = 10;
4457 let NumMicroOps = 3;
4458 }
4459 def : InstRW<[SPRWriteResGroup479, ReadAfterVecYLd], (instrs VPERMWZ128rm)>;
4461 def SPRWriteResGroup480 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
4462 let Latency = 13;
4463 let NumMicroOps = 3;
4464 }
4465 def : InstRW<[SPRWriteResGroup480, ReadAfterVecYLd], (instregex "^VPERMWZ(128|256)rmk(z?)$")>;
4467 def SPRWriteResGroup481 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
4468 let Latency = 4;
4469 let NumMicroOps = 2;
4470 }
4471 def : InstRW<[SPRWriteResGroup481], (instregex "^VPERMWZ(128|256)rr$")>;
4473 def SPRWriteResGroup482 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> {
4474 let Latency = 11;
4475 let NumMicroOps = 3;
4476 }
4477 def : InstRW<[SPRWriteResGroup482, ReadAfterVecYLd], (instrs VPERMWZ256rm)>;
4479 def SPRWriteResGroup483 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
4480 let Latency = 11;
4481 let NumMicroOps = 3;
4482 }
4483 def : InstRW<[SPRWriteResGroup483, ReadAfterVecYLd], (instrs VPERMWZrm)>;
4485 def SPRWriteResGroup484 : SchedWriteRes<[SPRPort05]> {
4486 let ReleaseAtCycles = [2];
4487 let Latency = 8;
4488 let NumMicroOps = 2;
4489 }
4490 def : InstRW<[SPRWriteResGroup484], (instregex "^VPEXPAND(B|W)Z(128|256)rrk(z?)$",
4491 "^VPEXPAND(B|W)Zrrk(z?)$")>;
4493 def SPRWriteResGroup485 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10]> {
4494 let ReleaseAtCycles = [1, 2, 1];
4495 let Latency = 10;
4496 let NumMicroOps = 4;
4497 }
4498 def : InstRW<[SPRWriteResGroup485, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)SWYrm$")>;
4500 def SPRWriteResGroup486 : SchedWriteRes<[SPRPort00_01]> {
4501 let Latency = 7;
4502 }
4503 def : InstRW<[SPRWriteResGroup486], (instregex "^VPMADDUBSWZ(128|256)rrk(z?)$",
4504 "^VPMULH((U|RS)?)WZ(128|256)rrk(z?)$",
4505 "^VPMULLWZ(128|256)rrk(z?)$")>;
4507 def SPRWriteResGroup487 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
4508 let Latency = 14;
4509 let NumMicroOps = 2;
4510 }
4511 def : InstRW<[SPRWriteResGroup487, ReadAfterVecYLd], (instregex "^VPMADDUBSWZrmk(z?)$",
4512 "^VPMULH((U|RS)?)WZrmk(z?)$",
4513 "^VPMULLWZrmk(z?)$")>;
4515 def SPRWriteResGroup488 : SchedWriteRes<[SPRPort00]> {
4516 let Latency = 7;
4517 }
4518 def : InstRW<[SPRWriteResGroup488], (instregex "^VPMADDUBSWZrrk(z?)$",
4519 "^VPMULH((U|RS)?)WZrrk(z?)$",
4520 "^VPMULLWZrrk(z?)$")>;
4522 def SPRWriteResGroup489 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4523 let Latency = 12;
4524 let NumMicroOps = 4;
4525 }
4526 def : InstRW<[SPRWriteResGroup489], (instregex "^VPMOV((US)?)DBZ(128|256)mr$",
4527 "^VPMOV((S|US)?)(D|Q)WZ(128|256)mr$",
4528 "^VPMOV(Q|W|SD|SW)BZ256mr$",
4529 "^VPMOV(W|SD)BZ128mr$",
4530 "^VPMOV(U?)SQBZ256mr$",
4531 "^VPMOV(U?)SQDZ(128|256)mr$",
4532 "^VPMOV(U?)SWBZ128mr$")>;
4533 def : InstRW<[SPRWriteResGroup489], (instrs VPMOVUSWBZ256mr)>;
4535 def SPRWriteResGroup490 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4536 let Latency = 13;
4537 let NumMicroOps = 4;
4538 }
4539 def : InstRW<[SPRWriteResGroup490], (instregex "^VPMOV(D|Q|W|SQ|SW)BZ128mrk$",
4540 "^VPMOV((S|US)?)(D|Q)WZ128mrk$",
4541 "^VPMOV(U?)S(DB|QD)Z128mrk$",
4542 "^VPMOVUS(Q|W)BZ128mrk$")>;
4544 def SPRWriteResGroup491 : SchedWriteRes<[SPRPort01_05, SPRPort05]> {
4545 let Latency = 2;
4546 let NumMicroOps = 2;
4547 }
4548 def : InstRW<[SPRWriteResGroup491], (instregex "^VPMOV(D|Q|W|SQ|SW)BZ128rr$",
4549 "^VPMOV((S|US)?)(D|Q)WZ128rr$",
4550 "^VPMOV(U?)S(DB|QD)Z128rr$",
4551 "^VPMOV(U?)SQDZ128rrk(z?)$",
4552 "^VPMOVUS(Q|W)BZ128rr$")>;
4554 def SPRWriteResGroup492 : SchedWriteRes<[SPRPort01_05, SPRPort05]> {
4555 let Latency = 4;
4556 let NumMicroOps = 2;
4557 }
4558 def : InstRW<[SPRWriteResGroup492], (instregex "^VPMOV(D|Q|W|SQ|SW)BZ128rrk(z?)$",
4559 "^VPMOV(D|Q|W|SQ|SW)BZ256rr$",
4560 "^VPMOV((S|US)?)(D|Q)WZ128rrk(z?)$",
4561 "^VPMOV((S|US)?)(D|Q)WZ256rr$",
4562 "^VPMOV(U?)SDBZ128rrk(z?)$",
4563 "^VPMOV(U?)S(DB|QD)Z256rr$",
4564 "^VPMOV(U?)SQDZ256rrk(z?)$",
4565 "^VPMOVUS(Q|W)BZ128rrk(z?)$",
4566 "^VPMOVUS(Q|W)BZ256rr$")>;
4568 def SPRWriteResGroup493 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4569 let Latency = 15;
4570 let NumMicroOps = 4;
4571 }
4572 def : InstRW<[SPRWriteResGroup493], (instregex "^VPMOV(D|Q|W|SQ|SW)BZ256mrk$",
4573 "^VPMOV((S|US)?)(D|Q)WZ256mrk$",
4574 "^VPMOV(U?)S(DB|QD)Z256mrk$",
4575 "^VPMOVUS(Q|W)BZ256mrk$")>;
4577 def SPRWriteResGroup494 : SchedWriteRes<[SPRPort01_05, SPRPort05]> {
4578 let Latency = 6;
4579 let NumMicroOps = 2;
4580 }
4581 def : InstRW<[SPRWriteResGroup494], (instregex "^VPMOV(D|Q|W|SQ|SW)BZ256rrk(z?)$",
4582 "^VPMOV((S|US)?)(D|Q)WZ256rrk(z?)$",
4583 "^VPMOV(U?)SDBZ256rrk(z?)$",
4584 "^VPMOVUS(Q|W)BZ256rrk(z?)$")>;
4586 def SPRWriteResGroup495 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4587 let Latency = 20;
4588 let NumMicroOps = 4;
4589 }
4590 def : InstRW<[SPRWriteResGroup495], (instregex "^VPMOV((S|US)?)QBZ128mr$")>;
4592 def SPRWriteResGroup496 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> {
4593 let Latency = 14;
4594 let NumMicroOps = 3;
4595 }
4596 def : InstRW<[SPRWriteResGroup496], (instregex "^VPMOVQDZ((256)?)mrk$")>;
4598 def SPRWriteResGroup497 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> {
4599 let ReleaseAtCycles = [3, 1];
4600 let Latency = 23;
4601 let NumMicroOps = 4;
4602 }
4603 def : InstRW<[SPRWriteResGroup497, ReadAfterVecXLd], (instregex "^VPMULLQZ128rm((b|k|bk|kz)?)$")>;
4604 def : InstRW<[SPRWriteResGroup497, ReadAfterVecXLd], (instrs VPMULLQZ128rmbkz)>;
4605 def : InstRW<[SPRWriteResGroup497, ReadAfterVecYLd], (instregex "^VPMULLQZ256rm((b|k|bk|kz)?)$")>;
4606 def : InstRW<[SPRWriteResGroup497, ReadAfterVecYLd], (instrs VPMULLQZ256rmbkz)>;
4608 def SPRWriteResGroup498 : SchedWriteRes<[SPRPort00_01]> {
4609 let ReleaseAtCycles = [3];
4610 let Latency = 15;
4611 let NumMicroOps = 3;
4612 }
4613 def : InstRW<[SPRWriteResGroup498], (instregex "^VPMULLQZ(128|256)rr((k|kz)?)$")>;
4615 def SPRWriteResGroup499 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
4616 let ReleaseAtCycles = [3, 1];
4617 let Latency = 23;
4618 let NumMicroOps = 4;
4619 }
4620 def : InstRW<[SPRWriteResGroup499, ReadAfterVecYLd], (instregex "^VPMULLQZrm((b|k|bk|kz)?)$")>;
4621 def : InstRW<[SPRWriteResGroup499, ReadAfterVecYLd], (instrs VPMULLQZrmbkz)>;
4623 def SPRWriteResGroup500 : SchedWriteRes<[SPRPort00]> {
4624 let ReleaseAtCycles = [3];
4625 let Latency = 15;
4626 let NumMicroOps = 3;
4627 }
4628 def : InstRW<[SPRWriteResGroup500], (instregex "^VPMULLQZrr((k|kz)?)$")>;
4630 def SPRWriteResGroup501 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> {
4631 let ReleaseAtCycles = [1, 1, 1, 4, 4];
4632 let Latency = 12;
4633 let NumMicroOps = 11;
4634 }
4635 def : InstRW<[SPRWriteResGroup501], (instregex "^VPSCATTER(D|Q)QZ256mr$",
4636 "^VSCATTER(D|Q)PDZ256mr$")>;
4637 def : InstRW<[SPRWriteResGroup501], (instrs VPSCATTERDDZ128mr,
4638 VPSCATTERQDZ256mr,
4639 VSCATTERDPSZ128mr,
4640 VSCATTERQPSZ256mr)>;
4642 def SPRWriteResGroup502 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> {
4643 let ReleaseAtCycles = [1, 1, 1, 8, 8];
4644 let Latency = 12;
4645 let NumMicroOps = 19;
4646 }
4647 def : InstRW<[SPRWriteResGroup502], (instrs VPSCATTERDDZ256mr,
4648 VSCATTERDPSZ256mr)>;
4650 def SPRWriteResGroup503 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> {
4651 let ReleaseAtCycles = [2, 1, 16, 16];
4652 let Latency = 19;
4653 let NumMicroOps = 35;
4654 }
4655 def : InstRW<[SPRWriteResGroup503], (instrs VPSCATTERDDZmr,
4656 VSCATTERDPSZmr)>;
4658 def SPRWriteResGroup504 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> {
4659 let ReleaseAtCycles = [1, 1, 1, 2, 2];
4660 let Latency = 12;
4661 let NumMicroOps = 7;
4662 }
4663 def : InstRW<[SPRWriteResGroup504], (instregex "^VPSCATTER(D|Q)QZ128mr$",
4664 "^VSCATTER(D|Q)PDZ128mr$")>;
4665 def : InstRW<[SPRWriteResGroup504], (instrs VPSCATTERQDZ128mr,
4666 VSCATTERQPSZ128mr)>;
4668 def SPRWriteResGroup505 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> {
4669 let ReleaseAtCycles = [2, 1, 8, 8];
4670 let Latency = 12;
4671 let NumMicroOps = 19;
4672 }
4673 def : InstRW<[SPRWriteResGroup505], (instregex "^VPSCATTER(D|Q)QZmr$",
4674 "^VSCATTER(D|Q)PDZmr$")>;
4675 def : InstRW<[SPRWriteResGroup505], (instrs VPSCATTERQDZmr,
4676 VSCATTERQPSZmr)>;
4678 def SPRWriteResGroup506 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> {
4679 let Latency = 8;
4680 let NumMicroOps = 2;
4681 }
4682 def : InstRW<[SPRWriteResGroup506, ReadAfterVecXLd], (instregex "^VPSH(L|R)D(D|Q)Z128rmbi$",
4683 "^VPSH(L|R)D(D|Q|W)Z128rmi$",
4684 "^VPSH(L|R)DV(D|Q|W)Z128m$",
4685 "^VPSH(L|R)DV(D|Q)Z128m(b|k|kz)$",
4686 "^VPSH(L|R)DV(D|Q)Z128mbk(z?)$")>;
4688 def SPRWriteResGroup507 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10]> {
4689 let Latency = 9;
4690 let NumMicroOps = 3;
4691 }
4692 def : InstRW<[SPRWriteResGroup507, ReadAfterVecXLd], (instregex "^VPSH(L|R)D(D|Q)Z128rm(b?)ik(z?)$")>;
4694 def SPRWriteResGroup508 : SchedWriteRes<[SPRPort00_01]>;
4695 def : InstRW<[SPRWriteResGroup508], (instregex "^VPSH(L|R)D(D|Q|W)Z(128|256)rri$",
4696 "^VPSH(L|R)DV(D|Q|W)Z(128|256)r$",
4697 "^VPSH(L|R)DV(D|Q)Z(128|256)rk(z?)$")>;
4699 def SPRWriteResGroup509 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05]> {
4700 let Latency = 2;
4701 let NumMicroOps = 2;
4702 }
4703 def : InstRW<[SPRWriteResGroup509], (instregex "^VPSH(L|R)D(D|Q)Z(128|256)rrik(z?)$")>;
4705 def SPRWriteResGroup510 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> {
4706 let Latency = 9;
4707 let NumMicroOps = 2;
4708 }
4709 def : InstRW<[SPRWriteResGroup510, ReadAfterVecYLd], (instregex "^VPSH(L|R)D(D|Q)Z256rmbi$",
4710 "^VPSH(L|R)D(D|Q|W)Z256rmi$",
4711 "^VPSH(L|R)DV(D|Q|W)Z256m$",
4712 "^VPSH(L|R)DV(D|Q)Z256m(b|k|kz)$",
4713 "^VPSH(L|R)DV(D|Q)Z256mbk(z?)$")>;
4715 def SPRWriteResGroup511 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10]> {
4716 let Latency = 10;
4717 let NumMicroOps = 3;
4718 }
4719 def : InstRW<[SPRWriteResGroup511, ReadAfterVecYLd], (instregex "^VPSH(L|R)D(D|Q)Z256rm(b?)ik(z?)$")>;
4721 def SPRWriteResGroup512 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
4722 let Latency = 9;
4723 let NumMicroOps = 2;
4724 }
4725 def : InstRW<[SPRWriteResGroup512, ReadAfterVecYLd], (instregex "^VPSH(L|R)D(D|Q)Zrmbi$",
4726 "^VPSH(L|R)D(D|Q|W)Zrmi$",
4727 "^VPSH(L|R)DV(D|Q|W)Zm$",
4728 "^VPSH(L|R)DV(D|Q)Zm(b|k|kz)$",
4729 "^VPSH(L|R)DV(D|Q)Zmbk(z?)$")>;
4731 def SPRWriteResGroup513 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10]> {
4732 let Latency = 10;
4733 let NumMicroOps = 3;
4734 }
4735 def : InstRW<[SPRWriteResGroup513, ReadAfterVecYLd], (instregex "^VPSH(L|R)D(D|Q)Zrm(b?)ik(z?)$")>;
4737 def SPRWriteResGroup514 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
4738 let Latency = 2;
4739 let NumMicroOps = 2;
4740 }
4741 def : InstRW<[SPRWriteResGroup514], (instregex "^VPSH(L|R)D(D|Q)Zrrik(z?)$")>;
4743 def SPRWriteResGroup515 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10]> {
4744 let Latency = 11;
4745 let NumMicroOps = 3;
4746 }
4747 def : InstRW<[SPRWriteResGroup515, ReadAfterVecXLd], (instregex "^VPSH(L|R)DWZ128rmik(z?)$")>;
4749 def SPRWriteResGroup516 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05]> {
4750 let Latency = 4;
4751 let NumMicroOps = 2;
4752 }
4753 def : InstRW<[SPRWriteResGroup516], (instregex "^VPSH(L|R)DWZ(128|256)rrik(z?)$")>;
4755 def SPRWriteResGroup517 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10]> {
4756 let Latency = 12;
4757 let NumMicroOps = 3;
4758 }
4759 def : InstRW<[SPRWriteResGroup517, ReadAfterVecYLd], (instregex "^VPSH(L|R)DWZ256rmik(z?)$")>;
4761 def SPRWriteResGroup518 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10]> {
4762 let Latency = 12;
4763 let NumMicroOps = 3;
4764 }
4765 def : InstRW<[SPRWriteResGroup518, ReadAfterVecYLd], (instregex "^VPSH(L|R)DWZrmik(z?)$")>;
4767 def SPRWriteResGroup519 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
4768 let Latency = 4;
4769 let NumMicroOps = 2;
4770 }
4771 def : InstRW<[SPRWriteResGroup519], (instregex "^VPSH(L|R)DWZrrik(z?)$")>;
4773 def SPRWriteResGroup520 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
4774 let Latency = 6;
4775 let NumMicroOps = 3;
4776 }
4777 def : InstRW<[SPRWriteResGroup520, ReadAfterVecXLd], (instrs VPSHUFBITQMBZ128rm)>;
4778 def : InstRW<[SPRWriteResGroup520, ReadAfterVecYLd], (instregex "^VPSHUFBITQMBZ((256)?)rm$")>;
4780 def SPRWriteResGroup521 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> {
4781 let Latency = 8;
4782 let NumMicroOps = 3;
4783 }
4784 def : InstRW<[SPRWriteResGroup521, ReadAfterVecXLd], (instrs VPSHUFBITQMBZ128rmk)>;
4785 def : InstRW<[SPRWriteResGroup521, ReadAfterVecYLd], (instregex "^VPSHUFBITQMBZ((256)?)rmk$")>;
4787 def SPRWriteResGroup522 : SchedWriteRes<[SPRPort00_01, SPRPort01_05]> {
4788 let Latency = 4;
4789 let NumMicroOps = 2;
4790 }
4791 def : InstRW<[SPRWriteResGroup522], (instregex "^VPS(L|R)LWZ128rrk(z?)$",
4792 "^VPSRAWZ128rrk(z?)$")>;
4794 def SPRWriteResGroup523 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10]> {
4795 let ReleaseAtCycles = [2, 1, 1];
4796 let Latency = 16;
4797 let NumMicroOps = 4;
4798 }
4799 def : InstRW<[SPRWriteResGroup523, ReadAfterVecYLd], (instregex "^VR(CP|SQRT)PHZm(bk|kz)$",
4800 "^VR(CP|SQRT)PHZm(k|bkz)$")>;
4802 def SPRWriteResGroup524 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
4803 let ReleaseAtCycles = [2, 1];
4804 let Latency = 9;
4805 let NumMicroOps = 3;
4806 }
4807 def : InstRW<[SPRWriteResGroup524], (instregex "^VRCPPHZrk(z?)$")>;
4809 def SPRWriteResGroup525 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> {
4810 let ReleaseAtCycles = [3, 1];
4811 let Latency = 20;
4812 let NumMicroOps = 4;
4813 }
4814 def : InstRW<[SPRWriteResGroup525, ReadAfterVecXLd], (instregex "^VREDUCEPHZ128rm(b?)i$")>;
4815 def : InstRW<[SPRWriteResGroup525, ReadAfterVecXLd], (instrs VREDUCESHZrmi)>;
4816 def : InstRW<[SPRWriteResGroup525, ReadAfterVecYLd], (instregex "^VREDUCEPHZ256rm(b?)i$")>;
4818 def SPRWriteResGroup526 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> {
4819 let ReleaseAtCycles = [3, 1];
4820 let Latency = 22;
4821 let NumMicroOps = 4;
4822 }
4823 def : InstRW<[SPRWriteResGroup526, ReadAfterVecXLd], (instregex "^VREDUCEPHZ128rm(b?)ik(z?)$",
4824 "^VREDUCESHZrmik(z?)$")>;
4825 def : InstRW<[SPRWriteResGroup526, ReadAfterVecYLd], (instregex "^VREDUCEPHZ256rm(b?)ik(z?)$")>;
4827 def SPRWriteResGroup527 : SchedWriteRes<[SPRPort00_01]> {
4828 let ReleaseAtCycles = [3];
4829 let Latency = 13;
4830 let NumMicroOps = 3;
4831 }
4832 def : InstRW<[SPRWriteResGroup527], (instregex "^VREDUCEPHZ(128|256)rri$",
4833 "^VREDUCESHZrri(b?)$")>;
4835 def SPRWriteResGroup528 : SchedWriteRes<[SPRPort00_01]> {
4836 let ReleaseAtCycles = [3];
4837 let Latency = 16;
4838 let NumMicroOps = 3;
4839 }
4840 def : InstRW<[SPRWriteResGroup528], (instregex "^VREDUCEPHZ(128|256)rrik(z?)$",
4841 "^VREDUCESHZrri(bk|kz)$",
4842 "^VREDUCESHZrri(k|bkz)$")>;
4844 def SPRWriteResGroup529 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
4845 let ReleaseAtCycles = [3, 1];
4846 let Latency = 20;
4847 let NumMicroOps = 4;
4848 }
4849 def : InstRW<[SPRWriteResGroup529, ReadAfterVecYLd], (instregex "^VREDUCEPHZrm(b?)i$")>;
4851 def SPRWriteResGroup530 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
4852 let ReleaseAtCycles = [3, 1];
4853 let Latency = 22;
4854 let NumMicroOps = 4;
4855 }
4856 def : InstRW<[SPRWriteResGroup530, ReadAfterVecYLd], (instregex "^VREDUCEPHZrm(b?)ik(z?)$")>;
4858 def SPRWriteResGroup531 : SchedWriteRes<[SPRPort00]> {
4859 let ReleaseAtCycles = [3];
4860 let Latency = 13;
4861 let NumMicroOps = 3;
4862 }
4863 def : InstRW<[SPRWriteResGroup531], (instregex "^VREDUCEPHZrri(b?)$")>;
4865 def SPRWriteResGroup532 : SchedWriteRes<[SPRPort00]> {
4866 let ReleaseAtCycles = [3];
4867 let Latency = 16;
4868 let NumMicroOps = 3;
4869 }
4870 def : InstRW<[SPRWriteResGroup532], (instregex "^VREDUCEPHZrri(bk|kz)$",
4871 "^VREDUCEPHZrri(k|bkz)$")>;
4873 def SPRWriteResGroup533 : SchedWriteRes<[SPRPort00]> {
4874 let ReleaseAtCycles = [2];
4875 let Latency = 8;
4876 let NumMicroOps = 2;
4877 }
4878 def : InstRW<[SPRWriteResGroup533], (instregex "^VRNDSCALEP(D|S)Zrri((b|k|bk|kz)?)$",
4879 "^VRNDSCALEP(D|S)Zrribkz$")>;
4881 def SPRWriteResGroup534 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> {
4882 let ReleaseAtCycles = [2, 1];
4883 let Latency = 17;
4884 let NumMicroOps = 3;
4885 }
4886 def : InstRW<[SPRWriteResGroup534, ReadAfterVecXLd], (instregex "^VRNDSCALEPHZ128rm(b?)ik(z?)$",
4887 "^VRNDSCALESHZrmik(z?)_Int$",
4888 "^VSCALEFPHZ128rm(bk|kz)$",
4889 "^VSCALEFPHZ128rm(k|bkz)$")>;
4890 def : InstRW<[SPRWriteResGroup534, ReadAfterVecYLd], (instregex "^VRNDSCALEPHZ256rm(b?)ik(z?)$",
4891 "^VSCALEFPHZ256rm(bk|kz)$",
4892 "^VSCALEFPHZ256rm(k|bkz)$")>;
4893 def : InstRW<[SPRWriteResGroup534, ReadAfterVecLd], (instregex "^VSCALEFSHZrmk(z?)$")>;
4895 def SPRWriteResGroup535 : SchedWriteRes<[SPRPort00_01]> {
4896 let ReleaseAtCycles = [2];
4897 let Latency = 11;
4898 let NumMicroOps = 2;
4899 }
4900 def : InstRW<[SPRWriteResGroup535], (instregex "^VRNDSCALEPHZ(128|256)rrik(z?)$",
4901 "^VRNDSCALESHZrri(b?)k(z?)_Int$",
4902 "^VSCALEFPHZ(128|256)rrk(z?)$",
4903 "^VSCALEFSHZrrbk(z?)_Int$",
4904 "^VSCALEFSHZrrk(z?)$")>;
4906 def SPRWriteResGroup536 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
4907 let ReleaseAtCycles = [2, 1];
4908 let Latency = 17;
4909 let NumMicroOps = 3;
4910 }
4911 def : InstRW<[SPRWriteResGroup536, ReadAfterVecYLd], (instregex "^VRNDSCALEPHZrm(b?)ik(z?)$",
4912 "^VSCALEFPHZrm(bk|kz)$",
4913 "^VSCALEFPHZrm(k|bkz)$")>;
4915 def SPRWriteResGroup537 : SchedWriteRes<[SPRPort00]> {
4916 let ReleaseAtCycles = [2];
4917 let Latency = 11;
4918 let NumMicroOps = 2;
4919 }
4920 def : InstRW<[SPRWriteResGroup537], (instregex "^VRNDSCALEPHZrri(bk|kz)$",
4921 "^VRNDSCALEPHZrri(k|bkz)$",
4922 "^VSCALEFPHZrr(bk|kz)$",
4923 "^VSCALEFPHZrr(k|bkz)$")>;
4925 def SPRWriteResGroup538 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
4926 let ReleaseAtCycles = [2, 1];
4927 let Latency = 6;
4928 let NumMicroOps = 3;
4929 }
4930 def : InstRW<[SPRWriteResGroup538], (instregex "^VRSQRT14P(D|S)Zr$")>;
4931 def : InstRW<[SPRWriteResGroup538], (instrs VRSQRT14PSZrk,
4932 VRSQRTPHZr)>;
4934 def SPRWriteResGroup539 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
4935 let Latency = 25;
4936 let NumMicroOps = 2;
4937 }
4938 def : InstRW<[SPRWriteResGroup539], (instrs VSQRTPDYm)>;
4939 def : InstRW<[SPRWriteResGroup539, ReadAfterVecYLd], (instregex "^VSQRTPDZ256m(b?)$")>;
4941 def SPRWriteResGroup540 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> {
4942 let Latency = 20;
4943 let NumMicroOps = 2;
4944 }
4945 def : InstRW<[SPRWriteResGroup540, ReadAfterVecXLd], (instregex "^VSQRTPDZ128m(bk|kz)$",
4946 "^VSQRTPDZ128m(k|bkz)$")>;
4947 def : InstRW<[SPRWriteResGroup540, ReadAfterVecLd], (instregex "^VSQRTSDZmk(z?)_Int$")>;
4949 def SPRWriteResGroup541 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10]> {
4950 let ReleaseAtCycles = [2, 1, 1];
4951 let Latency = 38;
4952 let NumMicroOps = 4;
4953 }
4954 def : InstRW<[SPRWriteResGroup541, ReadAfterVecYLd], (instrs VSQRTPDZm)>;
4956 def SPRWriteResGroup542 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10]> {
4957 let ReleaseAtCycles = [2, 1, 1];
4958 let Latency = 39;
4959 let NumMicroOps = 4;
4960 }
4961 def : InstRW<[SPRWriteResGroup542, ReadAfterVecYLd], (instrs VSQRTPDZmb)>;
4963 def SPRWriteResGroup543 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
4964 let ReleaseAtCycles = [2, 1];
4965 let Latency = 31;
4966 let NumMicroOps = 3;
4967 }
4968 def : InstRW<[SPRWriteResGroup543], (instrs VSQRTPDZr)>;
4970 def SPRWriteResGroup544 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_10]> {
4971 let ReleaseAtCycles = [2, 1, 1];
4972 let Latency = 41;
4973 let NumMicroOps = 4;
4974 }
4975 def : InstRW<[SPRWriteResGroup544, ReadAfterVecXLd], (instregex "^VSQRTPHZ128m(bk|kz)$",
4976 "^VSQRTPHZ128m(k|bkz)$")>;
4978 def SPRWriteResGroup545 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
4979 let ReleaseAtCycles = [2, 1];
4980 let Latency = 35;
4981 let NumMicroOps = 3;
4982 }
4983 def : InstRW<[SPRWriteResGroup545], (instregex "^VSQRTPHZ(128|256)rk$")>;
4984 def : InstRW<[SPRWriteResGroup545], (instrs VSQRTPHZ256rkz)>;
4986 def SPRWriteResGroup546 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
4987 let ReleaseAtCycles = [2, 1];
4988 let Latency = 12;
4989 let NumMicroOps = 3;
4990 }
4991 def : InstRW<[SPRWriteResGroup546], (instrs VSQRTPHZ128rkz)>;
4993 def SPRWriteResGroup547 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_10]> {
4994 let ReleaseAtCycles = [2, 1, 1];
4995 let Latency = 40;
4996 let NumMicroOps = 4;
4997 }
4998 def : InstRW<[SPRWriteResGroup547, ReadAfterVecYLd], (instregex "^VSQRTPHZ256m(b?)$")>;
5000 def SPRWriteResGroup548 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_10]> {
5001 let ReleaseAtCycles = [2, 1, 1];
5002 let Latency = 42;
5003 let NumMicroOps = 4;
5004 }
5005 def : InstRW<[SPRWriteResGroup548, ReadAfterVecYLd], (instregex "^VSQRTPHZ256m(bk|kz)$",
5006 "^VSQRTPHZ256m(k|bkz)$")>;
5008 def SPRWriteResGroup549 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
5009 let ReleaseAtCycles = [4, 2, 1, 1, 1];
5010 let Latency = 53;
5011 let NumMicroOps = 9;
5012 }
5013 def : InstRW<[SPRWriteResGroup549, ReadAfterVecYLd], (instregex "^VSQRTPHZm(b?)$")>;
5015 def SPRWriteResGroup550 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> {
5016 let ReleaseAtCycles = [4, 2, 1, 1, 1];
5017 let Latency = 55;
5018 let NumMicroOps = 9;
5019 }
5020 def : InstRW<[SPRWriteResGroup550, ReadAfterVecYLd], (instregex "^VSQRTPHZm(bk|kz)$",
5021 "^VSQRTPHZm(k|bkz)$")>;
5023 def SPRWriteResGroup551 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
5024 let ReleaseAtCycles = [4, 1, 1];
5025 let Latency = 45;
5026 let NumMicroOps = 6;
5027 }
5028 def : InstRW<[SPRWriteResGroup551], (instregex "^VSQRTPHZr(b?)$")>;
5030 def SPRWriteResGroup552 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
5031 let ReleaseAtCycles = [4, 1, 1];
5032 let Latency = 47;
5033 let NumMicroOps = 6;
5034 }
5035 def : InstRW<[SPRWriteResGroup552], (instregex "^VSQRTPHZr(bk|kz)$",
5036 "^VSQRTPHZr(k|bkz)$")>;
5038 def SPRWriteResGroup553 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
5039 let ReleaseAtCycles = [2, 1];
5040 let Latency = 19;
5041 let NumMicroOps = 3;
5042 }
5043 def : InstRW<[SPRWriteResGroup553], (instrs VSQRTPSZr)>;
5045 def SPRWriteResGroup554 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11]> {
5046 let ReleaseAtCycles = [1, 2, 3, 3, 1];
5047 let Latency = 12;
5048 let NumMicroOps = 10;
5049 }
5050 def : InstRW<[SPRWriteResGroup554], (instrs VZEROALL)>;
5052 def SPRWriteResGroup555 : SchedWriteRes<[SPRPort00_01_05_06]> {
5053 let ReleaseAtCycles = [2];
5054 let Latency = 2;
5055 let NumMicroOps = 2;
5056 }
5057 def : InstRW<[SPRWriteResGroup555], (instrs WAIT)>;
5059 def SPRWriteResGroup556 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5060 let ReleaseAtCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];
5061 let Latency = SapphireRapidsModel.MaxLatency;
5062 let NumMicroOps = 144;
5063 }
5064 def : InstRW<[SPRWriteResGroup556], (instrs WRMSR)>;
5066 def SPRWriteResGroup557 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort05]> {
5067 let ReleaseAtCycles = [2, 1, 4, 1];
5068 let Latency = SapphireRapidsModel.MaxLatency;
5069 let NumMicroOps = 8;
5070 }
5071 def : InstRW<[SPRWriteResGroup557], (instrs WRPKRUr)>;
5073 def SPRWriteResGroup558 : SchedWriteRes<[SPRPort00_01_05_06_11]> {
5074 let ReleaseAtCycles = [2];
5075 let Latency = 12;
5076 let NumMicroOps = 2;
5077 }
5078 def : InstRW<[SPRWriteResGroup558, WriteRMW], (instregex "^XADD(16|32|64)rm$")>;
5080 def SPRWriteResGroup559 : SchedWriteRes<[SPRPort00_01_05_06_11]> {
5081 let ReleaseAtCycles = [2];
5082 let Latency = 13;
5083 let NumMicroOps = 2;
5084 }
5085 def : InstRW<[SPRWriteResGroup559, WriteRMW], (instrs XADD8rm)>;
5087 def SPRWriteResGroup560 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> {
5088 let ReleaseAtCycles = [4, 1];
5089 let Latency = 39;
5090 let NumMicroOps = 5;
5091 }
5092 def : InstRW<[SPRWriteResGroup560, WriteRMW], (instregex "^XCHG(16|32)rm$")>;
5094 def SPRWriteResGroup561 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> {
5095 let ReleaseAtCycles = [5, 1];
5096 let Latency = 39;
5097 let NumMicroOps = 6;
5098 }
5099 def : InstRW<[SPRWriteResGroup561, WriteRMW], (instrs XCHG64rm)>;
5101 def SPRWriteResGroup562 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> {
5102 let ReleaseAtCycles = [4, 1];
5103 let Latency = 40;
5104 let NumMicroOps = 5;
5105 }
5106 def : InstRW<[SPRWriteResGroup562, WriteRMW], (instrs XCHG8rm)>;
5108 def SPRWriteResGroup563 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06, SPRPort00_05, SPRPort01, SPRPort05, SPRPort06]> {
5109 let ReleaseAtCycles = [2, 4, 2, 1, 2, 4];
5110 let Latency = 17;
5111 let NumMicroOps = 15;
5112 }
5113 def : InstRW<[SPRWriteResGroup563], (instrs XCH_F)>;
5115 def SPRWriteResGroup564 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01]> {
5116 let ReleaseAtCycles = [7, 3, 8, 5];
5117 let Latency = 4;
5118 let NumMicroOps = 23;
5119 }
5120 def : InstRW<[SPRWriteResGroup564], (instrs XGETBV)>;
5122 def SPRWriteResGroup565 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> {
5123 let ReleaseAtCycles = [2, 1];
5124 let Latency = 7;
5125 let NumMicroOps = 3;
5126 }
5127 def : InstRW<[SPRWriteResGroup565], (instrs XLAT)>;
5129 def SPRWriteResGroup566 : SchedWriteRes<[SPRPort01, SPRPort02_03, SPRPort02_03_10, SPRPort06]> {
5130 let ReleaseAtCycles = [1, 21, 1, 8];
5131 let Latency = 37;
5132 let NumMicroOps = 31;
5133 }
5134 def : InstRW<[SPRWriteResGroup566], (instregex "^XRSTOR((S|64)?)$")>;
5135 def : InstRW<[SPRWriteResGroup566], (instrs XRSTORS64)>;
5137 def SPRWriteResGroup567 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5138 let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
5139 let Latency = 42;
5140 let NumMicroOps = 140;
5141 }
5142 def : InstRW<[SPRWriteResGroup567], (instrs XSAVE)>;
5144 def SPRWriteResGroup568 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5145 let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
5146 let Latency = 41;
5147 let NumMicroOps = 140;
5148 }
5149 def : InstRW<[SPRWriteResGroup568], (instrs XSAVE64)>;
5151 def SPRWriteResGroup569 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5152 let ReleaseAtCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];
5153 let Latency = 42;
5154 let NumMicroOps = 151;
5155 }
5156 def : InstRW<[SPRWriteResGroup569], (instrs XSAVEC)>;
5158 def SPRWriteResGroup570 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5159 let ReleaseAtCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];
5160 let Latency = 42;
5161 let NumMicroOps = 152;
5162 }
5163 def : InstRW<[SPRWriteResGroup570], (instrs XSAVEC64)>;
5165 def SPRWriteResGroup571 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5166 let ReleaseAtCycles = [25, 35, 52, 27, 4, 1, 10, 1];
5167 let Latency = 42;
5168 let NumMicroOps = 155;
5169 }
5170 def : InstRW<[SPRWriteResGroup571], (instrs XSAVEOPT)>;
5172 def SPRWriteResGroup572 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5173 let ReleaseAtCycles = [25, 35, 53, 27, 4, 1, 10, 1];
5174 let Latency = 42;
5175 let NumMicroOps = 156;
5176 }
5177 def : InstRW<[SPRWriteResGroup572], (instrs XSAVEOPT64)>;
5179 def SPRWriteResGroup573 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5180 let ReleaseAtCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];
5181 let Latency = 42;
5182 let NumMicroOps = 184;
5183 }
5184 def : InstRW<[SPRWriteResGroup573], (instrs XSAVES)>;
5186 def SPRWriteResGroup574 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5187 let ReleaseAtCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];
5188 let Latency = 42;
5189 let NumMicroOps = 186;
5190 }
5191 def : InstRW<[SPRWriteResGroup574], (instrs XSAVES64)>;
5193 def SPRWriteResGroup575 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort05]> {
5194 let ReleaseAtCycles = [4, 23, 2, 14, 8, 1, 2];
5195 let Latency = 5;
5196 let NumMicroOps = 54;
5197 }
5198 def : InstRW<[SPRWriteResGroup575], (instrs XSETBV)>;
5200 def SPRWriteResGroup576 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> {
5201 let ReleaseAtCycles = [2, 1];
5202 let Latency = SapphireRapidsModel.MaxLatency;
5203 let NumMicroOps = 3;
5204 }
5205 def : InstRW<[SPRWriteResGroup576], (instrs XTEST)>;
5207 }