llvm/lib/Target/X86/X86SchedSkylakeClient.td

   1 //=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for Skylake Client to support
  10 // instruction scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def SkylakeClientModel : SchedMachineModel {
  15   // All x86 instructions are modeled as a single micro-op, and SKylake can
  16   // decode 6 instructions per cycle.
  17   let IssueWidth = 6;
  18   let MicroOpBufferSize = 224; // Based on the reorder buffer.
  19   let LoadLatency = 5;
  20   let MispredictPenalty = 14;
  21
  22   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  23   let LoopMicroOpBufferSize = 50;
  24
  25   // This flag is set to allow the scheduler to assign a default model to
  26   // unrecognized opcodes.
  27   let CompleteModel = 0;
  28 }
  29
  30 let SchedModel = SkylakeClientModel in {
  31
  32 // Skylake Client can issue micro-ops to 8 different ports in one cycle.
  33
  34 // Ports 0, 1, 5, and 6 handle all computation.
  35 // Port 4 gets the data half of stores. Store data can be available later than
  36 // the store address, but since we don't model the latency of stores, we can
  37 // ignore that.
  38 // Ports 2 and 3 are identical. They handle loads and the address half of
  39 // stores. Port 7 can handle address calculations.
  40 def SKLPort0 : ProcResource<1>;
  41 def SKLPort1 : ProcResource<1>;
  42 def SKLPort2 : ProcResource<1>;
  43 def SKLPort3 : ProcResource<1>;
  44 def SKLPort4 : ProcResource<1>;
  45 def SKLPort5 : ProcResource<1>;
  46 def SKLPort6 : ProcResource<1>;
  47 def SKLPort7 : ProcResource<1>;
  48
  49 // Many micro-ops are capable of issuing on multiple ports.
  50 def SKLPort01  : ProcResGroup<[SKLPort0, SKLPort1]>;
  51 def SKLPort23  : ProcResGroup<[SKLPort2, SKLPort3]>;
  52 def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>;
  53 def SKLPort04  : ProcResGroup<[SKLPort0, SKLPort4]>;
  54 def SKLPort05  : ProcResGroup<[SKLPort0, SKLPort5]>;
  55 def SKLPort06  : ProcResGroup<[SKLPort0, SKLPort6]>;
  56 def SKLPort15  : ProcResGroup<[SKLPort1, SKLPort5]>;
  57 def SKLPort16  : ProcResGroup<[SKLPort1, SKLPort6]>;
  58 def SKLPort56  : ProcResGroup<[SKLPort5, SKLPort6]>;
  59 def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;
  60 def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;
  61 def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
  62
  63 def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
  64 // FP division and sqrt on port 0.
  65 def SKLFPDivider : ProcResource<1>;
  66
  67 // 60 Entry Unified Scheduler
  68 def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
  69                               SKLPort5, SKLPort6, SKLPort7]> {
  70   let BufferSize=60;
  71 }
  72
  73 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  74 // cycles after the memory operand.
  75 def : ReadAdvance<ReadAfterLd, 5>;
  76
  77 // Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
  78 // until 5/6/7 cycles after the memory operand.
  79 def : ReadAdvance<ReadAfterVecLd, 5>;
  80 def : ReadAdvance<ReadAfterVecXLd, 6>;
  81 def : ReadAdvance<ReadAfterVecYLd, 7>;
  82
  83 def : ReadAdvance<ReadInt2Fpu, 0>;
  84
  85 // Many SchedWrites are defined in pairs with and without a folded load.
  86 // Instructions with folded loads are usually micro-fused, so they only appear
  87 // as two micro-ops when queued in the reservation station.
  88 // This multiclass defines the resource usage for variants with and without
  89 // folded loads.
  90 multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
  91                           list<ProcResourceKind> ExePorts,
  92                           int Lat, list<int> Res = [1], int UOps = 1,
  93                           int LoadLat = 5, int LoadUOps = 1> {
  94   // Register variant is using a single cycle on ExePort.
  95   def : WriteRes<SchedRW, ExePorts> {
  96     let Latency = Lat;
  97     let ReleaseAtCycles = Res;
  98     let NumMicroOps = UOps;
  99   }
 100
 101   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
 102   // the latency (default = 5).
 103   def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {
 104     let Latency = !add(Lat, LoadLat);
 105     let ReleaseAtCycles = !listconcat([1], Res);
 106     let NumMicroOps = !add(UOps, LoadUOps);
 107   }
 108 }
 109
 110 // A folded store needs a cycle on port 4 for the store data, and an extra port
 111 // 2/3/7 cycle to recompute the address.
 112 def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;
 113
 114 // Arithmetic.
 115 defm : SKLWriteResPair<WriteALU,    [SKLPort0156], 1>; // Simple integer ALU op.
 116 defm : SKLWriteResPair<WriteADC,    [SKLPort06],   1>; // Integer ALU + flags op.
 117
 118 // Integer multiplication.
 119 defm : SKLWriteResPair<WriteIMul8,     [SKLPort1],   3>;
 120 defm : SKLWriteResPair<WriteIMul16,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,2], 4>;
 121 defm : X86WriteRes<WriteIMul16Imm,     [SKLPort1,SKLPort0156], 4, [1,1], 2>;
 122 defm : X86WriteRes<WriteIMul16ImmLd,   [SKLPort1,SKLPort0156,SKLPort23], 8, [1,1,1], 3>;
 123 defm : SKLWriteResPair<WriteIMul16Reg, [SKLPort1],   3>;
 124 defm : SKLWriteResPair<WriteIMul32,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>;
 125 defm : SKLWriteResPair<WriteMULX32,    [SKLPort1,SKLPort06,SKLPort0156], 3, [1,1,1], 3>;
 126 defm : SKLWriteResPair<WriteIMul32Imm, [SKLPort1],   3>;
 127 defm : SKLWriteResPair<WriteIMul32Reg, [SKLPort1],   3>;
 128 defm : SKLWriteResPair<WriteIMul64,    [SKLPort1,SKLPort5], 4, [1,1], 2>;
 129 defm : SKLWriteResPair<WriteMULX64,    [SKLPort1,SKLPort5], 3, [1,1], 2>;
 130 defm : SKLWriteResPair<WriteIMul64Imm, [SKLPort1],   3>;
 131 defm : SKLWriteResPair<WriteIMul64Reg, [SKLPort1],   3>;
 132 def SKLWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }
 133 def  : WriteRes<WriteIMulHLd, []> {
 134   let Latency = !add(SKLWriteIMulH.Latency, SkylakeClientModel.LoadLatency);
 135 }
 136
 137 defm : X86WriteRes<WriteBSWAP32,    [SKLPort15], 1, [1], 1>;
 138 defm : X86WriteRes<WriteBSWAP64,    [SKLPort06, SKLPort15], 2, [1,1], 2>;
 139 defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>;
 140 defm : X86WriteRes<WriteCMPXCHGRMW,[SKLPort23,SKLPort06,SKLPort0156,SKLPort237,SKLPort4], 8, [1,2,1,1,1], 6>;
 141 defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>;
 142
 143 // TODO: Why isn't the SKLDivider used?
 144 defm : SKLWriteResPair<WriteDiv8,   [SKLPort0,SKLDivider], 25, [1,10], 1, 4>;
 145 defm : X86WriteRes<WriteDiv16,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
 146 defm : X86WriteRes<WriteDiv32,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
 147 defm : X86WriteRes<WriteDiv64,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
 148 defm : X86WriteRes<WriteDiv16Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
 149 defm : X86WriteRes<WriteDiv32Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
 150 defm : X86WriteRes<WriteDiv64Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
 151
 152 defm : X86WriteRes<WriteIDiv8,    [SKLPort0,SKLDivider], 25, [1,10], 1>;
 153 defm : X86WriteRes<WriteIDiv16,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
 154 defm : X86WriteRes<WriteIDiv32,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
 155 defm : X86WriteRes<WriteIDiv64,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
 156 defm : X86WriteRes<WriteIDiv8Ld,  [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 157 defm : X86WriteRes<WriteIDiv16Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 158 defm : X86WriteRes<WriteIDiv32Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 159 defm : X86WriteRes<WriteIDiv64Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 160
 161 defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>;
 162
 163 def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
 164
 165 defm : SKLWriteResPair<WriteCMOV,  [SKLPort06], 1, [1], 1>; // Conditional move.
 166 defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move.
 167 def  : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
 168 def  : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> {
 169   let Latency = 2;
 170   let NumMicroOps = 3;
 171 }
 172
 173 defm : X86WriteRes<WriteLAHFSAHF,        [SKLPort06], 1, [1], 1>;
 174 defm : X86WriteRes<WriteBitTest,         [SKLPort06], 1, [1], 1>;
 175 defm : X86WriteRes<WriteBitTestImmLd,    [SKLPort06,SKLPort23], 6, [1,1], 2>;
 176 defm : X86WriteRes<WriteBitTestRegLd,    [SKLPort0156,SKLPort23], 6, [1,1], 2>;
 177 defm : X86WriteRes<WriteBitTestSet,      [SKLPort06], 1, [1], 1>;
 178 defm : X86WriteRes<WriteBitTestSetImmLd, [SKLPort06,SKLPort23], 5, [1,1], 3>;
 179 defm : X86WriteRes<WriteBitTestSetRegLd, [SKLPort0156,SKLPort23], 5, [1,1], 2>;
 180
 181 // Bit counts.
 182 defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>;
 183 defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>;
 184 defm : SKLWriteResPair<WriteLZCNT,          [SKLPort1], 3>;
 185 defm : SKLWriteResPair<WriteTZCNT,          [SKLPort1], 3>;
 186 defm : SKLWriteResPair<WritePOPCNT,         [SKLPort1], 3>;
 187
 188 // Integer shifts and rotates.
 189 defm : SKLWriteResPair<WriteShift,    [SKLPort06],  1>;
 190 defm : SKLWriteResPair<WriteShiftCL,  [SKLPort06],  3, [3], 3>;
 191 defm : SKLWriteResPair<WriteRotate,   [SKLPort06],  1, [1], 1>;
 192 defm : SKLWriteResPair<WriteRotateCL, [SKLPort06],  3, [3], 3>;
 193
 194 // SHLD/SHRD.
 195 defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>;
 196 defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>;
 197 defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>;
 198 defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>;
 199
 200 // BMI1 BEXTR/BLS, BMI2 BZHI
 201 defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>;
 202 defm : SKLWriteResPair<WriteBLS,   [SKLPort15], 1>;
 203 defm : SKLWriteResPair<WriteBZHI,  [SKLPort15], 1>;
 204
 205 // Loads, stores, and moves, not folded with other operations.
 206 defm : X86WriteRes<WriteLoad,    [SKLPort23], 5, [1], 1>;
 207 defm : X86WriteRes<WriteStore,   [SKLPort237, SKLPort4], 1, [1,1], 1>;
 208 defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>;
 209 defm : X86WriteRes<WriteMove,    [SKLPort0156], 1, [1], 1>;
 210
 211 // Model the effect of clobbering the read-write mask operand of the GATHER operation.
 212 // Does not cost anything by itself, only has latency, matching that of the WriteLoad,
 213 defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;
 214
 215 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 216 // These can often bypass execution ports completely.
 217 def : WriteRes<WriteZero,  []>;
 218
 219 // Branches don't produce values, so they have no latency, but they still
 220 // consume resources. Indirect branches can fold loads.
 221 defm : SKLWriteResPair<WriteJump,  [SKLPort06],   1>;
 222
 223 // Floating point. This covers both scalar and vector operations.
 224 defm : X86WriteRes<WriteFLD0,          [SKLPort05], 1, [1], 1>;
 225 defm : X86WriteRes<WriteFLD1,          [SKLPort05], 1, [2], 2>;
 226 defm : X86WriteRes<WriteFLDC,          [SKLPort05], 1, [2], 2>;
 227 defm : X86WriteRes<WriteFLoad,         [SKLPort23], 5, [1], 1>;
 228 defm : X86WriteRes<WriteFLoadX,        [SKLPort23], 6, [1], 1>;
 229 defm : X86WriteRes<WriteFLoadY,        [SKLPort23], 7, [1], 1>;
 230 defm : X86WriteRes<WriteFMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
 231 defm : X86WriteRes<WriteFMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
 232 defm : X86WriteRes<WriteFStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
 233 defm : X86WriteRes<WriteFStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 234 defm : X86WriteRes<WriteFStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 235 defm : X86WriteRes<WriteFStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
 236 defm : X86WriteRes<WriteFStoreNTX,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 237 defm : X86WriteRes<WriteFStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 238
 239 defm : X86WriteRes<WriteFMaskedStore32,  [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
 240 defm : X86WriteRes<WriteFMaskedStore32Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
 241 defm : X86WriteRes<WriteFMaskedStore64,  [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
 242 defm : X86WriteRes<WriteFMaskedStore64Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
 243
 244 defm : X86WriteRes<WriteFMove,         [SKLPort015], 1, [1], 1>;
 245 defm : X86WriteRes<WriteFMoveX,        [SKLPort015], 1, [1], 1>;
 246 defm : X86WriteRes<WriteFMoveY,        [SKLPort015], 1, [1], 1>;
 247 defm : X86WriteResUnsupported<WriteFMoveZ>;
 248 defm : X86WriteRes<WriteEMMS,          [SKLPort05,SKLPort0156], 10, [9,1], 10>;
 249
 250 defm : SKLWriteResPair<WriteFAdd,     [SKLPort01],  4, [1], 1, 5>; // Floating point add/sub.
 251 defm : SKLWriteResPair<WriteFAddX,    [SKLPort01],  4, [1], 1, 6>;
 252 defm : SKLWriteResPair<WriteFAddY,    [SKLPort01],  4, [1], 1, 7>;
 253 defm : X86WriteResPairUnsupported<WriteFAddZ>;
 254 defm : SKLWriteResPair<WriteFAdd64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double add/sub.
 255 defm : SKLWriteResPair<WriteFAdd64X,  [SKLPort01],  4, [1], 1, 6>;
 256 defm : SKLWriteResPair<WriteFAdd64Y,  [SKLPort01],  4, [1], 1, 7>;
 257 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
 258
 259 defm : SKLWriteResPair<WriteFCmp,     [SKLPort01],  4, [1], 1, 5>; // Floating point compare.
 260 defm : SKLWriteResPair<WriteFCmpX,    [SKLPort01],  4, [1], 1, 6>;
 261 defm : SKLWriteResPair<WriteFCmpY,    [SKLPort01],  4, [1], 1, 7>;
 262 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
 263 defm : SKLWriteResPair<WriteFCmp64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double compare.
 264 defm : SKLWriteResPair<WriteFCmp64X,  [SKLPort01],  4, [1], 1, 6>;
 265 defm : SKLWriteResPair<WriteFCmp64Y,  [SKLPort01],  4, [1], 1, 7>;
 266 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
 267
 268 defm : SKLWriteResPair<WriteFCom,      [SKLPort0],  2>; // Floating point compare to flags (X87).
 269 defm : SKLWriteResPair<WriteFComX,     [SKLPort0],  2>; // Floating point compare to flags (SSE).
 270
 271 defm : SKLWriteResPair<WriteFMul,     [SKLPort01],  4, [1], 1, 5>; // Floating point multiplication.
 272 defm : SKLWriteResPair<WriteFMulX,    [SKLPort01],  4, [1], 1, 6>;
 273 defm : SKLWriteResPair<WriteFMulY,    [SKLPort01],  4, [1], 1, 7>;
 274 defm : X86WriteResPairUnsupported<WriteFMulZ>;
 275 defm : SKLWriteResPair<WriteFMul64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double multiplication.
 276 defm : SKLWriteResPair<WriteFMul64X,  [SKLPort01],  4, [1], 1, 6>;
 277 defm : SKLWriteResPair<WriteFMul64Y,  [SKLPort01],  4, [1], 1, 7>;
 278 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
 279
 280 defm : SKLWriteResPair<WriteFDiv,     [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division.
 281 defm : SKLWriteResPair<WriteFDivX,    [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>;
 282 defm : SKLWriteResPair<WriteFDivY,    [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>;
 283 defm : X86WriteResPairUnsupported<WriteFDivZ>;
 284 defm : SKLWriteResPair<WriteFDiv64,   [SKLPort0,SKLFPDivider], 14, [1,4], 1, 5>; // Floating point double division.
 285 defm : SKLWriteResPair<WriteFDiv64X,  [SKLPort0,SKLFPDivider], 14, [1,4], 1, 6>;
 286 defm : SKLWriteResPair<WriteFDiv64Y,  [SKLPort0,SKLFPDivider], 14, [1,8], 1, 7>;
 287 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
 288
 289 defm : SKLWriteResPair<WriteFSqrt,    [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
 290 defm : SKLWriteResPair<WriteFSqrtX,   [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>;
 291 defm : SKLWriteResPair<WriteFSqrtY,   [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>;
 292 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
 293 defm : SKLWriteResPair<WriteFSqrt64,  [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
 294 defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>;
 295 defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>;
 296 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
 297 defm : SKLWriteResPair<WriteFSqrt80,  [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root.
 298
 299 defm : SKLWriteResPair<WriteFRcp,   [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.
 300 defm : SKLWriteResPair<WriteFRcpX,  [SKLPort0], 4, [1], 1, 6>;
 301 defm : SKLWriteResPair<WriteFRcpY,  [SKLPort0], 4, [1], 1, 7>;
 302 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
 303
 304 defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.
 305 defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>;
 306 defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>;
 307 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
 308
 309 defm : SKLWriteResPair<WriteFMA,    [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add.
 310 defm : SKLWriteResPair<WriteFMAX,   [SKLPort01], 4, [1], 1, 6>;
 311 defm : SKLWriteResPair<WriteFMAY,   [SKLPort01], 4, [1], 1, 7>;
 312 defm : X86WriteResPairUnsupported<WriteFMAZ>;
 313 defm : SKLWriteResPair<WriteDPPD,   [SKLPort5,SKLPort01],  9, [1,2], 3, 6>; // Floating point double dot product.
 314 defm : X86WriteRes<WriteDPPS,       [SKLPort5,SKLPort01], 13, [1,3], 4>;
 315 defm : X86WriteRes<WriteDPPSY,      [SKLPort5,SKLPort01], 13, [1,3], 4>;
 316 defm : X86WriteRes<WriteDPPSLd,     [SKLPort5,SKLPort01,SKLPort06,SKLPort23], 19, [1,3,1,1], 6>;
 317 defm : X86WriteRes<WriteDPPSYLd,    [SKLPort5,SKLPort01,SKLPort06,SKLPort23], 20, [1,3,1,1], 6>;
 318 defm : SKLWriteResPair<WriteFSign,   [SKLPort0], 1>; // Floating point fabs/fchs.
 319 defm : SKLWriteResPair<WriteFRnd,     [SKLPort01], 8, [2], 2, 6>; // Floating point rounding.
 320 defm : SKLWriteResPair<WriteFRndY,    [SKLPort01], 8, [2], 2, 7>;
 321 defm : X86WriteResPairUnsupported<WriteFRndZ>;
 322 defm : SKLWriteResPair<WriteFLogic,  [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
 323 defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>;
 324 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
 325 defm : SKLWriteResPair<WriteFTest,   [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
 326 defm : SKLWriteResPair<WriteFTestY,  [SKLPort0], 2, [1], 1, 7>;
 327 defm : X86WriteResPairUnsupported<WriteFTestZ>;
 328 defm : SKLWriteResPair<WriteFShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 329 defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>;
 330 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
 331 defm : SKLWriteResPair<WriteFVarShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 332 defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
 333 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
 334 defm : SKLWriteResPair<WriteFBlend,  [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends.
 335 defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>;
 336 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
 337 defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends.
 338 defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>;
 339 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
 340
 341 // FMA Scheduling helper class.
 342 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
 343
 344 // Vector integer operations.
 345 defm : X86WriteRes<WriteVecLoad,         [SKLPort23], 5, [1], 1>;
 346 defm : X86WriteRes<WriteVecLoadX,        [SKLPort23], 6, [1], 1>;
 347 defm : X86WriteRes<WriteVecLoadY,        [SKLPort23], 7, [1], 1>;
 348 defm : X86WriteRes<WriteVecLoadNT,       [SKLPort23,SKLPort015], 7, [1,1], 2>;
 349 defm : X86WriteRes<WriteVecLoadNTY,      [SKLPort23,SKLPort015], 8, [1,1], 2>;
 350 defm : X86WriteRes<WriteVecMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
 351 defm : X86WriteRes<WriteVecMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
 352 defm : X86WriteRes<WriteVecStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
 353 defm : X86WriteRes<WriteVecStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 354 defm : X86WriteRes<WriteVecStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 355 defm : X86WriteRes<WriteVecStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
 356 defm : X86WriteRes<WriteVecStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 357 defm : X86WriteRes<WriteVecMaskedStore32,  [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
 358 defm : X86WriteRes<WriteVecMaskedStore32Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
 359 defm : X86WriteRes<WriteVecMaskedStore64,  [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
 360 defm : X86WriteRes<WriteVecMaskedStore64Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
 361 defm : X86WriteRes<WriteVecMove,         [SKLPort05],  1, [1], 1>;
 362 defm : X86WriteRes<WriteVecMoveX,        [SKLPort015], 1, [1], 1>;
 363 defm : X86WriteRes<WriteVecMoveY,        [SKLPort015], 1, [1], 1>;
 364 defm : X86WriteResUnsupported<WriteVecMoveZ>;
 365 defm : X86WriteRes<WriteVecMoveToGpr,    [SKLPort0], 2, [1], 1>;
 366 defm : X86WriteRes<WriteVecMoveFromGpr,  [SKLPort5], 1, [1], 1>;
 367
 368 defm : SKLWriteResPair<WriteVecALU,   [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 369 defm : SKLWriteResPair<WriteVecALUX,  [SKLPort01], 1, [1], 1, 6>;
 370 defm : SKLWriteResPair<WriteVecALUY,  [SKLPort01], 1, [1], 1, 7>;
 371 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
 372 defm : SKLWriteResPair<WriteVecLogic, [SKLPort05],  1, [1], 1, 5>; // Vector integer and/or/xor.
 373 defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>;
 374 defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>;
 375 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
 376 defm : SKLWriteResPair<WriteVecTest,  [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
 377 defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>;
 378 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
 379 defm : SKLWriteResPair<WriteVecIMul,  [SKLPort0] ,  5, [1], 1, 5>; // Vector integer multiply.
 380 defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01],  5, [1], 1, 6>;
 381 defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01],  5, [1], 1, 7>;
 382 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
 383 defm : SKLWriteResPair<WritePMULLD,   [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD.
 384 defm : SKLWriteResPair<WritePMULLDY,  [SKLPort01], 10, [2], 2, 7>;
 385 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
 386 defm : SKLWriteResPair<WriteShuffle,  [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
 387 defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>;
 388 defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>;
 389 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
 390 defm : SKLWriteResPair<WriteVarShuffle,  [SKLPort0,SKLPort5], 1, [1,1], 2, 5>; // Vector shuffles.
 391 defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>;
 392 defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
 393 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
 394 defm : SKLWriteResPair<WriteBlend,  [SKLPort5], 1, [1], 1, 6>; // Vector blends.
 395 defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>;
 396 defm : X86WriteResPairUnsupported<WriteBlendZ>;
 397 defm : SKLWriteResPair<WriteVarBlend,  [SKLPort015], 2, [2], 2, 6>; // Vector variable blends.
 398 defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>;
 399 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
 400 defm : SKLWriteResPair<WriteMPSAD,  [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD.
 401 defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>;
 402 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
 403 defm : SKLWriteResPair<WritePSADBW,  [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW.
 404 defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>;
 405 defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>;
 406 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
 407 defm : SKLWriteResPair<WritePHMINPOS, [SKLPort0], 4, [1], 1, 6>; // Vector PHMINPOS.
 408
 409 // Vector integer shifts.
 410 defm : SKLWriteResPair<WriteVecShift,     [SKLPort0], 1, [1], 1, 5>;
 411 defm : X86WriteRes<WriteVecShiftX,        [SKLPort5,SKLPort01],  2, [1,1], 2>;
 412 defm : X86WriteRes<WriteVecShiftY,        [SKLPort5,SKLPort01],  4, [1,1], 2>;
 413 defm : X86WriteRes<WriteVecShiftXLd,      [SKLPort01,SKLPort23], 7, [1,1], 2>;
 414 defm : X86WriteRes<WriteVecShiftYLd,      [SKLPort01,SKLPort23], 8, [1,1], 2>;
 415 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
 416
 417 defm : SKLWriteResPair<WriteVecShiftImm,  [SKLPort0],  1, [1], 1, 5>; // Vector integer immediate shifts.
 418 defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>;
 419 defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>;
 420 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
 421 defm : SKLWriteResPair<WriteVarVecShift,  [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts.
 422 defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>;
 423 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
 424
 425 // Vector insert/extract operations.
 426 def : WriteRes<WriteVecInsert, [SKLPort5]> {
 427   let Latency = 2;
 428   let NumMicroOps = 2;
 429   let ReleaseAtCycles = [2];
 430 }
 431 def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> {
 432   let Latency = 6;
 433   let NumMicroOps = 2;
 434 }
 435 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 436
 437 def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> {
 438   let Latency = 3;
 439   let NumMicroOps = 2;
 440 }
 441 def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> {
 442   let Latency = 2;
 443   let NumMicroOps = 3;
 444 }
 445
 446 // Conversion between integer and float.
 447 defm : SKLWriteResPair<WriteCvtSS2I,   [SKLPort0,SKLPort01], 6, [1,1], 2, 5>;
 448 defm : SKLWriteResPair<WriteCvtPS2I,   [SKLPort01], 4, [1], 1, 6>;
 449 defm : SKLWriteResPair<WriteCvtPS2IY,  [SKLPort01], 4, [1], 1, 7>;
 450 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
 451 defm : SKLWriteResPair<WriteCvtSD2I,   [SKLPort0,SKLPort01], 6, [1,1], 2, 5>;
 452 defm : SKLWriteResPair<WriteCvtPD2I,   [SKLPort5,SKLPort01], 5, [1,1], 2, 6>;
 453 defm : SKLWriteResPair<WriteCvtPD2IY,  [SKLPort5,SKLPort01], 7, [1,1], 2, 6>;
 454 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
 455
 456 defm : X86WriteRes<WriteCvtI2SS,      [SKLPort5,SKLPort01],  5, [1,1], 2>;
 457 defm : X86WriteRes<WriteCvtI2SSLd,   [SKLPort23,SKLPort01], 10, [1,1], 2>;
 458 defm : SKLWriteResPair<WriteCvtI2PS,   [SKLPort01], 4, [1], 1, 6>;
 459 defm : SKLWriteResPair<WriteCvtI2PSY,  [SKLPort01], 4, [1], 1, 7>;
 460 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
 461 defm : X86WriteRes<WriteCvtI2SD,      [SKLPort5,SKLPort01],  5, [1,1], 2>;
 462 defm : X86WriteRes<WriteCvtI2SDLd,   [SKLPort23,SKLPort01], 10, [1,1], 2>;
 463 defm : X86WriteRes<WriteCvtI2PD,      [SKLPort5,SKLPort01],  5, [1,1], 2>;
 464 defm : X86WriteRes<WriteCvtI2PDLd,   [SKLPort23,SKLPort01], 10, [1,1], 2>;
 465 defm : X86WriteRes<WriteCvtI2PDY,     [SKLPort5,SKLPort01],  7, [1,1], 2>;
 466 defm : X86WriteRes<WriteCvtI2PDYLd,  [SKLPort23,SKLPort01], 11, [1,1], 2>;
 467 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
 468
 469 defm : X86WriteRes<WriteCvtSS2SD,     [SKLPort5,SKLPort01],  5, [1,1], 2>;
 470 defm : X86WriteRes<WriteCvtSS2SDLd,  [SKLPort23,SKLPort01], 10, [1,1], 2>;
 471 defm : X86WriteRes<WriteCvtPS2PD,     [SKLPort5,SKLPort01],  5, [1,1], 2>;
 472 defm : X86WriteRes<WriteCvtPS2PDLd,  [SKLPort23,SKLPort01],  9, [1,1], 2>;
 473 defm : X86WriteRes<WriteCvtPS2PDY,    [SKLPort5,SKLPort01],  7, [1,1], 2>;
 474 defm : X86WriteRes<WriteCvtPS2PDYLd, [SKLPort23,SKLPort01], 11, [1,1], 2>;
 475 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
 476 defm : SKLWriteResPair<WriteCvtSD2SS,  [SKLPort5,SKLPort01], 5, [1,1], 2, 5>;
 477 defm : SKLWriteResPair<WriteCvtPD2PS,  [SKLPort5,SKLPort01], 5, [1,1], 2, 6>;
 478 defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort5,SKLPort01], 7, [1,1], 2, 6>;
 479 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
 480
 481 defm : X86WriteRes<WriteCvtPH2PS,     [SKLPort5,SKLPort01],  5, [1,1], 2>;
 482 defm : X86WriteRes<WriteCvtPH2PSY,    [SKLPort5,SKLPort01],  7, [1,1], 2>;
 483 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
 484 defm : X86WriteRes<WriteCvtPH2PSLd,  [SKLPort23,SKLPort01],  9, [1,1], 2>;
 485 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;
 486 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
 487
 488 defm : X86WriteRes<WriteCvtPS2PH,                        [SKLPort5,SKLPort01], 5, [1,1], 2>;
 489 defm : X86WriteRes<WriteCvtPS2PHY,                       [SKLPort5,SKLPort01], 7, [1,1], 2>;
 490 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
 491 defm : X86WriteRes<WriteCvtPS2PHSt,  [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>;
 492 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>;
 493 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
 494
 495 // Strings instructions.
 496
 497 // Packed Compare Implicit Length Strings, Return Mask
 498 def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
 499   let Latency = 10;
 500   let NumMicroOps = 3;
 501   let ReleaseAtCycles = [3];
 502 }
 503 def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {
 504   let Latency = 16;
 505   let NumMicroOps = 4;
 506   let ReleaseAtCycles = [3,1];
 507 }
 508
 509 // Packed Compare Explicit Length Strings, Return Mask
 510 def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> {
 511   let Latency = 19;
 512   let NumMicroOps = 9;
 513   let ReleaseAtCycles = [4,3,1,1];
 514 }
 515 def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> {
 516   let Latency = 25;
 517   let NumMicroOps = 10;
 518   let ReleaseAtCycles = [4,3,1,1,1];
 519 }
 520
 521 // Packed Compare Implicit Length Strings, Return Index
 522 def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
 523   let Latency = 10;
 524   let NumMicroOps = 3;
 525   let ReleaseAtCycles = [3];
 526 }
 527 def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {
 528   let Latency = 16;
 529   let NumMicroOps = 4;
 530   let ReleaseAtCycles = [3,1];
 531 }
 532
 533 // Packed Compare Explicit Length Strings, Return Index
 534 def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> {
 535   let Latency = 18;
 536   let NumMicroOps = 8;
 537   let ReleaseAtCycles = [4,3,1];
 538 }
 539 def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> {
 540   let Latency = 24;
 541   let NumMicroOps = 9;
 542   let ReleaseAtCycles = [4,3,1,1];
 543 }
 544
 545 // MOVMSK Instructions.
 546 def : WriteRes<WriteFMOVMSK,    [SKLPort0]> { let Latency = 2; }
 547 def : WriteRes<WriteVecMOVMSK,  [SKLPort0]> { let Latency = 2; }
 548 def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; }
 549 def : WriteRes<WriteMMXMOVMSK,  [SKLPort0]> { let Latency = 2; }
 550
 551 // AES instructions.
 552 def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.
 553   let Latency = 4;
 554   let NumMicroOps = 1;
 555   let ReleaseAtCycles = [1];
 556 }
 557 def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {
 558   let Latency = 10;
 559   let NumMicroOps = 2;
 560   let ReleaseAtCycles = [1,1];
 561 }
 562
 563 def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn.
 564   let Latency = 8;
 565   let NumMicroOps = 2;
 566   let ReleaseAtCycles = [2];
 567 }
 568 def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> {
 569   let Latency = 14;
 570   let NumMicroOps = 3;
 571   let ReleaseAtCycles = [2,1];
 572 }
 573
 574 def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation.
 575   let Latency = 20;
 576   let NumMicroOps = 11;
 577   let ReleaseAtCycles = [3,6,2];
 578 }
 579 def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {
 580   let Latency = 25;
 581   let NumMicroOps = 11;
 582   let ReleaseAtCycles = [3,6,1,1];
 583 }
 584
 585 // Carry-less multiplication instructions.
 586 def : WriteRes<WriteCLMul, [SKLPort5]> {
 587   let Latency = 6;
 588   let NumMicroOps = 1;
 589   let ReleaseAtCycles = [1];
 590 }
 591 def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> {
 592   let Latency = 12;
 593   let NumMicroOps = 2;
 594   let ReleaseAtCycles = [1,1];
 595 }
 596
 597 // Catch-all for expensive system instructions.
 598 def : WriteRes<WriteSystem,     [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 599
 600 // AVX2.
 601 defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
 602 defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
 603 defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector shuffles.
 604 defm : SKLWriteResPair<WriteVPMOV256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width packed vector width-changing move.
 605 defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector variable shuffles.
 606
 607 // Old microcoded instructions that nobody use.
 608 def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 609
 610 // Fence instructions.
 611 def : WriteRes<WriteFence,  [SKLPort23, SKLPort4]> { let NumMicroOps = 2; let ReleaseAtCycles = [1,1]; }
 612
 613 // Load/store MXCSR.
 614 def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
 615 def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
 616
 617 // Nop, not very useful expect it provides a model for nops!
 618 def : WriteRes<WriteNop, []>;
 619
 620 ////////////////////////////////////////////////////////////////////////////////
 621 // Horizontal add/sub  instructions.
 622 ////////////////////////////////////////////////////////////////////////////////
 623
 624 defm : SKLWriteResPair<WriteFHAdd,  [SKLPort5,SKLPort01], 6, [2,1], 3, 6>;
 625 defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>;
 626 defm : SKLWriteResPair<WritePHAdd,  [SKLPort5,SKLPort05],  3, [2,1], 3, 5>;
 627 defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>;
 628 defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>;
 629
 630 // Remaining instrs.
 631
 632 def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
 633   let Latency = 1;
 634   let NumMicroOps = 1;
 635   let ReleaseAtCycles = [1];
 636 }
 637 def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)rr",
 638                                             "MMX_PADDUS(B|W)rr",
 639                                             "MMX_PAVG(B|W)rr",
 640                                             "MMX_PCMPEQ(B|D|W)rr",
 641                                             "MMX_PCMPGT(B|D|W)rr",
 642                                             "MMX_P(MAX|MIN)SWrr",
 643                                             "MMX_P(MAX|MIN)UBrr",
 644                                             "MMX_PSUBS(B|W)rr",
 645                                             "MMX_PSUBUS(B|W)rr")>;
 646
 647 def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
 648   let Latency = 1;
 649   let NumMicroOps = 1;
 650   let ReleaseAtCycles = [1];
 651 }
 652 def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r",
 653                                             "UCOM_F(P?)r")>;
 654
 655 def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
 656   let Latency = 1;
 657   let NumMicroOps = 1;
 658   let ReleaseAtCycles = [1];
 659 }
 660 def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 661
 662 def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
 663   let Latency = 1;
 664   let NumMicroOps = 1;
 665   let ReleaseAtCycles = [1];
 666 }
 667 def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
 668
 669 def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
 670   let Latency = 1;
 671   let NumMicroOps = 1;
 672   let ReleaseAtCycles = [1];
 673 }
 674 def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
 675
 676 def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
 677   let Latency = 1;
 678   let NumMicroOps = 1;
 679   let ReleaseAtCycles = [1];
 680 }
 681 def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>;
 682
 683 def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
 684   let Latency = 1;
 685   let NumMicroOps = 1;
 686   let ReleaseAtCycles = [1];
 687 }
 688 def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr",
 689                                             "VPBLENDD(Y?)rri")>;
 690
 691 def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
 692   let Latency = 1;
 693   let NumMicroOps = 1;
 694   let ReleaseAtCycles = [1];
 695 }
 696 def: InstRW<[SKLWriteResGroup10], (instrs SGDT64m,
 697                                           SIDT64m,
 698                                           SMSW16m,
 699                                           STRm,
 700                                           SYSCALL)>;
 701
 702 def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
 703   let Latency = 1;
 704   let NumMicroOps = 2;
 705   let ReleaseAtCycles = [1,1];
 706 }
 707 def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
 708 def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>;
 709
 710 def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
 711   let Latency = 2;
 712   let NumMicroOps = 2;
 713   let ReleaseAtCycles = [2];
 714 }
 715 def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
 716
 717 def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
 718   let Latency = 2;
 719   let NumMicroOps = 2;
 720   let ReleaseAtCycles = [2];
 721 }
 722 def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP,
 723                                           MMX_MOVDQ2Qrr)>;
 724
 725 def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
 726   let Latency = 2;
 727   let NumMicroOps = 2;
 728   let ReleaseAtCycles = [2];
 729 }
 730 def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,
 731                                           WAIT,
 732                                           XGETBV)>;
 733
 734 def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 735   let Latency = 2;
 736   let NumMicroOps = 2;
 737   let ReleaseAtCycles = [1,1];
 738 }
 739 def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
 740
 741 def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 742   let Latency = 2;
 743   let NumMicroOps = 2;
 744   let ReleaseAtCycles = [1,1];
 745 }
 746 def: InstRW<[SKLWriteResGroup23], (instrs CWD,
 747                                           JCXZ, JECXZ, JRCXZ,
 748                                           ADC8i8, SBB8i8,
 749                                           ADC16i16, SBB16i16,
 750                                           ADC32i32, SBB32i32,
 751                                           ADC64i32, SBB64i32)>;
 752
 753 def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
 754   let Latency = 2;
 755   let NumMicroOps = 3;
 756   let ReleaseAtCycles = [1,1,1];
 757 }
 758 def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>;
 759
 760 def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
 761   let Latency = 2;
 762   let NumMicroOps = 3;
 763   let ReleaseAtCycles = [1,1,1];
 764 }
 765 def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
 766
 767 def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
 768   let Latency = 2;
 769   let NumMicroOps = 3;
 770   let ReleaseAtCycles = [1,1,1];
 771 }
 772 def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
 773                                           STOSB, STOSL, STOSQ, STOSW)>;
 774 def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
 775
 776 def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {
 777   let Latency = 3;
 778   let NumMicroOps = 1;
 779   let ReleaseAtCycles = [1];
 780 }
 781 def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr",
 782                                              "PEXT(32|64)rr")>;
 783
 784 def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {
 785   let Latency = 3;
 786   let NumMicroOps = 1;
 787   let ReleaseAtCycles = [1];
 788 }
 789 def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
 790                                              "VPBROADCAST(B|W)rr")>;
 791
 792 def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
 793   let Latency = 3;
 794   let NumMicroOps = 2;
 795   let ReleaseAtCycles = [1,1];
 796 }
 797 def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>;
 798
 799 def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
 800   let Latency = 3;
 801   let NumMicroOps = 3;
 802   let ReleaseAtCycles = [1,2];
 803 }
 804 def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>;
 805
 806 def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
 807   let Latency = 3;
 808   let NumMicroOps = 3;
 809   let ReleaseAtCycles = [2,1];
 810 }
 811 def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr",
 812                                              "(V?)PHSUBSW(Y?)rr")>;
 813
 814 def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5]> {
 815   let Latency = 2;
 816   let NumMicroOps = 2;
 817   let ReleaseAtCycles = [2];
 818 }
 819 def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWrr,
 820                                           MMX_PACKSSWBrr,
 821                                           MMX_PACKUSWBrr)>;
 822
 823 def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 824   let Latency = 3;
 825   let NumMicroOps = 3;
 826   let ReleaseAtCycles = [1,2];
 827 }
 828 def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
 829
 830 def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 831   let Latency = 2;
 832   let NumMicroOps = 3;
 833   let ReleaseAtCycles = [1,2];
 834 }
 835 def: InstRW<[SKLWriteResGroup42], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
 836                                           RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
 837
 838 def SKLWriteResGroup42b : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
 839   let Latency = 5;
 840   let NumMicroOps = 8;
 841   let ReleaseAtCycles = [2,4,2];
 842 }
 843 def: InstRW<[SKLWriteResGroup42b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
 844
 845 def SKLWriteResGroup42c : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
 846   let Latency = 6;
 847   let NumMicroOps = 8;
 848   let ReleaseAtCycles = [2,4,2];
 849 }
 850 def: InstRW<[SKLWriteResGroup42c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
 851
 852 def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
 853   let Latency = 3;
 854   let NumMicroOps = 3;
 855   let ReleaseAtCycles = [1,1,1];
 856 }
 857 def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>;
 858
 859 def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
 860   let Latency = 3;
 861   let NumMicroOps = 4;
 862   let ReleaseAtCycles = [1,1,1,1];
 863 }
 864 def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;
 865
 866 def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
 867   let Latency = 3;
 868   let NumMicroOps = 4;
 869   let ReleaseAtCycles = [1,1,1,1];
 870 }
 871 def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>;
 872
 873 def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {
 874   let Latency = 4;
 875   let NumMicroOps = 1;
 876   let ReleaseAtCycles = [1];
 877 }
 878 def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 879
 880 def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
 881   let Latency = 4;
 882   let NumMicroOps = 3;
 883   let ReleaseAtCycles = [1,1,1];
 884 }
 885 def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m",
 886                                              "IST_F(16|32)m")>;
 887
 888 def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {
 889   let Latency = 4;
 890   let NumMicroOps = 4;
 891   let ReleaseAtCycles = [4];
 892 }
 893 def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>;
 894
 895 def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 896   let Latency = 4;
 897   let NumMicroOps = 4;
 898   let ReleaseAtCycles = [1,3];
 899 }
 900 def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>;
 901
 902 def SKLWriteResGroup56 : SchedWriteRes<[]> {
 903   let Latency = 0;
 904   let NumMicroOps = 4;
 905   let ReleaseAtCycles = [];
 906 }
 907 def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>;
 908
 909 def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
 910   let Latency = 4;
 911   let NumMicroOps = 4;
 912   let ReleaseAtCycles = [1,1,2];
 913 }
 914 def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
 915
 916 def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort0]> {
 917   let Latency = 5;
 918   let NumMicroOps = 2;
 919   let ReleaseAtCycles = [1,1];
 920 }
 921 def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PS2PIrr")>;
 922
 923 def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
 924   let Latency = 5;
 925   let NumMicroOps = 3;
 926   let ReleaseAtCycles = [1,1,1];
 927 }
 928 def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;
 929
 930 def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 931   let Latency = 5;
 932   let NumMicroOps = 5;
 933   let ReleaseAtCycles = [1,4];
 934 }
 935 def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>;
 936
 937 def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
 938   let Latency = 5;
 939   let NumMicroOps = 6;
 940   let ReleaseAtCycles = [1,1,4];
 941 }
 942 def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>;
 943
 944 def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {
 945   let Latency = 6;
 946   let NumMicroOps = 1;
 947   let ReleaseAtCycles = [1];
 948 }
 949 def: InstRW<[SKLWriteResGroup67], (instrs VBROADCASTSSrm,
 950                                           VPBROADCASTDrm,
 951                                           VPBROADCASTQrm)>;
 952 def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm",
 953                                              "(V?)MOVSLDUPrm",
 954                                              "(V?)MOVDDUPrm")>;
 955
 956 def SKLWriteResGroup68 : SchedWriteRes<[SKLPort01]> {
 957   let Latency = 6;
 958   let NumMicroOps = 2;
 959   let ReleaseAtCycles = [2];
 960 }
 961 def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSrr)>;
 962
 963 def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
 964   let Latency = 6;
 965   let NumMicroOps = 2;
 966   let ReleaseAtCycles = [1,1];
 967 }
 968 def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBrm,
 969                                           MMX_PADDSWrm,
 970                                           MMX_PADDUSBrm,
 971                                           MMX_PADDUSWrm,
 972                                           MMX_PAVGBrm,
 973                                           MMX_PAVGWrm,
 974                                           MMX_PCMPEQBrm,
 975                                           MMX_PCMPEQDrm,
 976                                           MMX_PCMPEQWrm,
 977                                           MMX_PCMPGTBrm,
 978                                           MMX_PCMPGTDrm,
 979                                           MMX_PCMPGTWrm,
 980                                           MMX_PMAXSWrm,
 981                                           MMX_PMAXUBrm,
 982                                           MMX_PMINSWrm,
 983                                           MMX_PMINUBrm,
 984                                           MMX_PSUBSBrm,
 985                                           MMX_PSUBSWrm,
 986                                           MMX_PSUBUSBrm,
 987                                           MMX_PSUBUSWrm)>;
 988
 989 def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
 990   let Latency = 6;
 991   let NumMicroOps = 2;
 992   let ReleaseAtCycles = [1,1];
 993 }
 994 def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64m)>;
 995 def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>;
 996
 997 def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
 998   let Latency = 6;
 999   let NumMicroOps = 2;
1000   let ReleaseAtCycles = [1,1];
1001 }
1002 def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",
1003                                              "MOVBE(16|32|64)rm")>;
1004
1005 def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1006   let Latency = 6;
1007   let NumMicroOps = 2;
1008   let ReleaseAtCycles = [1,1];
1009 }
1010 def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
1011 def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
1012
1013 def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1014   let Latency = 6;
1015   let NumMicroOps = 3;
1016   let ReleaseAtCycles = [2,1];
1017 }
1018 def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>;
1019
1020 def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
1021   let Latency = 6;
1022   let NumMicroOps = 4;
1023   let ReleaseAtCycles = [1,1,1,1];
1024 }
1025 def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;
1026
1027 def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1028   let Latency = 6;
1029   let NumMicroOps = 4;
1030   let ReleaseAtCycles = [1,1,1,1];
1031 }
1032 def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)",
1033                                              "SHL(8|16|32|64)m(1|i)",
1034                                              "SHR(8|16|32|64)m(1|i)")>;
1035
1036 def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1037   let Latency = 6;
1038   let NumMicroOps = 4;
1039   let ReleaseAtCycles = [1,1,1,1];
1040 }
1041 def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm",
1042                                              "PUSH(16|32|64)rmm")>;
1043
1044 def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
1045   let Latency = 6;
1046   let NumMicroOps = 6;
1047   let ReleaseAtCycles = [1,5];
1048 }
1049 def: InstRW<[SKLWriteResGroup84], (instrs STD)>;
1050
1051 def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
1052   let Latency = 7;
1053   let NumMicroOps = 1;
1054   let ReleaseAtCycles = [1];
1055 }
1056 def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>;
1057 def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128rm,
1058                                           VBROADCASTI128rm,
1059                                           VBROADCASTSDYrm,
1060                                           VBROADCASTSSYrm,
1061                                           VMOVDDUPYrm,
1062                                           VMOVSHDUPYrm,
1063                                           VMOVSLDUPYrm,
1064                                           VPBROADCASTDYrm,
1065                                           VPBROADCASTQYrm)>;
1066
1067 def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1068   let Latency = 6;
1069   let NumMicroOps = 2;
1070   let ReleaseAtCycles = [1,1];
1071 }
1072 def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm",
1073                                              "(V?)PMOV(SX|ZX)BQrm",
1074                                              "(V?)PMOV(SX|ZX)BWrm",
1075                                              "(V?)PMOV(SX|ZX)DQrm",
1076                                              "(V?)PMOV(SX|ZX)WDrm",
1077                                              "(V?)PMOV(SX|ZX)WQrm")>;
1078
1079 def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1080   let Latency = 7;
1081   let NumMicroOps = 2;
1082   let ReleaseAtCycles = [1,1];
1083 }
1084 def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rmi,
1085                                           VINSERTI128rmi,
1086                                           VPBLENDDrmi)>;
1087 def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd],
1088                                   (instregex "(V?)PADD(B|D|Q|W)rm",
1089                                              "(V?)PSUB(B|D|Q|W)rm")>;
1090
1091 def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1092   let Latency = 7;
1093   let NumMicroOps = 3;
1094   let ReleaseAtCycles = [2,1];
1095 }
1096 def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWrm,
1097                                           MMX_PACKSSWBrm,
1098                                           MMX_PACKUSWBrm)>;
1099
1100 def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1101   let Latency = 7;
1102   let NumMicroOps = 3;
1103   let ReleaseAtCycles = [1,2];
1104 }
1105 def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64,
1106                                           SCASB, SCASL, SCASQ, SCASW)>;
1107
1108 def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
1109   let Latency = 7;
1110   let NumMicroOps = 3;
1111   let ReleaseAtCycles = [1,1,1];
1112 }
1113 def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVT(T?)SS2SI64rr")>;
1114
1115 def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
1116   let Latency = 7;
1117   let NumMicroOps = 3;
1118   let ReleaseAtCycles = [1,1,1];
1119 }
1120 def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>;
1121
1122 def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
1123   let Latency = 7;
1124   let NumMicroOps = 3;
1125   let ReleaseAtCycles = [1,1,1];
1126 }
1127 def: InstRW<[SKLWriteResGroup98], (instrs LRET64, RET64)>;
1128
1129 def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1130   let Latency = 7;
1131   let NumMicroOps = 5;
1132   let ReleaseAtCycles = [1,1,1,2];
1133 }
1134 def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)",
1135                                               "ROR(8|16|32|64)m(1|i)")>;
1136
1137 def SKLWriteResGroup100_1 : SchedWriteRes<[SKLPort06]> {
1138   let Latency = 2;
1139   let NumMicroOps = 2;
1140   let ReleaseAtCycles = [2];
1141 }
1142 def: InstRW<[SKLWriteResGroup100_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1143                                              ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1144
1145 def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1146   let Latency = 7;
1147   let NumMicroOps = 5;
1148   let ReleaseAtCycles = [1,1,1,2];
1149 }
1150 def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
1151
1152 def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1153   let Latency = 7;
1154   let NumMicroOps = 5;
1155   let ReleaseAtCycles = [1,1,1,1,1];
1156 }
1157 def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>;
1158 def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64m)>;
1159
1160 def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
1161   let Latency = 7;
1162   let NumMicroOps = 7;
1163   let ReleaseAtCycles = [1,3,1,2];
1164 }
1165 def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
1166
1167 def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
1168   let Latency = 8;
1169   let NumMicroOps = 2;
1170   let ReleaseAtCycles = [1,1];
1171 }
1172 def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm",
1173                                               "PEXT(32|64)rm")>;
1174
1175 def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1176   let Latency = 8;
1177   let NumMicroOps = 2;
1178   let ReleaseAtCycles = [1,1];
1179 }
1180 def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m")>;
1181 def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm,
1182                                            VPBROADCASTWYrm,
1183                                            VPMOVSXBDYrm,
1184                                            VPMOVSXBQYrm,
1185                                            VPMOVSXWQYrm)>;
1186
1187 def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1188   let Latency = 8;
1189   let NumMicroOps = 2;
1190   let ReleaseAtCycles = [1,1];
1191 }
1192 def: InstRW<[SKLWriteResGroup110], (instrs VPBLENDDYrmi)>;
1193 def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd],
1194                                    (instregex "VPADD(B|D|Q|W)Yrm",
1195                                               "VPSUB(B|D|Q|W)Yrm")>;
1196
1197 def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1198   let Latency = 8;
1199   let NumMicroOps = 4;
1200   let ReleaseAtCycles = [1,2,1];
1201 }
1202 def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1203
1204 def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1205   let Latency = 8;
1206   let NumMicroOps = 5;
1207   let ReleaseAtCycles = [1,1,1,2];
1208 }
1209 def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)",
1210                                               "RCR(8|16|32|64)m(1|i)")>;
1211
1212 def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1213   let Latency = 8;
1214   let NumMicroOps = 6;
1215   let ReleaseAtCycles = [1,1,1,3];
1216 }
1217 def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
1218                                               "ROR(8|16|32|64)mCL",
1219                                               "SAR(8|16|32|64)mCL",
1220                                               "SHL(8|16|32|64)mCL",
1221                                               "SHR(8|16|32|64)mCL")>;
1222
1223 def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1224   let Latency = 8;
1225   let NumMicroOps = 6;
1226   let ReleaseAtCycles = [1,1,1,2,1];
1227 }
1228 def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;
1229
1230 def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1231   let Latency = 9;
1232   let NumMicroOps = 2;
1233   let ReleaseAtCycles = [1,1];
1234 }
1235 def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm,
1236                                            VPCMPGTQrm,
1237                                            VPMOVSXBWYrm,
1238                                            VPMOVSXDQYrm,
1239                                            VPMOVSXWDYrm,
1240                                            VPMOVZXWDYrm)>;
1241
1242 def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort0]> {
1243   let Latency = 9;
1244   let NumMicroOps = 2;
1245   let ReleaseAtCycles = [1,1];
1246 }
1247 def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIrm")>;
1248
1249 def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1250   let Latency = 9;
1251   let NumMicroOps = 4;
1252   let ReleaseAtCycles = [2,1,1];
1253 }
1254 def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",
1255                                               "(V?)PHSUBSWrm")>;
1256
1257 def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1258   let Latency = 9;
1259   let NumMicroOps = 5;
1260   let ReleaseAtCycles = [1,2,1,1];
1261 }
1262 def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
1263                                               "LSL(16|32|64)rm")>;
1264
1265 def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1266   let Latency = 10;
1267   let NumMicroOps = 2;
1268   let ReleaseAtCycles = [1,1];
1269 }
1270 def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1271                                               "ILD_F(16|32|64)m")>;
1272 def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>;
1273
1274 def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1275   let Latency = 10;
1276   let NumMicroOps = 4;
1277   let ReleaseAtCycles = [2,1,1];
1278 }
1279 def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm,
1280                                            VPHSUBSWYrm)>;
1281
1282 def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1283   let Latency = 10;
1284   let NumMicroOps = 8;
1285   let ReleaseAtCycles = [1,1,1,1,1,3];
1286 }
1287 def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
1288
1289 def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1290   let Latency = 11;
1291   let NumMicroOps = 2;
1292   let ReleaseAtCycles = [1,1];
1293 }
1294 def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>;
1295
1296 def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1297   let Latency = 11;
1298   let NumMicroOps = 3;
1299   let ReleaseAtCycles = [2,1];
1300 }
1301 def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>;
1302
1303 def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
1304   let Latency = 11;
1305   let NumMicroOps = 7;
1306   let ReleaseAtCycles = [2,3,2];
1307 }
1308 def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",
1309                                               "RCR(16|32|64)rCL")>;
1310
1311 def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1312   let Latency = 11;
1313   let NumMicroOps = 9;
1314   let ReleaseAtCycles = [1,5,1,2];
1315 }
1316 def: InstRW<[SKLWriteResGroup155], (instrs RCL8rCL)>;
1317
1318 def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
1319   let Latency = 11;
1320   let NumMicroOps = 11;
1321   let ReleaseAtCycles = [2,9];
1322 }
1323 def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
1324
1325 def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1326   let Latency = 13;
1327   let NumMicroOps = 3;
1328   let ReleaseAtCycles = [2,1];
1329 }
1330 def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1331
1332 def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1333   let Latency = 14;
1334   let NumMicroOps = 3;
1335   let ReleaseAtCycles = [1,1,1];
1336 }
1337 def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>;
1338
1339 def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1340   let Latency = 14;
1341   let NumMicroOps = 10;
1342   let ReleaseAtCycles = [2,4,1,3];
1343 }
1344 def: InstRW<[SKLWriteResGroup170], (instrs RCR8rCL)>;
1345
1346 def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {
1347   let Latency = 15;
1348   let NumMicroOps = 1;
1349   let ReleaseAtCycles = [1];
1350 }
1351 def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1352
1353 def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1354   let Latency = 15;
1355   let NumMicroOps = 10;
1356   let ReleaseAtCycles = [1,1,1,5,1,1];
1357 }
1358 def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;
1359
1360 def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1361   let Latency = 16;
1362   let NumMicroOps = 14;
1363   let ReleaseAtCycles = [1,1,1,4,2,5];
1364 }
1365 def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>;
1366
1367 def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {
1368   let Latency = 16;
1369   let NumMicroOps = 16;
1370   let ReleaseAtCycles = [16];
1371 }
1372 def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>;
1373
1374 def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
1375   let Latency = 17;
1376   let NumMicroOps = 15;
1377   let ReleaseAtCycles = [2,1,2,4,2,4];
1378 }
1379 def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>;
1380
1381 def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
1382   let Latency = 18;
1383   let NumMicroOps = 8;
1384   let ReleaseAtCycles = [1,1,1,5];
1385 }
1386 def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;
1387
1388 def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1389   let Latency = 18;
1390   let NumMicroOps = 11;
1391   let ReleaseAtCycles = [2,1,1,4,1,2];
1392 }
1393 def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
1394
1395 def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {
1396   let Latency = 20;
1397   let NumMicroOps = 1;
1398   let ReleaseAtCycles = [1];
1399 }
1400 def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1401
1402 def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1403   let Latency = 20;
1404   let NumMicroOps = 8;
1405   let ReleaseAtCycles = [1,1,1,1,1,1,2];
1406 }
1407 def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>;
1408
1409 def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
1410   let Latency = 20;
1411   let NumMicroOps = 10;
1412   let ReleaseAtCycles = [1,2,7];
1413 }
1414 def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>;
1415
1416 def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1417   let Latency = 22;
1418   let NumMicroOps = 2;
1419   let ReleaseAtCycles = [1,1];
1420 }
1421 def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>;
1422
1423 def SKLWriteResGroupVEX2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1424   let Latency = 18;
1425   let NumMicroOps = 5; // 2 uops perform multiple loads
1426   let ReleaseAtCycles = [1,2,1,1];
1427 }
1428 def: InstRW<[SKLWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
1429                                             VGATHERQPDrm, VPGATHERQQrm,
1430                                             VGATHERQPSrm, VPGATHERQDrm)>;
1431
1432 def SKLWriteResGroupVEX4 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1433   let Latency = 20;
1434   let NumMicroOps = 5; // 2 uops peform multiple loads
1435   let ReleaseAtCycles = [1,4,1,1];
1436 }
1437 def: InstRW<[SKLWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
1438                                             VGATHERDPSrm,  VPGATHERDDrm,
1439                                             VGATHERQPDYrm, VPGATHERQQYrm,
1440                                             VGATHERQPSYrm,  VPGATHERQDYrm)>;
1441
1442 def SKLWriteResGroupVEX8 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1443   let Latency = 22;
1444   let NumMicroOps = 5; // 2 uops perform multiple loads
1445   let ReleaseAtCycles = [1,8,1,1];
1446 }
1447 def: InstRW<[SKLWriteResGroupVEX8], (instrs VGATHERDPSYrm,  VPGATHERDDYrm)>;
1448
1449 def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1450   let Latency = 23;
1451   let NumMicroOps = 19;
1452   let ReleaseAtCycles = [2,1,4,1,1,4,6];
1453 }
1454 def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>;
1455
1456 def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1457   let Latency = 25;
1458   let NumMicroOps = 3;
1459   let ReleaseAtCycles = [1,1,1];
1460 }
1461 def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>;
1462
1463 def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1464   let Latency = 27;
1465   let NumMicroOps = 2;
1466   let ReleaseAtCycles = [1,1];
1467 }
1468 def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>;
1469
1470 def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1471   let Latency = 30;
1472   let NumMicroOps = 3;
1473   let ReleaseAtCycles = [1,1,1];
1474 }
1475 def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>;
1476
1477 def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
1478   let Latency = 35;
1479   let NumMicroOps = 23;
1480   let ReleaseAtCycles = [1,5,3,4,10];
1481 }
1482 def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",
1483                                               "IN(8|16|32)rr")>;
1484
1485 def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1486   let Latency = 35;
1487   let NumMicroOps = 23;
1488   let ReleaseAtCycles = [1,5,2,1,4,10];
1489 }
1490 def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",
1491                                               "OUT(8|16|32)rr")>;
1492
1493 def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1494   let Latency = 37;
1495   let NumMicroOps = 31;
1496   let ReleaseAtCycles = [1,8,1,21];
1497 }
1498 def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;
1499
1500 def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
1501   let Latency = 40;
1502   let NumMicroOps = 18;
1503   let ReleaseAtCycles = [1,1,2,3,1,1,1,8];
1504 }
1505 def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>;
1506
1507 def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1508   let Latency = 41;
1509   let NumMicroOps = 39;
1510   let ReleaseAtCycles = [1,10,1,1,26];
1511 }
1512 def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>;
1513
1514 def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
1515   let Latency = 42;
1516   let NumMicroOps = 22;
1517   let ReleaseAtCycles = [2,20];
1518 }
1519 def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>;
1520
1521 def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1522   let Latency = 42;
1523   let NumMicroOps = 40;
1524   let ReleaseAtCycles = [1,11,1,1,26];
1525 }
1526 def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>;
1527 def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>;
1528
1529 def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1530   let Latency = 46;
1531   let NumMicroOps = 44;
1532   let ReleaseAtCycles = [1,11,1,1,30];
1533 }
1534 def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;
1535
1536 def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
1537   let Latency = 62;
1538   let NumMicroOps = 64;
1539   let ReleaseAtCycles = [2,8,5,10,39];
1540 }
1541 def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>;
1542
1543 def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1544   let Latency = 63;
1545   let NumMicroOps = 88;
1546   let ReleaseAtCycles = [4,4,31,1,2,1,45];
1547 }
1548 def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>;
1549
1550 def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1551   let Latency = 63;
1552   let NumMicroOps = 90;
1553   let ReleaseAtCycles = [4,2,33,1,2,1,47];
1554 }
1555 def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>;
1556
1557 def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
1558   let Latency = 75;
1559   let NumMicroOps = 15;
1560   let ReleaseAtCycles = [6,3,6];
1561 }
1562 def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>;
1563
1564 def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
1565   let Latency = 106;
1566   let NumMicroOps = 100;
1567   let ReleaseAtCycles = [9,1,11,16,1,11,21,30];
1568 }
1569 def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>;
1570
1571 def: InstRW<[WriteZero], (instrs CLC)>;
1572
1573
1574 // Instruction variants handled by the renamer. These might not need execution
1575 // ports in certain conditions.
1576 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
1577 // section "Skylake Pipeline" > "Register allocation and renaming".
1578 // These can be investigated with llvm-exegesis, e.g.
1579 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1580 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1581
1582 def SKLWriteZeroLatency : SchedWriteRes<[]> {
1583   let Latency = 0;
1584 }
1585
1586 def SKLWriteZeroIdiom : SchedWriteVariant<[
1587     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1588     SchedVar<NoSchedPred,                          [WriteALU]>
1589 ]>;
1590 def : InstRW<[SKLWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
1591                                           XOR32rr, XOR64rr)>;
1592
1593 def SKLWriteFZeroIdiom : SchedWriteVariant<[
1594     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1595     SchedVar<NoSchedPred,                          [WriteFLogic]>
1596 ]>;
1597 def : InstRW<[SKLWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr,
1598                                            VXORPDrr)>;
1599
1600 def SKLWriteFZeroIdiomY : SchedWriteVariant<[
1601     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1602     SchedVar<NoSchedPred,                          [WriteFLogicY]>
1603 ]>;
1604 def : InstRW<[SKLWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>;
1605
1606 def SKLWriteVZeroIdiomLogicX : SchedWriteVariant<[
1607     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1608     SchedVar<NoSchedPred,                          [WriteVecLogicX]>
1609 ]>;
1610 def : InstRW<[SKLWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>;
1611
1612 def SKLWriteVZeroIdiomLogicY : SchedWriteVariant<[
1613     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1614     SchedVar<NoSchedPred,                          [WriteVecLogicY]>
1615 ]>;
1616 def : InstRW<[SKLWriteVZeroIdiomLogicY], (instrs VPXORYrr)>;
1617
1618 def SKLWriteVZeroIdiomALUX : SchedWriteVariant<[
1619     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1620     SchedVar<NoSchedPred,                          [WriteVecALUX]>
1621 ]>;
1622 def : InstRW<[SKLWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr,
1623                                                PCMPGTDrr, VPCMPGTDrr,
1624                                                PCMPGTWrr, VPCMPGTWrr)>;
1625
1626 def SKLWriteVZeroIdiomALUY : SchedWriteVariant<[
1627     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1628     SchedVar<NoSchedPred,                          [WriteVecALUY]>
1629 ]>;
1630 def : InstRW<[SKLWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
1631                                                VPCMPGTDYrr,
1632                                                VPCMPGTWYrr)>;
1633
1634 def SKLWritePSUB : SchedWriteRes<[SKLPort015]> {
1635   let Latency = 1;
1636   let NumMicroOps = 1;
1637   let ReleaseAtCycles = [1];
1638 }
1639
1640 def SKLWriteVZeroIdiomPSUB : SchedWriteVariant<[
1641     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1642     SchedVar<NoSchedPred,                          [SKLWritePSUB]>
1643 ]>;
1644 def : InstRW<[SKLWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr,
1645                                                PSUBDrr, VPSUBDrr,
1646                                                PSUBQrr, VPSUBQrr,
1647                                                PSUBWrr, VPSUBWrr,
1648                                                VPSUBBYrr,
1649                                                VPSUBDYrr,
1650                                                VPSUBQYrr,
1651                                                VPSUBWYrr)>;
1652
1653 def SKLWritePCMPGTQ : SchedWriteRes<[SKLPort5]> {
1654   let Latency = 3;
1655   let NumMicroOps = 1;
1656   let ReleaseAtCycles = [1];
1657 }
1658
1659 def SKLWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
1660     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1661     SchedVar<NoSchedPred,                          [SKLWritePCMPGTQ]>
1662 ]>;
1663 def : InstRW<[SKLWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
1664                                                   VPCMPGTQYrr)>;
1665
1666
1667 // CMOVs that use both Z and C flag require an extra uop.
1668 def SKLWriteCMOVA_CMOVBErr : SchedWriteRes<[SKLPort06]> {
1669   let Latency = 2;
1670   let ReleaseAtCycles = [2];
1671   let NumMicroOps = 2;
1672 }
1673
1674 def SKLWriteCMOVA_CMOVBErm : SchedWriteRes<[SKLPort23,SKLPort06]> {
1675   let Latency = 7;
1676   let ReleaseAtCycles = [1,2];
1677   let NumMicroOps = 3;
1678 }
1679
1680 def SKLCMOVA_CMOVBErr :  SchedWriteVariant<[
1681   SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKLWriteCMOVA_CMOVBErr]>,
1682   SchedVar<NoSchedPred,                             [WriteCMOV]>
1683 ]>;
1684
1685 def SKLCMOVA_CMOVBErm :  SchedWriteVariant<[
1686   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKLWriteCMOVA_CMOVBErm]>,
1687   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
1688 ]>;
1689
1690 def : InstRW<[SKLCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
1691 def : InstRW<[SKLCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
1692
1693 // SETCCs that use both Z and C flag require an extra uop.
1694 def SKLWriteSETA_SETBEr : SchedWriteRes<[SKLPort06]> {
1695   let Latency = 2;
1696   let ReleaseAtCycles = [2];
1697   let NumMicroOps = 2;
1698 }
1699
1700 def SKLWriteSETA_SETBEm : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
1701   let Latency = 3;
1702   let ReleaseAtCycles = [1,1,2];
1703   let NumMicroOps = 4;
1704 }
1705
1706 def SKLSETA_SETBErr :  SchedWriteVariant<[
1707   SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKLWriteSETA_SETBEr]>,
1708   SchedVar<NoSchedPred,                         [WriteSETCC]>
1709 ]>;
1710
1711 def SKLSETA_SETBErm :  SchedWriteVariant<[
1712   SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKLWriteSETA_SETBEm]>,
1713   SchedVar<NoSchedPred,                         [WriteSETCCStore]>
1714 ]>;
1715
1716 def : InstRW<[SKLSETA_SETBErr], (instrs SETCCr)>;
1717 def : InstRW<[SKLSETA_SETBErm], (instrs SETCCm)>;
1718
1719 ///////////////////////////////////////////////////////////////////////////////
1720 // Dependency breaking instructions.
1721 ///////////////////////////////////////////////////////////////////////////////
1722
1723 def : IsZeroIdiomFunction<[
1724   // GPR Zero-idioms.
1725   DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>,
1726
1727   // SSE Zero-idioms.
1728   DepBreakingClass<[
1729     // fp variants.
1730     XORPSrr, XORPDrr,
1731
1732     // int variants.
1733     PXORrr,
1734     PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr,
1735     PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr
1736   ], ZeroIdiomPredicate>,
1737
1738   // AVX Zero-idioms.
1739   DepBreakingClass<[
1740     // xmm fp variants.
1741     VXORPSrr, VXORPDrr,
1742
1743     // xmm int variants.
1744     VPXORrr,
1745     VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,
1746     VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr,
1747
1748     // ymm variants.
1749     VXORPSYrr, VXORPDYrr, VPXORYrr,
1750     VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr,
1751     VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr
1752   ], ZeroIdiomPredicate>,
1753 ]>;
1754
1755 } // SchedModel