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1 //=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the machine model for Skylake Server to support
10 // instruction scheduling and other instruction cost heuristics.
11 //
12 //===----------------------------------------------------------------------===//
14 def SkylakeServerModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and SKylake can
16 // decode 6 instructions per cycle.
17 let IssueWidth = 6;
18 let MicroOpBufferSize = 224; // Based on the reorder buffer.
19 let LoadLatency = 5;
20 let MispredictPenalty = 14;
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
25 // This flag is set to allow the scheduler to assign a default model to
26 // unrecognized opcodes.
27 let CompleteModel = 0;
28 }
30 let SchedModel = SkylakeServerModel in {
32 // Skylake Server can issue micro-ops to 8 different ports in one cycle.
34 // Ports 0, 1, 5, and 6 handle all computation.
35 // Port 4 gets the data half of stores. Store data can be available later than
36 // the store address, but since we don't model the latency of stores, we can
37 // ignore that.
38 // Ports 2 and 3 are identical. They handle loads and the address half of
39 // stores. Port 7 can handle address calculations.
40 def SKXPort0 : ProcResource<1>;
41 def SKXPort1 : ProcResource<1>;
42 def SKXPort2 : ProcResource<1>;
43 def SKXPort3 : ProcResource<1>;
44 def SKXPort4 : ProcResource<1>;
45 def SKXPort5 : ProcResource<1>;
46 def SKXPort6 : ProcResource<1>;
47 def SKXPort7 : ProcResource<1>;
49 // Many micro-ops are capable of issuing on multiple ports.
50 def SKXPort01 : ProcResGroup<[SKXPort0, SKXPort1]>;
51 def SKXPort23 : ProcResGroup<[SKXPort2, SKXPort3]>;
52 def SKXPort237 : ProcResGroup<[SKXPort2, SKXPort3, SKXPort7]>;
53 def SKXPort04 : ProcResGroup<[SKXPort0, SKXPort4]>;
54 def SKXPort05 : ProcResGroup<[SKXPort0, SKXPort5]>;
55 def SKXPort06 : ProcResGroup<[SKXPort0, SKXPort6]>;
56 def SKXPort15 : ProcResGroup<[SKXPort1, SKXPort5]>;
57 def SKXPort16 : ProcResGroup<[SKXPort1, SKXPort6]>;
58 def SKXPort56 : ProcResGroup<[SKXPort5, SKXPort6]>;
59 def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>;
60 def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>;
61 def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>;
63 def SKXDivider : ProcResource<1>; // Integer division issued on port 0.
64 // FP division and sqrt on port 0.
65 def SKXFPDivider : ProcResource<1>;
67 // 60 Entry Unified Scheduler
68 def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4,
69 SKXPort5, SKXPort6, SKXPort7]> {
70 let BufferSize=60;
71 }
73 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
74 // cycles after the memory operand.
75 def : ReadAdvance<ReadAfterLd, 5>;
77 // Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
78 // until 5/6/7 cycles after the memory operand.
79 def : ReadAdvance<ReadAfterVecLd, 5>;
80 def : ReadAdvance<ReadAfterVecXLd, 6>;
81 def : ReadAdvance<ReadAfterVecYLd, 7>;
83 def : ReadAdvance<ReadInt2Fpu, 0>;
85 // Many SchedWrites are defined in pairs with and without a folded load.
86 // Instructions with folded loads are usually micro-fused, so they only appear
87 // as two micro-ops when queued in the reservation station.
88 // This multiclass defines the resource usage for variants with and without
89 // folded loads.
90 multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW,
91 list<ProcResourceKind> ExePorts,
92 int Lat, list<int> Res = [1], int UOps = 1,
93 int LoadLat = 5, int LoadUOps = 1> {
94 // Register variant is using a single cycle on ExePort.
95 def : WriteRes<SchedRW, ExePorts> {
96 let Latency = Lat;
97 let ReleaseAtCycles = Res;
98 let NumMicroOps = UOps;
99 }
101 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
102 // the latency (default = 5).
103 def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> {
104 let Latency = !add(Lat, LoadLat);
105 let ReleaseAtCycles = !listconcat([1], Res);
106 let NumMicroOps = !add(UOps, LoadUOps);
107 }
108 }
110 // A folded store needs a cycle on port 4 for the store data, and an extra port
111 // 2/3/7 cycle to recompute the address.
112 def : WriteRes<WriteRMW, [SKXPort237,SKXPort4]>;
114 // Arithmetic.
115 defm : SKXWriteResPair<WriteALU, [SKXPort0156], 1>; // Simple integer ALU op.
116 defm : SKXWriteResPair<WriteADC, [SKXPort06], 1>; // Integer ALU + flags op.
118 // Integer multiplication.
119 defm : SKXWriteResPair<WriteIMul8, [SKXPort1], 3>;
120 defm : SKXWriteResPair<WriteIMul16, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,2], 4>;
121 defm : X86WriteRes<WriteIMul16Imm, [SKXPort1,SKXPort0156], 4, [1,1], 2>;
122 defm : X86WriteRes<WriteIMul16ImmLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;
123 defm : X86WriteRes<WriteIMul16Reg, [SKXPort1], 3, [1], 1>;
124 defm : X86WriteRes<WriteIMul16RegLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;
125 defm : SKXWriteResPair<WriteIMul32, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,1], 3>;
126 defm : SKXWriteResPair<WriteMULX32, [SKXPort1,SKXPort06,SKXPort0156], 3, [1,1,1], 3>;
127 defm : SKXWriteResPair<WriteIMul32Imm, [SKXPort1], 3>;
128 defm : SKXWriteResPair<WriteIMul32Reg, [SKXPort1], 3>;
129 defm : SKXWriteResPair<WriteIMul64, [SKXPort1,SKXPort5], 4, [1,1], 2>;
130 defm : SKXWriteResPair<WriteMULX64, [SKXPort1,SKXPort5], 3, [1,1], 2>;
131 defm : SKXWriteResPair<WriteIMul64Imm, [SKXPort1], 3>;
132 defm : SKXWriteResPair<WriteIMul64Reg, [SKXPort1], 3>;
133 def SKXWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }
134 def : WriteRes<WriteIMulHLd, []> {
135 let Latency = !add(SKXWriteIMulH.Latency, SkylakeServerModel.LoadLatency);
136 }
138 defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>;
139 defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>;
140 defm : X86WriteRes<WriteCMPXCHG,[SKXPort06, SKXPort0156], 5, [2,3], 5>;
141 defm : X86WriteRes<WriteCMPXCHGRMW,[SKXPort23,SKXPort06,SKXPort0156,SKXPort237,SKXPort4], 8, [1,2,1,1,1], 6>;
142 defm : X86WriteRes<WriteXCHG, [SKXPort0156], 2, [3], 3>;
144 // TODO: Why isn't the SKXDivider used?
145 defm : SKXWriteResPair<WriteDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
146 defm : X86WriteRes<WriteDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
147 defm : X86WriteRes<WriteDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
148 defm : X86WriteRes<WriteDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
149 defm : X86WriteRes<WriteDiv16Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
150 defm : X86WriteRes<WriteDiv32Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
151 defm : X86WriteRes<WriteDiv64Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
153 defm : X86WriteRes<WriteIDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1>;
154 defm : X86WriteRes<WriteIDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
155 defm : X86WriteRes<WriteIDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
156 defm : X86WriteRes<WriteIDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
157 defm : X86WriteRes<WriteIDiv8Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
158 defm : X86WriteRes<WriteIDiv16Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
159 defm : X86WriteRes<WriteIDiv32Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
160 defm : X86WriteRes<WriteIDiv64Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
162 defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>;
164 def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.
166 defm : SKXWriteResPair<WriteCMOV, [SKXPort06], 1, [1], 1>; // Conditional move.
167 defm : X86WriteRes<WriteFCMOV, [SKXPort1], 3, [1], 1>; // x87 conditional move.
168 def : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
169 def : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> {
170 let Latency = 2;
171 let NumMicroOps = 3;
172 }
173 defm : X86WriteRes<WriteLAHFSAHF, [SKXPort06], 1, [1], 1>;
174 defm : X86WriteRes<WriteBitTest, [SKXPort06], 1, [1], 1>;
175 defm : X86WriteRes<WriteBitTestImmLd, [SKXPort06,SKXPort23], 6, [1,1], 2>;
176 defm : X86WriteRes<WriteBitTestRegLd, [SKXPort0156,SKXPort23], 6, [1,1], 2>;
177 defm : X86WriteRes<WriteBitTestSet, [SKXPort06], 1, [1], 1>;
178 defm : X86WriteRes<WriteBitTestSetImmLd, [SKXPort06,SKXPort23], 5, [1,1], 3>;
179 defm : X86WriteRes<WriteBitTestSetRegLd, [SKXPort0156,SKXPort23], 5, [1,1], 2>;
181 // Integer shifts and rotates.
182 defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;
183 defm : SKXWriteResPair<WriteShiftCL, [SKXPort06], 3, [3], 3>;
184 defm : SKXWriteResPair<WriteRotate, [SKXPort06], 1, [1], 1>;
185 defm : SKXWriteResPair<WriteRotateCL, [SKXPort06], 3, [3], 3>;
187 // SHLD/SHRD.
188 defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>;
189 defm : X86WriteRes<WriteSHDrrcl,[SKXPort1,SKXPort06,SKXPort0156], 6, [1, 2, 1], 4>;
190 defm : X86WriteRes<WriteSHDmri, [SKXPort1,SKXPort23,SKXPort237,SKXPort0156], 9, [1, 1, 1, 1], 4>;
191 defm : X86WriteRes<WriteSHDmrcl,[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort0156], 11, [1, 1, 1, 2, 1], 6>;
193 // Bit counts.
194 defm : SKXWriteResPair<WriteBSF, [SKXPort1], 3>;
195 defm : SKXWriteResPair<WriteBSR, [SKXPort1], 3>;
196 defm : SKXWriteResPair<WriteLZCNT, [SKXPort1], 3>;
197 defm : SKXWriteResPair<WriteTZCNT, [SKXPort1], 3>;
198 defm : SKXWriteResPair<WritePOPCNT, [SKXPort1], 3>;
200 // BMI1 BEXTR/BLS, BMI2 BZHI
201 defm : SKXWriteResPair<WriteBEXTR, [SKXPort06,SKXPort15], 2, [1,1], 2>;
202 defm : SKXWriteResPair<WriteBLS, [SKXPort15], 1>;
203 defm : SKXWriteResPair<WriteBZHI, [SKXPort15], 1>;
205 // Loads, stores, and moves, not folded with other operations.
206 defm : X86WriteRes<WriteLoad, [SKXPort23], 5, [1], 1>;
207 defm : X86WriteRes<WriteStore, [SKXPort237, SKXPort4], 1, [1,1], 1>;
208 defm : X86WriteRes<WriteStoreNT, [SKXPort237, SKXPort4], 1, [1,1], 2>;
209 defm : X86WriteRes<WriteMove, [SKXPort0156], 1, [1], 1>;
211 // Model the effect of clobbering the read-write mask operand of the GATHER operation.
212 // Does not cost anything by itself, only has latency, matching that of the WriteLoad,
213 defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;
215 // Idioms that clear a register, like xorps %xmm0, %xmm0.
216 // These can often bypass execution ports completely.
217 def : WriteRes<WriteZero, []>;
219 // Branches don't produce values, so they have no latency, but they still
220 // consume resources. Indirect branches can fold loads.
221 defm : SKXWriteResPair<WriteJump, [SKXPort06], 1>;
223 // Floating point. This covers both scalar and vector operations.
224 defm : X86WriteRes<WriteFLD0, [SKXPort05], 1, [1], 1>;
225 defm : X86WriteRes<WriteFLD1, [SKXPort05], 1, [2], 2>;
226 defm : X86WriteRes<WriteFLDC, [SKXPort05], 1, [2], 2>;
227 defm : X86WriteRes<WriteFLoad, [SKXPort23], 5, [1], 1>;
228 defm : X86WriteRes<WriteFLoadX, [SKXPort23], 6, [1], 1>;
229 defm : X86WriteRes<WriteFLoadY, [SKXPort23], 7, [1], 1>;
230 defm : X86WriteRes<WriteFMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>;
231 defm : X86WriteRes<WriteFMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>;
232 defm : X86WriteRes<WriteFStore, [SKXPort237,SKXPort4], 1, [1,1], 2>;
233 defm : X86WriteRes<WriteFStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>;
234 defm : X86WriteRes<WriteFStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
235 defm : X86WriteRes<WriteFStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>;
236 defm : X86WriteRes<WriteFStoreNTX, [SKXPort237,SKXPort4], 1, [1,1], 2>;
237 defm : X86WriteRes<WriteFStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
239 defm : X86WriteRes<WriteFMaskedStore32, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;
240 defm : X86WriteRes<WriteFMaskedStore32Y, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;
241 defm : X86WriteRes<WriteFMaskedStore64, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;
242 defm : X86WriteRes<WriteFMaskedStore64Y, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;
244 defm : X86WriteRes<WriteFMove, [SKXPort015], 1, [1], 1>;
245 defm : X86WriteRes<WriteFMoveX, [SKXPort015], 1, [1], 1>;
246 defm : X86WriteRes<WriteFMoveY, [SKXPort015], 1, [1], 1>;
247 defm : X86WriteRes<WriteFMoveZ, [SKXPort05], 1, [1], 1>;
248 defm : X86WriteRes<WriteEMMS, [SKXPort05,SKXPort0156], 10, [9,1], 10>;
250 defm : SKXWriteResPair<WriteFAdd, [SKXPort01], 4, [1], 1, 5>; // Floating point add/sub.
251 defm : SKXWriteResPair<WriteFAddX, [SKXPort01], 4, [1], 1, 6>;
252 defm : SKXWriteResPair<WriteFAddY, [SKXPort01], 4, [1], 1, 7>;
253 defm : SKXWriteResPair<WriteFAddZ, [SKXPort05], 4, [1], 1, 7>;
254 defm : SKXWriteResPair<WriteFAdd64, [SKXPort01], 4, [1], 1, 5>; // Floating point double add/sub.
255 defm : SKXWriteResPair<WriteFAdd64X, [SKXPort01], 4, [1], 1, 6>;
256 defm : SKXWriteResPair<WriteFAdd64Y, [SKXPort01], 4, [1], 1, 7>;
257 defm : SKXWriteResPair<WriteFAdd64Z, [SKXPort05], 4, [1], 1, 7>;
259 defm : SKXWriteResPair<WriteFCmp, [SKXPort01], 4, [1], 1, 5>; // Floating point compare.
260 defm : SKXWriteResPair<WriteFCmpX, [SKXPort01], 4, [1], 1, 6>;
261 defm : SKXWriteResPair<WriteFCmpY, [SKXPort01], 4, [1], 1, 7>;
262 defm : SKXWriteResPair<WriteFCmpZ, [SKXPort05], 4, [1], 1, 7>;
263 defm : SKXWriteResPair<WriteFCmp64, [SKXPort01], 4, [1], 1, 5>; // Floating point double compare.
264 defm : SKXWriteResPair<WriteFCmp64X, [SKXPort01], 4, [1], 1, 6>;
265 defm : SKXWriteResPair<WriteFCmp64Y, [SKXPort01], 4, [1], 1, 7>;
266 defm : SKXWriteResPair<WriteFCmp64Z, [SKXPort05], 4, [1], 1, 7>;
268 defm : SKXWriteResPair<WriteFCom, [SKXPort0], 2>; // Floating point compare to flags (X87).
269 defm : SKXWriteResPair<WriteFComX, [SKXPort0], 2>; // Floating point compare to flags (SSE).
271 defm : SKXWriteResPair<WriteFMul, [SKXPort01], 4, [1], 1, 5>; // Floating point multiplication.
272 defm : SKXWriteResPair<WriteFMulX, [SKXPort01], 4, [1], 1, 6>;
273 defm : SKXWriteResPair<WriteFMulY, [SKXPort01], 4, [1], 1, 7>;
274 defm : SKXWriteResPair<WriteFMulZ, [SKXPort05], 4, [1], 1, 7>;
275 defm : SKXWriteResPair<WriteFMul64, [SKXPort01], 4, [1], 1, 5>; // Floating point double multiplication.
276 defm : SKXWriteResPair<WriteFMul64X, [SKXPort01], 4, [1], 1, 6>;
277 defm : SKXWriteResPair<WriteFMul64Y, [SKXPort01], 4, [1], 1, 7>;
278 defm : SKXWriteResPair<WriteFMul64Z, [SKXPort05], 4, [1], 1, 7>;
280 defm : SKXWriteResPair<WriteFDiv, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
281 defm : SKXWriteResPair<WriteFDivX, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles.
282 defm : SKXWriteResPair<WriteFDivY, [SKXPort0,SKXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles.
283 defm : SKXWriteResPair<WriteFDivZ, [SKXPort0,SKXPort5,SKXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles.
284 defm : SKXWriteResPair<WriteFDiv64, [SKXPort0,SKXFPDivider], 14, [1,4], 1, 5>; // 10-14 cycles. // Floating point division.
285 defm : SKXWriteResPair<WriteFDiv64X, [SKXPort0,SKXFPDivider], 14, [1,4], 1, 6>; // 10-14 cycles.
286 defm : SKXWriteResPair<WriteFDiv64Y, [SKXPort0,SKXFPDivider], 14, [1,8], 1, 7>; // 10-14 cycles.
287 defm : SKXWriteResPair<WriteFDiv64Z, [SKXPort0,SKXPort5,SKXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles.
289 defm : SKXWriteResPair<WriteFSqrt, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
290 defm : SKXWriteResPair<WriteFSqrtX, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 6>;
291 defm : SKXWriteResPair<WriteFSqrtY, [SKXPort0,SKXFPDivider], 12, [1,6], 1, 7>;
292 defm : SKXWriteResPair<WriteFSqrtZ, [SKXPort0,SKXPort5,SKXFPDivider], 20, [2,1,12], 3, 7>;
293 defm : SKXWriteResPair<WriteFSqrt64, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
294 defm : SKXWriteResPair<WriteFSqrt64X, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 6>;
295 defm : SKXWriteResPair<WriteFSqrt64Y, [SKXPort0,SKXFPDivider], 18, [1,12],1, 7>;
296 defm : SKXWriteResPair<WriteFSqrt64Z, [SKXPort0,SKXPort5,SKXFPDivider], 32, [2,1,24], 3, 7>;
297 defm : SKXWriteResPair<WriteFSqrt80, [SKXPort0,SKXFPDivider], 21, [1,7]>; // Floating point long double square root.
299 defm : SKXWriteResPair<WriteFRcp, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.
300 defm : SKXWriteResPair<WriteFRcpX, [SKXPort0], 4, [1], 1, 6>;
301 defm : SKXWriteResPair<WriteFRcpY, [SKXPort0], 4, [1], 1, 7>;
302 defm : SKXWriteResPair<WriteFRcpZ, [SKXPort0,SKXPort5], 4, [2,1], 3, 7>;
304 defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.
305 defm : SKXWriteResPair<WriteFRsqrtX,[SKXPort0], 4, [1], 1, 6>;
306 defm : SKXWriteResPair<WriteFRsqrtY,[SKXPort0], 4, [1], 1, 7>;
307 defm : SKXWriteResPair<WriteFRsqrtZ,[SKXPort0,SKXPort5], 9, [2,1], 3, 7>;
309 defm : SKXWriteResPair<WriteFMA, [SKXPort01], 4, [1], 1, 5>; // Fused Multiply Add.
310 defm : SKXWriteResPair<WriteFMAX, [SKXPort01], 4, [1], 1, 6>;
311 defm : SKXWriteResPair<WriteFMAY, [SKXPort01], 4, [1], 1, 7>;
312 defm : SKXWriteResPair<WriteFMAZ, [SKXPort05], 4, [1], 1, 7>;
313 defm : SKXWriteResPair<WriteDPPD, [SKXPort5,SKXPort015], 9, [1,2], 3, 6>; // Floating point double dot product.
314 defm : X86WriteRes<WriteDPPS, [SKXPort5,SKXPort01], 13, [1,3], 4>;
315 defm : X86WriteRes<WriteDPPSY, [SKXPort5,SKXPort01], 13, [1,3], 4>;
316 defm : X86WriteRes<WriteDPPSLd, [SKXPort5,SKXPort01,SKXPort06,SKXPort23], 19, [1,3,1,1], 6>;
317 defm : X86WriteRes<WriteDPPSYLd, [SKXPort5,SKXPort01,SKXPort06,SKXPort23], 20, [1,3,1,1], 6>;
318 defm : SKXWriteResPair<WriteFSign, [SKXPort0], 1>; // Floating point fabs/fchs.
319 defm : SKXWriteResPair<WriteFRnd, [SKXPort01], 8, [2], 2, 6>; // Floating point rounding.
320 defm : SKXWriteResPair<WriteFRndY, [SKXPort01], 8, [2], 2, 7>;
321 defm : SKXWriteResPair<WriteFRndZ, [SKXPort05], 8, [2], 2, 7>;
322 defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
323 defm : SKXWriteResPair<WriteFLogicY, [SKXPort015], 1, [1], 1, 7>;
324 defm : SKXWriteResPair<WriteFLogicZ, [SKXPort05], 1, [1], 1, 7>;
325 defm : SKXWriteResPair<WriteFTest, [SKXPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
326 defm : SKXWriteResPair<WriteFTestY, [SKXPort0], 2, [1], 1, 7>;
327 defm : SKXWriteResPair<WriteFTestZ, [SKXPort0], 2, [1], 1, 7>;
328 defm : SKXWriteResPair<WriteFShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
329 defm : SKXWriteResPair<WriteFShuffleY, [SKXPort5], 1, [1], 1, 7>;
330 defm : SKXWriteResPair<WriteFShuffleZ, [SKXPort5], 1, [1], 1, 7>;
331 defm : SKXWriteResPair<WriteFVarShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
332 defm : SKXWriteResPair<WriteFVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
333 defm : SKXWriteResPair<WriteFVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
334 defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1, [1], 1, 6>; // Floating point vector blends.
335 defm : SKXWriteResPair<WriteFBlendY,[SKXPort015], 1, [1], 1, 7>;
336 defm : SKXWriteResPair<WriteFBlendZ,[SKXPort015], 1, [1], 1, 7>;
337 defm : SKXWriteResPair<WriteFVarBlend, [SKXPort015], 2, [2], 2, 6>; // Fp vector variable blends.
338 defm : SKXWriteResPair<WriteFVarBlendY,[SKXPort015], 2, [2], 2, 7>;
339 defm : SKXWriteResPair<WriteFVarBlendZ,[SKXPort015], 2, [2], 2, 7>;
341 // FMA Scheduling helper class.
342 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
344 // Vector integer operations.
345 defm : X86WriteRes<WriteVecLoad, [SKXPort23], 5, [1], 1>;
346 defm : X86WriteRes<WriteVecLoadX, [SKXPort23], 6, [1], 1>;
347 defm : X86WriteRes<WriteVecLoadY, [SKXPort23], 7, [1], 1>;
348 defm : X86WriteRes<WriteVecLoadNT, [SKXPort23,SKXPort015], 7, [1,1], 2>;
349 defm : X86WriteRes<WriteVecLoadNTY, [SKXPort23,SKXPort015], 8, [1,1], 2>;
350 defm : X86WriteRes<WriteVecMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>;
351 defm : X86WriteRes<WriteVecMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>;
352 defm : X86WriteRes<WriteVecStore, [SKXPort237,SKXPort4], 1, [1,1], 2>;
353 defm : X86WriteRes<WriteVecStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>;
354 defm : X86WriteRes<WriteVecStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
355 defm : X86WriteRes<WriteVecStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>;
356 defm : X86WriteRes<WriteVecStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
357 defm : X86WriteRes<WriteVecMaskedStore32, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;
358 defm : X86WriteRes<WriteVecMaskedStore32Y, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;
359 defm : X86WriteRes<WriteVecMaskedStore64, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;
360 defm : X86WriteRes<WriteVecMaskedStore64Y, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;
361 defm : X86WriteRes<WriteVecMove, [SKXPort05], 1, [1], 1>;
362 defm : X86WriteRes<WriteVecMoveX, [SKXPort015], 1, [1], 1>;
363 defm : X86WriteRes<WriteVecMoveY, [SKXPort015], 1, [1], 1>;
364 defm : X86WriteRes<WriteVecMoveZ, [SKXPort05], 1, [1], 1>;
365 defm : X86WriteRes<WriteVecMoveToGpr, [SKXPort0], 2, [1], 1>;
366 defm : X86WriteRes<WriteVecMoveFromGpr, [SKXPort5], 1, [1], 1>;
368 defm : SKXWriteResPair<WriteVecALU, [SKXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
369 defm : SKXWriteResPair<WriteVecALUX, [SKXPort01], 1, [1], 1, 6>;
370 defm : SKXWriteResPair<WriteVecALUY, [SKXPort01], 1, [1], 1, 7>;
371 defm : SKXWriteResPair<WriteVecALUZ, [SKXPort0], 1, [1], 1, 7>;
372 defm : SKXWriteResPair<WriteVecLogic, [SKXPort05], 1, [1], 1, 5>; // Vector integer and/or/xor.
373 defm : SKXWriteResPair<WriteVecLogicX,[SKXPort015], 1, [1], 1, 6>;
374 defm : SKXWriteResPair<WriteVecLogicY,[SKXPort015], 1, [1], 1, 7>;
375 defm : SKXWriteResPair<WriteVecLogicZ,[SKXPort05], 1, [1], 1, 7>;
376 defm : SKXWriteResPair<WriteVecTest, [SKXPort0,SKXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
377 defm : SKXWriteResPair<WriteVecTestY, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
378 defm : SKXWriteResPair<WriteVecTestZ, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
379 defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 5, [1], 1, 5>; // Vector integer multiply.
380 defm : SKXWriteResPair<WriteVecIMulX, [SKXPort01], 5, [1], 1, 6>;
381 defm : SKXWriteResPair<WriteVecIMulY, [SKXPort01], 5, [1], 1, 7>;
382 defm : SKXWriteResPair<WriteVecIMulZ, [SKXPort05], 5, [1], 1, 7>;
383 defm : SKXWriteResPair<WritePMULLD, [SKXPort01], 10, [2], 2, 6>; // Vector PMULLD.
384 defm : SKXWriteResPair<WritePMULLDY, [SKXPort01], 10, [2], 2, 7>;
385 defm : SKXWriteResPair<WritePMULLDZ, [SKXPort05], 10, [2], 2, 7>;
386 defm : SKXWriteResPair<WriteShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector shuffles.
387 defm : SKXWriteResPair<WriteShuffleX, [SKXPort5], 1, [1], 1, 6>;
388 defm : SKXWriteResPair<WriteShuffleY, [SKXPort5], 1, [1], 1, 7>;
389 defm : SKXWriteResPair<WriteShuffleZ, [SKXPort5], 1, [1], 1, 7>;
390 defm : SKXWriteResPair<WriteVarShuffle, [SKXPort0,SKXPort5], 1, [1,1], 2, 5>; // Vector variable shuffles.
391 defm : SKXWriteResPair<WriteVarShuffleX, [SKXPort5], 1, [1], 1, 6>;
392 defm : SKXWriteResPair<WriteVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
393 defm : SKXWriteResPair<WriteVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
394 defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends.
395 defm : SKXWriteResPair<WriteBlendY,[SKXPort5], 1, [1], 1, 7>;
396 defm : SKXWriteResPair<WriteBlendZ,[SKXPort5], 1, [1], 1, 7>;
397 defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends.
398 defm : SKXWriteResPair<WriteVarBlendY,[SKXPort015], 2, [2], 2, 6>;
399 defm : SKXWriteResPair<WriteVarBlendZ,[SKXPort05], 2, [1], 1, 6>;
400 defm : SKXWriteResPair<WriteMPSAD, [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD.
401 defm : SKXWriteResPair<WriteMPSADY, [SKXPort5], 4, [2], 2, 7>;
402 defm : SKXWriteResPair<WriteMPSADZ, [SKXPort5], 4, [2], 2, 7>;
403 defm : SKXWriteResPair<WritePSADBW, [SKXPort5], 3, [1], 1, 5>; // Vector PSADBW.
404 defm : SKXWriteResPair<WritePSADBWX, [SKXPort5], 3, [1], 1, 6>;
405 defm : SKXWriteResPair<WritePSADBWY, [SKXPort5], 3, [1], 1, 7>;
406 defm : SKXWriteResPair<WritePSADBWZ, [SKXPort5], 3, [1], 1, 7>; // TODO: 512-bit ops require ports 0/1 to be joined.
407 defm : SKXWriteResPair<WritePHMINPOS, [SKXPort0], 4, [1], 1, 6>; // Vector PHMINPOS.
409 // Vector integer shifts.
410 defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1, [1], 1, 5>;
411 defm : X86WriteRes<WriteVecShiftX, [SKXPort5,SKXPort01], 2, [1,1], 2>;
412 defm : X86WriteRes<WriteVecShiftY, [SKXPort5,SKXPort01], 4, [1,1], 2>;
413 defm : X86WriteRes<WriteVecShiftZ, [SKXPort5,SKXPort0], 4, [1,1], 2>;
414 defm : X86WriteRes<WriteVecShiftXLd, [SKXPort01,SKXPort23], 7, [1,1], 2>;
415 defm : X86WriteRes<WriteVecShiftYLd, [SKXPort01,SKXPort23], 8, [1,1], 2>;
416 defm : X86WriteRes<WriteVecShiftZLd, [SKXPort0,SKXPort23], 8, [1,1], 2>;
418 defm : SKXWriteResPair<WriteVecShiftImm, [SKXPort0], 1, [1], 1, 5>;
419 defm : SKXWriteResPair<WriteVecShiftImmX, [SKXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts.
420 defm : SKXWriteResPair<WriteVecShiftImmY, [SKXPort01], 1, [1], 1, 7>;
421 defm : SKXWriteResPair<WriteVecShiftImmZ, [SKXPort0], 1, [1], 1, 7>;
422 defm : SKXWriteResPair<WriteVarVecShift, [SKXPort01], 1, [1], 1, 6>; // Variable vector shifts.
423 defm : SKXWriteResPair<WriteVarVecShiftY, [SKXPort01], 1, [1], 1, 7>;
424 defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>;
426 // Vector insert/extract operations.
427 def : WriteRes<WriteVecInsert, [SKXPort5]> {
428 let Latency = 2;
429 let NumMicroOps = 2;
430 let ReleaseAtCycles = [2];
431 }
432 def : WriteRes<WriteVecInsertLd, [SKXPort5,SKXPort23]> {
433 let Latency = 6;
434 let NumMicroOps = 2;
435 }
436 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
438 def : WriteRes<WriteVecExtract, [SKXPort0,SKXPort5]> {
439 let Latency = 3;
440 let NumMicroOps = 2;
441 }
442 def : WriteRes<WriteVecExtractSt, [SKXPort4,SKXPort5,SKXPort237]> {
443 let Latency = 2;
444 let NumMicroOps = 3;
445 }
447 // Conversion between integer and float.
448 defm : SKXWriteResPair<WriteCvtSS2I, [SKXPort01], 6, [2], 2>; // Needs more work: DD vs DQ.
449 defm : SKXWriteResPair<WriteCvtPS2I, [SKXPort01], 3>;
450 defm : SKXWriteResPair<WriteCvtPS2IY, [SKXPort01], 3>;
451 defm : SKXWriteResPair<WriteCvtPS2IZ, [SKXPort05], 3>;
452 defm : SKXWriteResPair<WriteCvtSD2I, [SKXPort01], 6, [2], 2>;
453 defm : SKXWriteResPair<WriteCvtPD2I, [SKXPort01], 3>;
454 defm : SKXWriteResPair<WriteCvtPD2IY, [SKXPort01], 3>;
455 defm : SKXWriteResPair<WriteCvtPD2IZ, [SKXPort05], 3>;
457 defm : SKXWriteResPair<WriteCvtI2SS, [SKXPort1], 4>;
458 defm : SKXWriteResPair<WriteCvtI2PS, [SKXPort01], 4>;
459 defm : SKXWriteResPair<WriteCvtI2PSY, [SKXPort01], 4>;
460 defm : SKXWriteResPair<WriteCvtI2PSZ, [SKXPort05], 4>; // Needs more work: DD vs DQ.
461 defm : SKXWriteResPair<WriteCvtI2SD, [SKXPort1], 4>;
462 defm : SKXWriteResPair<WriteCvtI2PD, [SKXPort01], 4>;
463 defm : SKXWriteResPair<WriteCvtI2PDY, [SKXPort01], 4>;
464 defm : SKXWriteResPair<WriteCvtI2PDZ, [SKXPort05], 4>;
466 defm : SKXWriteResPair<WriteCvtSS2SD, [SKXPort1], 3>;
467 defm : SKXWriteResPair<WriteCvtPS2PD, [SKXPort1], 3>;
468 defm : SKXWriteResPair<WriteCvtPS2PDY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
469 defm : SKXWriteResPair<WriteCvtPS2PDZ, [SKXPort05], 3, [2], 2>;
470 defm : SKXWriteResPair<WriteCvtSD2SS, [SKXPort5,SKXPort01], 5, [1,1], 2, 5>;
471 defm : SKXWriteResPair<WriteCvtPD2PS, [SKXPort5,SKXPort01], 5, [1,1], 2, 4>;
472 defm : SKXWriteResPair<WriteCvtPD2PSY, [SKXPort5,SKXPort01], 7, [1,1], 2, 7>;
473 defm : SKXWriteResPair<WriteCvtPD2PSZ, [SKXPort5,SKXPort05], 7, [1,1], 2, 7>;
475 defm : X86WriteRes<WriteCvtPH2PS, [SKXPort5,SKXPort01], 5, [1,1], 2>;
476 defm : X86WriteRes<WriteCvtPH2PSY, [SKXPort5,SKXPort01], 7, [1,1], 2>;
477 defm : X86WriteRes<WriteCvtPH2PSZ, [SKXPort5,SKXPort0], 7, [1,1], 2>;
478 defm : X86WriteRes<WriteCvtPH2PSLd, [SKXPort23,SKXPort01], 9, [1,1], 2>;
479 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKXPort23,SKXPort01], 10, [1,1], 2>;
480 defm : X86WriteRes<WriteCvtPH2PSZLd, [SKXPort23,SKXPort05], 10, [1,1], 2>;
482 defm : X86WriteRes<WriteCvtPS2PH, [SKXPort5,SKXPort01], 5, [1,1], 2>;
483 defm : X86WriteRes<WriteCvtPS2PHY, [SKXPort5,SKXPort01], 7, [1,1], 2>;
484 defm : X86WriteRes<WriteCvtPS2PHZ, [SKXPort5,SKXPort05], 7, [1,1], 2>;
485 defm : X86WriteRes<WriteCvtPS2PHSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 6, [1,1,1,1], 4>;
486 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 8, [1,1,1,1], 4>;
487 defm : X86WriteRes<WriteCvtPS2PHZSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort05], 8, [1,1,1,1], 4>;
489 // Strings instructions.
491 // Packed Compare Implicit Length Strings, Return Mask
492 def : WriteRes<WritePCmpIStrM, [SKXPort0]> {
493 let Latency = 10;
494 let NumMicroOps = 3;
495 let ReleaseAtCycles = [3];
496 }
497 def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> {
498 let Latency = 16;
499 let NumMicroOps = 4;
500 let ReleaseAtCycles = [3,1];
501 }
503 // Packed Compare Explicit Length Strings, Return Mask
504 def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> {
505 let Latency = 19;
506 let NumMicroOps = 9;
507 let ReleaseAtCycles = [4,3,1,1];
508 }
509 def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> {
510 let Latency = 25;
511 let NumMicroOps = 10;
512 let ReleaseAtCycles = [4,3,1,1,1];
513 }
515 // Packed Compare Implicit Length Strings, Return Index
516 def : WriteRes<WritePCmpIStrI, [SKXPort0]> {
517 let Latency = 10;
518 let NumMicroOps = 3;
519 let ReleaseAtCycles = [3];
520 }
521 def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> {
522 let Latency = 16;
523 let NumMicroOps = 4;
524 let ReleaseAtCycles = [3,1];
525 }
527 // Packed Compare Explicit Length Strings, Return Index
528 def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> {
529 let Latency = 18;
530 let NumMicroOps = 8;
531 let ReleaseAtCycles = [4,3,1];
532 }
533 def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> {
534 let Latency = 24;
535 let NumMicroOps = 9;
536 let ReleaseAtCycles = [4,3,1,1];
537 }
539 // MOVMSK Instructions.
540 def : WriteRes<WriteFMOVMSK, [SKXPort0]> { let Latency = 2; }
541 def : WriteRes<WriteVecMOVMSK, [SKXPort0]> { let Latency = 2; }
542 def : WriteRes<WriteVecMOVMSKY, [SKXPort0]> { let Latency = 2; }
543 def : WriteRes<WriteMMXMOVMSK, [SKXPort0]> { let Latency = 2; }
545 // AES instructions.
546 def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption.
547 let Latency = 4;
548 let NumMicroOps = 1;
549 let ReleaseAtCycles = [1];
550 }
551 def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> {
552 let Latency = 10;
553 let NumMicroOps = 2;
554 let ReleaseAtCycles = [1,1];
555 }
557 def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn.
558 let Latency = 8;
559 let NumMicroOps = 2;
560 let ReleaseAtCycles = [2];
561 }
562 def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> {
563 let Latency = 14;
564 let NumMicroOps = 3;
565 let ReleaseAtCycles = [2,1];
566 }
568 def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation.
569 let Latency = 20;
570 let NumMicroOps = 11;
571 let ReleaseAtCycles = [3,6,2];
572 }
573 def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
574 let Latency = 25;
575 let NumMicroOps = 11;
576 let ReleaseAtCycles = [3,6,1,1];
577 }
579 // Carry-less multiplication instructions.
580 def : WriteRes<WriteCLMul, [SKXPort5]> {
581 let Latency = 6;
582 let NumMicroOps = 1;
583 let ReleaseAtCycles = [1];
584 }
585 def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> {
586 let Latency = 12;
587 let NumMicroOps = 2;
588 let ReleaseAtCycles = [1,1];
589 }
591 // Catch-all for expensive system instructions.
592 def : WriteRes<WriteSystem, [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
594 // AVX2.
595 defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
596 defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
597 defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles.
598 defm : SKXWriteResPair<WriteVPMOV256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width packed vector width-changing move.
599 defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles.
601 // Old microcoded instructions that nobody use.
602 def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
604 // Fence instructions.
605 def : WriteRes<WriteFence, [SKXPort23, SKXPort4]> { let NumMicroOps = 2; let ReleaseAtCycles = [1,1]; }
607 // Load/store MXCSR.
608 def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
609 def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
611 // Nop, not very useful expect it provides a model for nops!
612 def : WriteRes<WriteNop, []>;
614 ////////////////////////////////////////////////////////////////////////////////
615 // Horizontal add/sub instructions.
616 ////////////////////////////////////////////////////////////////////////////////
618 defm : SKXWriteResPair<WriteFHAdd, [SKXPort5,SKXPort01], 6, [2,1], 3, 6>;
619 defm : SKXWriteResPair<WriteFHAddY, [SKXPort5,SKXPort01], 6, [2,1], 3, 7>;
620 defm : SKXWriteResPair<WritePHAdd, [SKXPort5,SKXPort05], 3, [2,1], 3, 5>;
621 defm : SKXWriteResPair<WritePHAddX, [SKXPort5,SKXPort015], 3, [2,1], 3, 6>;
622 defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>;
624 // Remaining instrs.
626 def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> {
627 let Latency = 1;
628 let NumMicroOps = 1;
629 let ReleaseAtCycles = [1];
630 }
631 def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)kk",
632 "KANDN(B|D|Q|W)kk",
633 "KMOV(B|D|Q|W)kk",
634 "KNOT(B|D|Q|W)kk",
635 "KOR(B|D|Q|W)kk",
636 "KXNOR(B|D|Q|W)kk",
637 "KXOR(B|D|Q|W)kk",
638 "KSET0(B|D|Q|W)", // Same as KXOR
639 "KSET1(B|D|Q|W)", // Same as KXNOR
640 "MMX_PADDS(B|W)rr",
641 "MMX_PADDUS(B|W)rr",
642 "MMX_PAVG(B|W)rr",
643 "MMX_PCMPEQ(B|D|W)rr",
644 "MMX_PCMPGT(B|D|W)rr",
645 "MMX_P(MAX|MIN)SWrr",
646 "MMX_P(MAX|MIN)UBrr",
647 "MMX_PSUBS(B|W)rr",
648 "MMX_PSUBUS(B|W)rr",
649 "VPMOVB2M(Z|Z128|Z256)kr",
650 "VPMOVD2M(Z|Z128|Z256)kr",
651 "VPMOVQ2M(Z|Z128|Z256)kr",
652 "VPMOVW2M(Z|Z128|Z256)kr")>;
654 def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> {
655 let Latency = 1;
656 let NumMicroOps = 1;
657 let ReleaseAtCycles = [1];
658 }
659 def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r",
660 "KMOV(B|D|Q|W)kr",
661 "UCOM_F(P?)r")>;
663 def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
664 let Latency = 1;
665 let NumMicroOps = 1;
666 let ReleaseAtCycles = [1];
667 }
668 def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>;
670 def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> {
671 let Latency = 1;
672 let NumMicroOps = 1;
673 let ReleaseAtCycles = [1];
674 }
675 def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
677 def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
678 let Latency = 1;
679 let NumMicroOps = 1;
680 let ReleaseAtCycles = [1];
681 }
682 def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
684 def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
685 let Latency = 1;
686 let NumMicroOps = 1;
687 let ReleaseAtCycles = [1];
688 }
689 def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr")>;
691 def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
692 let Latency = 1;
693 let NumMicroOps = 1;
694 let ReleaseAtCycles = [1];
695 }
696 def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",
697 "VBLENDMPS(Z128|Z256)rr",
698 "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr",
699 "(V?)PADD(B|D|Q|W)rr",
700 "VPBLENDD(Y?)rri",
701 "VPBLENDMB(Z128|Z256)rr",
702 "VPBLENDMD(Z128|Z256)rr",
703 "VPBLENDMQ(Z128|Z256)rr",
704 "VPBLENDMW(Z128|Z256)rr",
705 "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk",
706 "VPTERNLOGD(Z|Z128|Z256)rri",
707 "VPTERNLOGQ(Z|Z128|Z256)rri")>;
709 def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
710 let Latency = 1;
711 let NumMicroOps = 1;
712 let ReleaseAtCycles = [1];
713 }
714 def: InstRW<[SKXWriteResGroup10], (instrs SGDT64m,
715 SIDT64m,
716 SMSW16m,
717 STRm,
718 SYSCALL)>;
720 def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
721 let Latency = 1;
722 let NumMicroOps = 2;
723 let ReleaseAtCycles = [1,1];
724 }
725 def: InstRW<[SKXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
726 def: InstRW<[SKXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk",
727 "ST_FP(32|64|80)m")>;
729 def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> {
730 let Latency = 2;
731 let NumMicroOps = 2;
732 let ReleaseAtCycles = [2];
733 }
734 def: InstRW<[SKXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
736 def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> {
737 let Latency = 2;
738 let NumMicroOps = 2;
739 let ReleaseAtCycles = [2];
740 }
741 def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP,
742 MMX_MOVDQ2Qrr)>;
744 def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> {
745 let Latency = 2;
746 let NumMicroOps = 2;
747 let ReleaseAtCycles = [2];
748 }
749 def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,
750 WAIT,
751 XGETBV)>;
753 def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
754 let Latency = 2;
755 let NumMicroOps = 2;
756 let ReleaseAtCycles = [1,1];
757 }
758 def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>;
760 def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
761 let Latency = 2;
762 let NumMicroOps = 2;
763 let ReleaseAtCycles = [1,1];
764 }
765 def: InstRW<[SKXWriteResGroup23], (instrs CWD,
766 JCXZ, JECXZ, JRCXZ,
767 ADC8i8, SBB8i8,
768 ADC16i16, SBB16i16,
769 ADC32i32, SBB32i32,
770 ADC64i32, SBB64i32)>;
772 def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> {
773 let Latency = 2;
774 let NumMicroOps = 3;
775 let ReleaseAtCycles = [1,1,1];
776 }
777 def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>;
779 def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
780 let Latency = 2;
781 let NumMicroOps = 3;
782 let ReleaseAtCycles = [1,1,1];
783 }
784 def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
786 def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
787 let Latency = 2;
788 let NumMicroOps = 3;
789 let ReleaseAtCycles = [1,1,1];
790 }
791 def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
792 STOSB, STOSL, STOSQ, STOSW)>;
793 def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
795 def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
796 let Latency = 2;
797 let NumMicroOps = 5;
798 let ReleaseAtCycles = [2,2,1];
799 }
800 def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>;
802 def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> {
803 let Latency = 3;
804 let NumMicroOps = 1;
805 let ReleaseAtCycles = [1];
806 }
807 def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",
808 "KORTEST(B|D|Q|W)kk",
809 "KTEST(B|D|Q|W)kk")>;
811 def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> {
812 let Latency = 3;
813 let NumMicroOps = 1;
814 let ReleaseAtCycles = [1];
815 }
816 def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr",
817 "PEXT(32|64)rr")>;
819 def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> {
820 let Latency = 3;
821 let NumMicroOps = 1;
822 let ReleaseAtCycles = [1];
823 }
824 def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
825 "VALIGND(Z|Z128|Z256)rri",
826 "VALIGNQ(Z|Z128|Z256)rri",
827 "VPBROADCAST(B|W)rr",
828 "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr")>;
830 def SKXWriteResGroup33 : SchedWriteRes<[SKXPort5]> {
831 let Latency = 4;
832 let NumMicroOps = 1;
833 let ReleaseAtCycles = [1];
834 }
835 def: InstRW<[SKXWriteResGroup33], (instregex "KADD(B|D|Q|W)kk",
836 "KSHIFTL(B|D|Q|W)ki",
837 "KSHIFTR(B|D|Q|W)ki",
838 "KUNPCK(BW|DQ|WD)kk",
839 "VCMPPD(Z|Z128|Z256)rri",
840 "VCMPPS(Z|Z128|Z256)rri",
841 "VCMP(SD|SS)Zrr",
842 "VFPCLASS(PD|PS)(Z|Z128|Z256)ri",
843 "VFPCLASS(SD|SS)Zri",
844 "VPCMPB(Z|Z128|Z256)rri",
845 "VPCMPD(Z|Z128|Z256)rri",
846 "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr",
847 "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr",
848 "VPCMPQ(Z|Z128|Z256)rri",
849 "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri",
850 "VPCMPW(Z|Z128|Z256)rri",
851 "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>;
853 def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> {
854 let Latency = 3;
855 let NumMicroOps = 2;
856 let ReleaseAtCycles = [1,1];
857 }
858 def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>;
860 def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> {
861 let Latency = 3;
862 let NumMicroOps = 3;
863 let ReleaseAtCycles = [1,2];
864 }
865 def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>;
867 def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> {
868 let Latency = 3;
869 let NumMicroOps = 3;
870 let ReleaseAtCycles = [2,1];
871 }
872 def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>;
874 def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5]> {
875 let Latency = 2;
876 let NumMicroOps = 2;
877 let ReleaseAtCycles = [2];
878 }
879 def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWrr,
880 MMX_PACKSSWBrr,
881 MMX_PACKUSWBrr)>;
883 def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
884 let Latency = 3;
885 let NumMicroOps = 3;
886 let ReleaseAtCycles = [1,2];
887 }
888 def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>;
890 def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
891 let Latency = 2;
892 let NumMicroOps = 3;
893 let ReleaseAtCycles = [1,2];
894 }
895 def: InstRW<[SKXWriteResGroup44], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
896 RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
898 def SKXWriteResGroup44b : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
899 let Latency = 5;
900 let NumMicroOps = 8;
901 let ReleaseAtCycles = [2,4,2];
902 }
903 def: InstRW<[SKXWriteResGroup44b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
905 def SKXWriteResGroup44c : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
906 let Latency = 6;
907 let NumMicroOps = 8;
908 let ReleaseAtCycles = [2,4,2];
909 }
910 def: InstRW<[SKXWriteResGroup44c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
912 def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {
913 let Latency = 3;
914 let NumMicroOps = 3;
915 let ReleaseAtCycles = [1,1,1];
916 }
917 def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>;
919 def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> {
920 let Latency = 3;
921 let NumMicroOps = 4;
922 let ReleaseAtCycles = [1,1,1,1];
923 }
924 def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>;
926 def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> {
927 let Latency = 3;
928 let NumMicroOps = 4;
929 let ReleaseAtCycles = [1,1,1,1];
930 }
931 def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>;
933 def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> {
934 let Latency = 4;
935 let NumMicroOps = 1;
936 let ReleaseAtCycles = [1];
937 }
938 def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
940 def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> {
941 let Latency = 4;
942 let NumMicroOps = 1;
943 let ReleaseAtCycles = [1];
944 }
945 def: InstRW<[SKXWriteResGroup50], (instregex "VCVTPD2QQ(Z128|Z256)rr",
946 "VCVTPD2UQQ(Z128|Z256)rr",
947 "VCVTPS2DQ(Y|Z128|Z256)rr",
948 "(V?)CVTPS2DQrr",
949 "VCVTPS2UDQ(Z128|Z256)rr",
950 "VCVTTPD2QQ(Z128|Z256)rr",
951 "VCVTTPD2UQQ(Z128|Z256)rr",
952 "VCVTTPS2DQ(Z128|Z256)rr",
953 "(V?)CVTTPS2DQrr",
954 "VCVTTPS2UDQ(Z128|Z256)rr")>;
956 def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> {
957 let Latency = 4;
958 let NumMicroOps = 1;
959 let ReleaseAtCycles = [1];
960 }
961 def: InstRW<[SKXWriteResGroup50z], (instrs VCVTPD2QQZrr,
962 VCVTPD2UQQZrr,
963 VCVTPS2DQZrr,
964 VCVTPS2UDQZrr,
965 VCVTTPD2QQZrr,
966 VCVTTPD2UQQZrr,
967 VCVTTPS2DQZrr,
968 VCVTTPS2UDQZrr)>;
970 def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
971 let Latency = 4;
972 let NumMicroOps = 2;
973 let ReleaseAtCycles = [2];
974 }
975 def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
976 "VEXPANDPS(Z|Z128|Z256)rr",
977 "VPEXPANDD(Z|Z128|Z256)rr",
978 "VPEXPANDQ(Z|Z128|Z256)rr",
979 "VPMOVDB(Z|Z128|Z256)rr",
980 "VPMOVDW(Z|Z128|Z256)rr",
981 "VPMOVQB(Z|Z128|Z256)rr",
982 "VPMOVQW(Z|Z128|Z256)rr",
983 "VPMOVSDB(Z|Z128|Z256)rr",
984 "VPMOVSDW(Z|Z128|Z256)rr",
985 "VPMOVSQB(Z|Z128|Z256)rr",
986 "VPMOVSQD(Z|Z128|Z256)rr",
987 "VPMOVSQW(Z|Z128|Z256)rr",
988 "VPMOVSWB(Z|Z128|Z256)rr",
989 "VPMOVUSDB(Z|Z128|Z256)rr",
990 "VPMOVUSDW(Z|Z128|Z256)rr",
991 "VPMOVUSQB(Z|Z128|Z256)rr",
992 "VPMOVUSQD(Z|Z128|Z256)rr",
993 "VPMOVUSWB(Z|Z128|Z256)rr",
994 "VPMOVWB(Z|Z128|Z256)rr")>;
996 def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
997 let Latency = 4;
998 let NumMicroOps = 3;
999 let ReleaseAtCycles = [1,1,1];
1000 }
1001 def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
1002 "IST_F(16|32)m",
1003 "VPMOVQD(Z|Z128|Z256)mr(b?)")>;
1005 def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> {
1006 let Latency = 4;
1007 let NumMicroOps = 4;
1008 let ReleaseAtCycles = [4];
1009 }
1010 def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>;
1012 def SKXWriteResGroup56 : SchedWriteRes<[]> {
1013 let Latency = 0;
1014 let NumMicroOps = 4;
1015 let ReleaseAtCycles = [];
1016 }
1017 def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>;
1019 def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> {
1020 let Latency = 4;
1021 let NumMicroOps = 4;
1022 let ReleaseAtCycles = [1,1,2];
1023 }
1024 def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1026 def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort01]> {
1027 let Latency = 5;
1028 let NumMicroOps = 2;
1029 let ReleaseAtCycles = [1,1];
1030 }
1031 def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr",
1032 "MMX_CVT(T?)PS2PIrr",
1033 "VCVTDQ2PDZ128rr",
1034 "VCVTPD2DQZ128rr",
1035 "(V?)CVT(T?)PD2DQrr",
1036 "VCVTPD2UDQZ128rr",
1037 "VCVTPS2PDZ128rr",
1038 "(V?)CVTPS2PDrr",
1039 "VCVTPS2QQZ128rr",
1040 "VCVTPS2UQQZ128rr",
1041 "VCVTQQ2PSZ128rr",
1042 "(V?)CVTSI(64)?2SDrr",
1043 "VCVTSI2SSZrr",
1044 "(V?)CVTSI2SSrr",
1045 "VCVTSI(64)?2SDZrr",
1046 "VCVTSS2SDZrr",
1047 "(V?)CVTSS2SDrr",
1048 "VCVTTPD2DQZ128rr",
1049 "VCVTTPD2UDQZ128rr",
1050 "VCVTTPS2QQZ128rr",
1051 "VCVTTPS2UQQZ128rr",
1052 "VCVTUDQ2PDZ128rr",
1053 "VCVTUQQ2PSZ128rr",
1054 "VCVTUSI2SSZrr",
1055 "VCVTUSI(64)?2SDZrr")>;
1057 def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1058 let Latency = 5;
1059 let NumMicroOps = 3;
1060 let ReleaseAtCycles = [2,1];
1061 }
1062 def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>;
1064 def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> {
1065 let Latency = 5;
1066 let NumMicroOps = 3;
1067 let ReleaseAtCycles = [1,1,1];
1068 }
1069 def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>;
1071 def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort01]> {
1072 let Latency = 5;
1073 let NumMicroOps = 3;
1074 let ReleaseAtCycles = [1,1,1];
1075 }
1076 def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",
1077 "VCVTPS2PHZ256mr(b?)",
1078 "VCVTPS2PHZmr(b?)")>;
1080 def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1081 let Latency = 5;
1082 let NumMicroOps = 4;
1083 let ReleaseAtCycles = [1,2,1];
1084 }
1085 def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
1086 "VPMOVDW(Z|Z128|Z256)mr(b?)",
1087 "VPMOVQB(Z|Z128|Z256)mr(b?)",
1088 "VPMOVQW(Z|Z128|Z256)mr(b?)",
1089 "VPMOVSDB(Z|Z128|Z256)mr(b?)",
1090 "VPMOVSDW(Z|Z128|Z256)mr(b?)",
1091 "VPMOVSQB(Z|Z128|Z256)mr(b?)",
1092 "VPMOVSQD(Z|Z128|Z256)mr(b?)",
1093 "VPMOVSQW(Z|Z128|Z256)mr(b?)",
1094 "VPMOVSWB(Z|Z128|Z256)mr(b?)",
1095 "VPMOVUSDB(Z|Z128|Z256)mr(b?)",
1096 "VPMOVUSDW(Z|Z128|Z256)mr(b?)",
1097 "VPMOVUSQB(Z|Z128|Z256)mr(b?)",
1098 "VPMOVUSQD(Z|Z128|Z256)mr(b?)",
1099 "VPMOVUSQW(Z|Z128|Z256)mr(b?)",
1100 "VPMOVUSWB(Z|Z128|Z256)mr(b?)",
1101 "VPMOVWB(Z|Z128|Z256)mr(b?)")>;
1103 def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1104 let Latency = 5;
1105 let NumMicroOps = 5;
1106 let ReleaseAtCycles = [1,4];
1107 }
1108 def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>;
1110 def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
1111 let Latency = 5;
1112 let NumMicroOps = 6;
1113 let ReleaseAtCycles = [1,1,4];
1114 }
1115 def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>;
1117 def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> {
1118 let Latency = 6;
1119 let NumMicroOps = 1;
1120 let ReleaseAtCycles = [1];
1121 }
1122 def: InstRW<[SKXWriteResGroup71], (instrs VBROADCASTSSrm,
1123 VPBROADCASTDrm,
1124 VPBROADCASTQrm)>;
1125 def: InstRW<[SKXWriteResGroup71], (instregex "(V?)MOVSHDUPrm",
1126 "(V?)MOVSLDUPrm",
1127 "(V?)MOVDDUPrm")>;
1129 def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> {
1130 let Latency = 6;
1131 let NumMicroOps = 2;
1132 let ReleaseAtCycles = [2];
1133 }
1134 def: InstRW<[SKXWriteResGroup72], (instrs MMX_CVTPI2PSrr)>;
1135 def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
1136 "VCOMPRESSPS(Z|Z128|Z256)rr",
1137 "VPCOMPRESSD(Z|Z128|Z256)rr",
1138 "VPCOMPRESSQ(Z|Z128|Z256)rr",
1139 "VPERMW(Z|Z128|Z256)rr")>;
1141 def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1142 let Latency = 6;
1143 let NumMicroOps = 2;
1144 let ReleaseAtCycles = [1,1];
1145 }
1146 def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBrm,
1147 MMX_PADDSWrm,
1148 MMX_PADDUSBrm,
1149 MMX_PADDUSWrm,
1150 MMX_PAVGBrm,
1151 MMX_PAVGWrm,
1152 MMX_PCMPEQBrm,
1153 MMX_PCMPEQDrm,
1154 MMX_PCMPEQWrm,
1155 MMX_PCMPGTBrm,
1156 MMX_PCMPGTDrm,
1157 MMX_PCMPGTWrm,
1158 MMX_PMAXSWrm,
1159 MMX_PMAXUBrm,
1160 MMX_PMINSWrm,
1161 MMX_PMINUBrm,
1162 MMX_PSUBSBrm,
1163 MMX_PSUBSWrm,
1164 MMX_PSUBUSBrm,
1165 MMX_PSUBUSWrm)>;
1167 def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {
1168 let Latency = 6;
1169 let NumMicroOps = 2;
1170 let ReleaseAtCycles = [1,1];
1171 }
1172 def: InstRW<[SKXWriteResGroup76], (instrs FARJMP64m)>;
1173 def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>;
1175 def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
1176 let Latency = 6;
1177 let NumMicroOps = 2;
1178 let ReleaseAtCycles = [1,1];
1179 }
1180 def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm",
1181 "MOVBE(16|32|64)rm")>;
1183 def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1184 let Latency = 6;
1185 let NumMicroOps = 2;
1186 let ReleaseAtCycles = [1,1];
1187 }
1188 def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>;
1189 def: InstRW<[SKXWriteResGroup80], (instrs VMOVDI2PDIZrm)>;
1191 def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1192 let Latency = 6;
1193 let NumMicroOps = 2;
1194 let ReleaseAtCycles = [1,1];
1195 }
1196 def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
1197 def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
1199 def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort01]> {
1200 let Latency = 6;
1201 let NumMicroOps = 3;
1202 let ReleaseAtCycles = [2,1];
1203 }
1204 def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",
1205 "VCVTSI642SSZrr",
1206 "VCVTUSI642SSZrr")>;
1208 def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> {
1209 let Latency = 6;
1210 let NumMicroOps = 4;
1211 let ReleaseAtCycles = [1,1,1,1];
1212 }
1213 def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>;
1215 def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1216 let Latency = 6;
1217 let NumMicroOps = 4;
1218 let ReleaseAtCycles = [1,1,1,1];
1219 }
1220 def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)",
1221 "SHL(8|16|32|64)m(1|i)",
1222 "SHR(8|16|32|64)m(1|i)")>;
1224 def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1225 let Latency = 6;
1226 let NumMicroOps = 4;
1227 let ReleaseAtCycles = [1,1,1,1];
1228 }
1229 def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm",
1230 "PUSH(16|32|64)rmm")>;
1232 def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
1233 let Latency = 6;
1234 let NumMicroOps = 6;
1235 let ReleaseAtCycles = [1,5];
1236 }
1237 def: InstRW<[SKXWriteResGroup88], (instrs STD)>;
1239 def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {
1240 let Latency = 7;
1241 let NumMicroOps = 1;
1242 let ReleaseAtCycles = [1];
1243 }
1244 def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
1245 def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128rm,
1246 VBROADCASTI128rm,
1247 VBROADCASTSDYrm,
1248 VBROADCASTSSYrm,
1249 VMOVDDUPYrm,
1250 VMOVSHDUPYrm,
1251 VMOVSLDUPYrm,
1252 VPBROADCASTDYrm,
1253 VPBROADCASTQYrm)>;
1255 def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> {
1256 let Latency = 7;
1257 let NumMicroOps = 2;
1258 let ReleaseAtCycles = [1,1];
1259 }
1260 def: InstRW<[SKXWriteResGroup90], (instrs VCVTDQ2PDYrr)>;
1262 def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1263 let Latency = 7;
1264 let NumMicroOps = 2;
1265 let ReleaseAtCycles = [1,1];
1266 }
1267 def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)",
1268 "VMOVSSZrm(b?)")>;
1270 def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> {
1271 let Latency = 6;
1272 let NumMicroOps = 2;
1273 let ReleaseAtCycles = [1,1];
1274 }
1275 def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm",
1276 "(V?)PMOV(SX|ZX)BQrm",
1277 "(V?)PMOV(SX|ZX)BWrm",
1278 "(V?)PMOV(SX|ZX)DQrm",
1279 "(V?)PMOV(SX|ZX)WDrm",
1280 "(V?)PMOV(SX|ZX)WQrm")>;
1282 def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort01]> {
1283 let Latency = 7;
1284 let NumMicroOps = 2;
1285 let ReleaseAtCycles = [1,1];
1286 }
1287 def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",
1288 "VCVTPD2DQ(Y|Z256)rr",
1289 "VCVTPD2UDQZ256rr",
1290 "VCVTPS2PD(Y|Z256)rr",
1291 "VCVTPS2QQZ256rr",
1292 "VCVTPS2UQQZ256rr",
1293 "VCVTQQ2PSZ256rr",
1294 "VCVTTPD2DQ(Y|Z256)rr",
1295 "VCVTTPD2UDQZ256rr",
1296 "VCVTTPS2QQZ256rr",
1297 "VCVTTPS2UQQZ256rr",
1298 "VCVTUDQ2PDZ256rr",
1299 "VCVTUQQ2PSZ256rr")>;
1301 def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> {
1302 let Latency = 7;
1303 let NumMicroOps = 2;
1304 let ReleaseAtCycles = [1,1];
1305 }
1306 def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr,
1307 VCVTPD2DQZrr,
1308 VCVTPD2UDQZrr,
1309 VCVTPS2PDZrr,
1310 VCVTPS2QQZrr,
1311 VCVTPS2UQQZrr,
1312 VCVTQQ2PSZrr,
1313 VCVTTPD2DQZrr,
1314 VCVTTPD2UDQZrr,
1315 VCVTTPS2QQZrr,
1316 VCVTTPS2UQQZrr,
1317 VCVTUDQ2PDZrr,
1318 VCVTUQQ2PSZrr)>;
1320 def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1321 let Latency = 7;
1322 let NumMicroOps = 2;
1323 let ReleaseAtCycles = [1,1];
1324 }
1325 def: InstRW<[SKXWriteResGroup95], (instrs VPBLENDDrmi)>;
1326 def: InstRW<[SKXWriteResGroup95, ReadAfterVecXLd],
1327 (instregex "VBLENDMPDZ128rm(b?)",
1328 "VBLENDMPSZ128rm(b?)",
1329 "VBROADCASTI32X2Z128rm(b?)",
1330 "VBROADCASTSSZ128rm(b?)",
1331 "VINSERT(F|I)128rmi",
1332 "VMOVAPDZ128rm(b?)",
1333 "VMOVAPSZ128rm(b?)",
1334 "VMOVDDUPZ128rm(b?)",
1335 "VMOVDQA32Z128rm(b?)",
1336 "VMOVDQA64Z128rm(b?)",
1337 "VMOVDQU16Z128rm(b?)",
1338 "VMOVDQU32Z128rm(b?)",
1339 "VMOVDQU64Z128rm(b?)",
1340 "VMOVDQU8Z128rm(b?)",
1341 "VMOVSHDUPZ128rm(b?)",
1342 "VMOVSLDUPZ128rm(b?)",
1343 "VMOVUPDZ128rm(b?)",
1344 "VMOVUPSZ128rm(b?)",
1345 "VPADD(B|D|Q|W)Z128rm(b?)",
1346 "(V?)PADD(B|D|Q|W)rm",
1347 "VPBLENDM(B|D|Q|W)Z128rm(b?)",
1348 "VPBROADCASTDZ128rm(b?)",
1349 "VPBROADCASTQZ128rm(b?)",
1350 "VPSUB(B|D|Q|W)Z128rm(b?)",
1351 "(V?)PSUB(B|D|Q|W)rm",
1352 "VPTERNLOGDZ128rm(b?)i",
1353 "VPTERNLOGQZ128rm(b?)i")>;
1355 def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1356 let Latency = 7;
1357 let NumMicroOps = 3;
1358 let ReleaseAtCycles = [2,1];
1359 }
1360 def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWrm,
1361 MMX_PACKSSWBrm,
1362 MMX_PACKUSWBrm)>;
1364 def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1365 let Latency = 7;
1366 let NumMicroOps = 3;
1367 let ReleaseAtCycles = [2,1];
1368 }
1369 def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2WZ128rr",
1370 "VPERMI2WZ256rr",
1371 "VPERMI2WZrr",
1372 "VPERMT2WZ128rr",
1373 "VPERMT2WZ256rr",
1374 "VPERMT2WZrr")>;
1376 def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1377 let Latency = 7;
1378 let NumMicroOps = 3;
1379 let ReleaseAtCycles = [1,2];
1380 }
1381 def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64,
1382 SCASB, SCASL, SCASQ, SCASW)>;
1384 def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort01]> {
1385 let Latency = 7;
1386 let NumMicroOps = 3;
1387 let ReleaseAtCycles = [1,1,1];
1388 }
1389 def: InstRW<[SKXWriteResGroup100], (instregex "(V?)CVT(T?)SS2SI64(Z?)rr",
1390 "VCVT(T?)SS2USI64Zrr")>;
1392 def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> {
1393 let Latency = 7;
1394 let NumMicroOps = 3;
1395 let ReleaseAtCycles = [1,1,1];
1396 }
1397 def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>;
1399 def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> {
1400 let Latency = 7;
1401 let NumMicroOps = 3;
1402 let ReleaseAtCycles = [1,1,1];
1403 }
1404 def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;
1406 def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> {
1407 let Latency = 7;
1408 let NumMicroOps = 3;
1409 let ReleaseAtCycles = [1,1,1];
1410 }
1411 def: InstRW<[SKXWriteResGroup104], (instrs LRET64, RET64)>;
1413 def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1414 let Latency = 7;
1415 let NumMicroOps = 4;
1416 let ReleaseAtCycles = [1,2,1];
1417 }
1418 def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
1419 "VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
1420 "VPCOMPRESSD(Z|Z128|Z256)mr(b?)",
1421 "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>;
1423 def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1424 let Latency = 7;
1425 let NumMicroOps = 5;
1426 let ReleaseAtCycles = [1,1,1,2];
1427 }
1428 def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
1429 "ROR(8|16|32|64)m(1|i)")>;
1431 def SKXWriteResGroup107_1 : SchedWriteRes<[SKXPort06]> {
1432 let Latency = 2;
1433 let NumMicroOps = 2;
1434 let ReleaseAtCycles = [2];
1435 }
1436 def: InstRW<[SKXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1437 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1439 def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1440 let Latency = 7;
1441 let NumMicroOps = 5;
1442 let ReleaseAtCycles = [1,1,1,2];
1443 }
1444 def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
1446 def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
1447 let Latency = 7;
1448 let NumMicroOps = 5;
1449 let ReleaseAtCycles = [1,1,1,1,1];
1450 }
1451 def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m")>;
1452 def: InstRW<[SKXWriteResGroup109], (instrs FARCALL64m)>;
1454 def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1455 let Latency = 7;
1456 let NumMicroOps = 7;
1457 let ReleaseAtCycles = [1,2,2,2];
1458 }
1459 def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
1460 VPSCATTERQQZ128mr,
1461 VSCATTERDPDZ128mr,
1462 VSCATTERQPDZ128mr)>;
1464 def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> {
1465 let Latency = 7;
1466 let NumMicroOps = 7;
1467 let ReleaseAtCycles = [1,3,1,2];
1468 }
1469 def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>;
1471 def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1472 let Latency = 7;
1473 let NumMicroOps = 11;
1474 let ReleaseAtCycles = [1,4,4,2];
1475 }
1476 def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
1477 VPSCATTERQQZ256mr,
1478 VSCATTERDPDZ256mr,
1479 VSCATTERQPDZ256mr)>;
1481 def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1482 let Latency = 7;
1483 let NumMicroOps = 19;
1484 let ReleaseAtCycles = [1,8,8,2];
1485 }
1486 def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr,
1487 VPSCATTERQDZmr,
1488 VPSCATTERQQZmr,
1489 VSCATTERDPDZmr,
1490 VSCATTERQPSZmr,
1491 VSCATTERQPDZmr)>;
1493 def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1494 let Latency = 7;
1495 let NumMicroOps = 36;
1496 let ReleaseAtCycles = [1,16,1,16,2];
1497 }
1498 def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
1500 def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> {
1501 let Latency = 8;
1502 let NumMicroOps = 2;
1503 let ReleaseAtCycles = [1,1];
1504 }
1505 def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm",
1506 "PEXT(32|64)rm")>;
1508 def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1509 let Latency = 8;
1510 let NumMicroOps = 2;
1511 let ReleaseAtCycles = [1,1];
1512 }
1513 def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",
1514 "VPBROADCASTB(Z|Z256)rm(b?)",
1515 "VPBROADCASTW(Z|Z256)rm(b?)")>;
1516 def: InstRW<[SKXWriteResGroup119], (instrs VPBROADCASTBYrm,
1517 VPBROADCASTWYrm,
1518 VPMOVSXBDYrm,
1519 VPMOVSXBQYrm,
1520 VPMOVSXWQYrm)>;
1522 def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1523 let Latency = 8;
1524 let NumMicroOps = 2;
1525 let ReleaseAtCycles = [1,1];
1526 }
1527 def: InstRW<[SKXWriteResGroup121], (instrs VPBLENDDYrmi)>;
1528 def: InstRW<[SKXWriteResGroup121, ReadAfterVecYLd],
1529 (instregex "VBLENDMPD(Z|Z256)rm(b?)",
1530 "VBLENDMPS(Z|Z256)rm(b?)",
1531 "VBROADCASTF32X2Z256rm(b?)",
1532 "VBROADCASTF32X2Zrm(b?)",
1533 "VBROADCASTF32X4Z256rm(b?)",
1534 "VBROADCASTF32X4Zrm(b?)",
1535 "VBROADCASTF32X8Zrm(b?)",
1536 "VBROADCASTF64X2Z256rm(b?)",
1537 "VBROADCASTF64X2Zrm(b?)",
1538 "VBROADCASTF64X4Zrm(b?)",
1539 "VBROADCASTI32X2Z256rm(b?)",
1540 "VBROADCASTI32X2Zrm(b?)",
1541 "VBROADCASTI32X4Z256rm(b?)",
1542 "VBROADCASTI32X4Zrm(b?)",
1543 "VBROADCASTI32X8Zrm(b?)",
1544 "VBROADCASTI64X2Z256rm(b?)",
1545 "VBROADCASTI64X2Zrm(b?)",
1546 "VBROADCASTI64X4Zrm(b?)",
1547 "VBROADCASTSD(Z|Z256)rm(b?)",
1548 "VBROADCASTSS(Z|Z256)rm(b?)",
1549 "VINSERTF32X4(Z|Z256)rm(b?)",
1550 "VINSERTF32X8Zrm(b?)",
1551 "VINSERTF64X2(Z|Z256)rm(b?)",
1552 "VINSERTF64X4Zrm(b?)",
1553 "VINSERTI32X4(Z|Z256)rm(b?)",
1554 "VINSERTI32X8Zrm(b?)",
1555 "VINSERTI64X2(Z|Z256)rm(b?)",
1556 "VINSERTI64X4Zrm(b?)",
1557 "VMOVAPD(Z|Z256)rm(b?)",
1558 "VMOVAPS(Z|Z256)rm(b?)",
1559 "VMOVDDUP(Z|Z256)rm(b?)",
1560 "VMOVDQA32(Z|Z256)rm(b?)",
1561 "VMOVDQA64(Z|Z256)rm(b?)",
1562 "VMOVDQU16(Z|Z256)rm(b?)",
1563 "VMOVDQU32(Z|Z256)rm(b?)",
1564 "VMOVDQU64(Z|Z256)rm(b?)",
1565 "VMOVDQU8(Z|Z256)rm(b?)",
1566 "VMOVSHDUP(Z|Z256)rm(b?)",
1567 "VMOVSLDUP(Z|Z256)rm(b?)",
1568 "VMOVUPD(Z|Z256)rm(b?)",
1569 "VMOVUPS(Z|Z256)rm(b?)",
1570 "VPADD(B|D|Q|W)Yrm",
1571 "VPADD(B|D|Q|W)(Z|Z256)rm(b?)",
1572 "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)",
1573 "VPBROADCASTD(Z|Z256)rm(b?)",
1574 "VPBROADCASTQ(Z|Z256)rm(b?)",
1575 "VPSUB(B|D|Q|W)Yrm",
1576 "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)",
1577 "VPTERNLOGD(Z|Z256)rm(b?)i",
1578 "VPTERNLOGQ(Z|Z256)rm(b?)i")>;
1580 def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1581 let Latency = 8;
1582 let NumMicroOps = 4;
1583 let ReleaseAtCycles = [1,2,1];
1584 }
1585 def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1587 def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1588 let Latency = 8;
1589 let NumMicroOps = 5;
1590 let ReleaseAtCycles = [1,1,1,2];
1591 }
1592 def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",
1593 "RCR(8|16|32|64)m(1|i)")>;
1595 def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1596 let Latency = 8;
1597 let NumMicroOps = 6;
1598 let ReleaseAtCycles = [1,1,1,3];
1599 }
1600 def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
1601 "ROR(8|16|32|64)mCL",
1602 "SAR(8|16|32|64)mCL",
1603 "SHL(8|16|32|64)mCL",
1604 "SHR(8|16|32|64)mCL")>;
1606 def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1607 let Latency = 8;
1608 let NumMicroOps = 6;
1609 let ReleaseAtCycles = [1,1,1,2,1];
1610 }
1611 def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>;
1613 def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1614 let Latency = 8;
1615 let NumMicroOps = 8;
1616 let ReleaseAtCycles = [1,2,1,2,2];
1617 }
1618 def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
1619 VPSCATTERQDZ256mr,
1620 VSCATTERQPSZ128mr,
1621 VSCATTERQPSZ256mr)>;
1623 def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1624 let Latency = 8;
1625 let NumMicroOps = 12;
1626 let ReleaseAtCycles = [1,4,1,4,2];
1627 }
1628 def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
1629 VSCATTERDPSZ128mr)>;
1631 def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1632 let Latency = 8;
1633 let NumMicroOps = 20;
1634 let ReleaseAtCycles = [1,8,1,8,2];
1635 }
1636 def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
1637 VSCATTERDPSZ256mr)>;
1639 def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1640 let Latency = 8;
1641 let NumMicroOps = 36;
1642 let ReleaseAtCycles = [1,16,1,16,2];
1643 }
1644 def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>;
1646 def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1647 let Latency = 9;
1648 let NumMicroOps = 2;
1649 let ReleaseAtCycles = [1,1];
1650 }
1651 def: InstRW<[SKXWriteResGroup135], (instrs MMX_CVTPI2PSrm)>;
1653 def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1654 let Latency = 9;
1655 let NumMicroOps = 2;
1656 let ReleaseAtCycles = [1,1];
1657 }
1658 def: InstRW<[SKXWriteResGroup136], (instrs VPMOVSXBWYrm,
1659 VPMOVSXDQYrm,
1660 VPMOVSXWDYrm,
1661 VPMOVZXWDYrm)>;
1662 def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
1663 "VFPCLASSSDZm(b?)i",
1664 "VFPCLASSSSZm(b?)i",
1665 "(V?)PCMPGTQrm",
1666 "VPERMI2DZ128rm(b?)",
1667 "VPERMI2PDZ128rm(b?)",
1668 "VPERMI2PSZ128rm(b?)",
1669 "VPERMI2QZ128rm(b?)",
1670 "VPERMT2DZ128rm(b?)",
1671 "VPERMT2PDZ128rm(b?)",
1672 "VPERMT2PSZ128rm(b?)",
1673 "VPERMT2QZ128rm(b?)",
1674 "VPMAXSQZ128rm(b?)",
1675 "VPMAXUQZ128rm(b?)",
1676 "VPMINSQZ128rm(b?)",
1677 "VPMINUQZ128rm(b?)")>;
1679 def SKXWriteResGroup136_2 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1680 let Latency = 10;
1681 let NumMicroOps = 2;
1682 let ReleaseAtCycles = [1,1];
1683 }
1684 def: InstRW<[SKXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i",
1685 "VCMP(SD|SS)Zrm",
1686 "VFPCLASSPDZ128m(b?)i",
1687 "VFPCLASSPSZ128m(b?)i",
1688 "VPCMPBZ128rm(b?)i",
1689 "VPCMPDZ128rm(b?)i",
1690 "VPCMPEQ(B|D|Q|W)Z128rm(b?)",
1691 "VPCMPGT(B|D|Q|W)Z128rm(b?)",
1692 "VPCMPQZ128rm(b?)i",
1693 "VPCMPU(B|D|Q|W)Z128rm(b?)i",
1694 "VPCMPWZ128rm(b?)i",
1695 "VPTESTMBZ128rm(b?)",
1696 "VPTESTMDZ128rm(b?)",
1697 "VPTESTMQZ128rm(b?)",
1698 "VPTESTMWZ128rm(b?)",
1699 "VPTESTNMBZ128rm(b?)",
1700 "VPTESTNMDZ128rm(b?)",
1701 "VPTESTNMQZ128rm(b?)",
1702 "VPTESTNMWZ128rm(b?)")>;
1704 def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort01]> {
1705 let Latency = 9;
1706 let NumMicroOps = 2;
1707 let ReleaseAtCycles = [1,1];
1708 }
1709 def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIrm",
1710 "(V?)CVTPS2PDrm")>;
1712 def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1713 let Latency = 9;
1714 let NumMicroOps = 4;
1715 let ReleaseAtCycles = [2,1,1];
1716 }
1717 def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm",
1718 "(V?)PHSUBSWrm")>;
1720 def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
1721 let Latency = 9;
1722 let NumMicroOps = 5;
1723 let ReleaseAtCycles = [1,2,1,1];
1724 }
1725 def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
1726 "LSL(16|32|64)rm")>;
1728 def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1729 let Latency = 10;
1730 let NumMicroOps = 2;
1731 let ReleaseAtCycles = [1,1];
1732 }
1733 def: InstRW<[SKXWriteResGroup148], (instrs VPCMPGTQYrm)>;
1734 def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1735 "ILD_F(16|32|64)m",
1736 "VALIGND(Z|Z256)rm(b?)i",
1737 "VALIGNQ(Z|Z256)rm(b?)i",
1738 "VPMAXSQ(Z|Z256)rm(b?)",
1739 "VPMAXUQ(Z|Z256)rm(b?)",
1740 "VPMINSQ(Z|Z256)rm(b?)",
1741 "VPMINUQ(Z|Z256)rm(b?)")>;
1743 def SKXWriteResGroup148_2 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1744 let Latency = 11;
1745 let NumMicroOps = 2;
1746 let ReleaseAtCycles = [1,1];
1747 }
1748 def: InstRW<[SKXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i",
1749 "VCMPPS(Z|Z256)rm(b?)i",
1750 "VFPCLASSPD(Z|Z256)m(b?)i",
1751 "VFPCLASSPS(Z|Z256)m(b?)i",
1752 "VPCMPB(Z|Z256)rm(b?)i",
1753 "VPCMPD(Z|Z256)rm(b?)i",
1754 "VPCMPEQB(Z|Z256)rm(b?)",
1755 "VPCMPEQD(Z|Z256)rm(b?)",
1756 "VPCMPEQQ(Z|Z256)rm(b?)",
1757 "VPCMPEQW(Z|Z256)rm(b?)",
1758 "VPCMPGTB(Z|Z256)rm(b?)",
1759 "VPCMPGTD(Z|Z256)rm(b?)",
1760 "VPCMPGTQ(Z|Z256)rm(b?)",
1761 "VPCMPGTW(Z|Z256)rm(b?)",
1762 "VPCMPQ(Z|Z256)rm(b?)i",
1763 "VPCMPU(B|D|Q|W)Z256rm(b?)i",
1764 "VPCMPU(B|D|Q|W)Zrm(b?)i",
1765 "VPCMPW(Z|Z256)rm(b?)i",
1766 "VPTESTM(B|D|Q|W)Z256rm(b?)",
1767 "VPTESTM(B|D|Q|W)Zrm(b?)",
1768 "VPTESTNM(B|D|Q|W)Z256rm(b?)",
1769 "VPTESTNM(B|D|Q|W)Zrm(b?)")>;
1771 def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort01]> {
1772 let Latency = 10;
1773 let NumMicroOps = 2;
1774 let ReleaseAtCycles = [1,1];
1775 }
1776 def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
1777 "VCVTDQ2PSZ128rm(b?)",
1778 "(V?)CVTDQ2PSrm",
1779 "VCVTPD2QQZ128rm(b?)",
1780 "VCVTPD2UQQZ128rm(b?)",
1781 "VCVTPH2PSZ128rm(b?)",
1782 "VCVTPS2DQZ128rm(b?)",
1783 "(V?)CVTPS2DQrm",
1784 "VCVTPS2PDZ128rm(b?)",
1785 "VCVTPS2QQZ128rm(b?)",
1786 "VCVTPS2UDQZ128rm(b?)",
1787 "VCVTPS2UQQZ128rm(b?)",
1788 "VCVTQQ2PDZ128rm(b?)",
1789 "VCVTQQ2PSZ128rm(b?)",
1790 "VCVTSS2SDZrm",
1791 "(V?)CVTSS2SDrm",
1792 "VCVTTPD2QQZ128rm(b?)",
1793 "VCVTTPD2UQQZ128rm(b?)",
1794 "VCVTTPS2DQZ128rm(b?)",
1795 "(V?)CVTTPS2DQrm",
1796 "VCVTTPS2QQZ128rm(b?)",
1797 "VCVTTPS2UDQZ128rm(b?)",
1798 "VCVTTPS2UQQZ128rm(b?)",
1799 "VCVTUDQ2PDZ128rm(b?)",
1800 "VCVTUDQ2PSZ128rm(b?)",
1801 "VCVTUQQ2PDZ128rm(b?)",
1802 "VCVTUQQ2PSZ128rm(b?)")>;
1804 def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1805 let Latency = 10;
1806 let NumMicroOps = 3;
1807 let ReleaseAtCycles = [2,1];
1808 }
1809 def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",
1810 "VEXPANDPSZ128rm(b?)",
1811 "VPEXPANDDZ128rm(b?)",
1812 "VPEXPANDQZ128rm(b?)")>;
1814 def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1815 let Latency = 10;
1816 let NumMicroOps = 4;
1817 let ReleaseAtCycles = [2,1,1];
1818 }
1819 def: InstRW<[SKXWriteResGroup154], (instrs VPHADDSWYrm,
1820 VPHSUBSWYrm)>;
1822 def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1823 let Latency = 10;
1824 let NumMicroOps = 8;
1825 let ReleaseAtCycles = [1,1,1,1,1,3];
1826 }
1827 def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
1829 def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1830 let Latency = 11;
1831 let NumMicroOps = 2;
1832 let ReleaseAtCycles = [1,1];
1833 }
1834 def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>;
1836 def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort01]> {
1837 let Latency = 11;
1838 let NumMicroOps = 2;
1839 let ReleaseAtCycles = [1,1];
1840 }
1841 def: InstRW<[SKXWriteResGroup161], (instrs VCVTDQ2PSYrm,
1842 VCVTPS2PDYrm)>;
1843 def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)",
1844 "VCVTPH2PS(Z|Z256)rm(b?)",
1845 "VCVTPS2PD(Z|Z256)rm(b?)",
1846 "VCVTQQ2PD(Z|Z256)rm(b?)",
1847 "VCVTQQ2PSZ256rm(b?)",
1848 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)",
1849 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)",
1850 "VCVT(T?)PS2DQYrm",
1851 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)",
1852 "VCVT(T?)PS2QQZ256rm(b?)",
1853 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)",
1854 "VCVT(T?)PS2UQQZ256rm(b?)",
1855 "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)",
1856 "VCVTUQQ2PD(Z|Z256)rm(b?)",
1857 "VCVTUQQ2PSZ256rm(b?)")>;
1859 def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1860 let Latency = 11;
1861 let NumMicroOps = 3;
1862 let ReleaseAtCycles = [2,1];
1863 }
1864 def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",
1865 "VEXPANDPD(Z|Z256)rm(b?)",
1866 "VEXPANDPS(Z|Z256)rm(b?)",
1867 "VPEXPANDD(Z|Z256)rm(b?)",
1868 "VPEXPANDQ(Z|Z256)rm(b?)")>;
1870 def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1871 let Latency = 11;
1872 let NumMicroOps = 3;
1873 let ReleaseAtCycles = [1,1,1];
1874 }
1875 def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>;
1877 def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort01]> {
1878 let Latency = 11;
1879 let NumMicroOps = 3;
1880 let ReleaseAtCycles = [1,1,1];
1881 }
1882 def: InstRW<[SKXWriteResGroup166], (instrs CVTPD2DQrm,
1883 CVTTPD2DQrm,
1884 MMX_CVTPD2PIrm,
1885 MMX_CVTTPD2PIrm)>;
1887 def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1888 let Latency = 11;
1889 let NumMicroOps = 4;
1890 let ReleaseAtCycles = [2,1,1];
1891 }
1892 def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>;
1894 def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
1895 let Latency = 11;
1896 let NumMicroOps = 7;
1897 let ReleaseAtCycles = [2,3,2];
1898 }
1899 def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL",
1900 "RCR(16|32|64)rCL")>;
1902 def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
1903 let Latency = 11;
1904 let NumMicroOps = 9;
1905 let ReleaseAtCycles = [1,5,1,2];
1906 }
1907 def: InstRW<[SKXWriteResGroup170], (instrs RCL8rCL)>;
1909 def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1910 let Latency = 11;
1911 let NumMicroOps = 11;
1912 let ReleaseAtCycles = [2,9];
1913 }
1914 def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>;
1916 def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> {
1917 let Latency = 15;
1918 let NumMicroOps = 3;
1919 let ReleaseAtCycles = [3];
1920 }
1921 def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>;
1923 def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> {
1924 let Latency = 15;
1925 let NumMicroOps = 3;
1926 let ReleaseAtCycles = [3];
1927 }
1928 def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>;
1930 def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1931 let Latency = 12;
1932 let NumMicroOps = 3;
1933 let ReleaseAtCycles = [2,1];
1934 }
1935 def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>;
1937 def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort01]> {
1938 let Latency = 12;
1939 let NumMicroOps = 3;
1940 let ReleaseAtCycles = [1,1,1];
1941 }
1942 def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
1943 "VCVT(T?)SS2USI64Zrm(b?)")>;
1945 def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort01]> {
1946 let Latency = 12;
1947 let NumMicroOps = 3;
1948 let ReleaseAtCycles = [1,1,1];
1949 }
1950 def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
1951 "VCVT(T?)PS2UQQZrm(b?)")>;
1953 def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1954 let Latency = 13;
1955 let NumMicroOps = 3;
1956 let ReleaseAtCycles = [2,1];
1957 }
1958 def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
1959 "VPERMWZ256rm(b?)",
1960 "VPERMWZrm(b?)")>;
1962 def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1963 let Latency = 13;
1964 let NumMicroOps = 3;
1965 let ReleaseAtCycles = [1,1,1];
1966 }
1967 def: InstRW<[SKXWriteResGroup181], (instrs VCVTDQ2PDYrm)>;
1969 def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1970 let Latency = 13;
1971 let NumMicroOps = 4;
1972 let ReleaseAtCycles = [2,1,1];
1973 }
1974 def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2WZ128rm(b?)",
1975 "VPERMT2WZ128rm(b?)")>;
1977 def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1978 let Latency = 14;
1979 let NumMicroOps = 3;
1980 let ReleaseAtCycles = [1,1,1];
1981 }
1982 def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>;
1984 def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort01]> {
1985 let Latency = 14;
1986 let NumMicroOps = 3;
1987 let ReleaseAtCycles = [1,1,1];
1988 }
1989 def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",
1990 "VCVTPD2UDQZrm(b?)",
1991 "VCVTQQ2PSZrm(b?)",
1992 "VCVTTPD2DQZrm(b?)",
1993 "VCVTTPD2UDQZrm(b?)",
1994 "VCVTUQQ2PSZrm(b?)")>;
1996 def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1997 let Latency = 14;
1998 let NumMicroOps = 4;
1999 let ReleaseAtCycles = [2,1,1];
2000 }
2001 def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2WZ256rm(b?)",
2002 "VPERMI2WZrm(b?)",
2003 "VPERMT2WZ256rm(b?)",
2004 "VPERMT2WZrm(b?)")>;
2006 def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
2007 let Latency = 14;
2008 let NumMicroOps = 10;
2009 let ReleaseAtCycles = [2,4,1,3];
2010 }
2011 def: InstRW<[SKXWriteResGroup190], (instrs RCR8rCL)>;
2013 def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> {
2014 let Latency = 15;
2015 let NumMicroOps = 1;
2016 let ReleaseAtCycles = [1];
2017 }
2018 def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
2020 def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2021 let Latency = 15;
2022 let NumMicroOps = 8;
2023 let ReleaseAtCycles = [1,2,2,1,2];
2024 }
2025 def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>;
2027 def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2028 let Latency = 15;
2029 let NumMicroOps = 10;
2030 let ReleaseAtCycles = [1,1,1,5,1,1];
2031 }
2032 def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;
2034 def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2035 let Latency = 16;
2036 let NumMicroOps = 14;
2037 let ReleaseAtCycles = [1,1,1,4,2,5];
2038 }
2039 def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>;
2041 def SKXWriteResGroup200 : SchedWriteRes<[SKXPort1, SKXPort05, SKXPort6]> {
2042 let Latency = 12;
2043 let NumMicroOps = 34;
2044 let ReleaseAtCycles = [1, 4, 5];
2045 }
2046 def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>;
2048 def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
2049 let Latency = 17;
2050 let NumMicroOps = 15;
2051 let ReleaseAtCycles = [2,1,2,4,2,4];
2052 }
2053 def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>;
2055 def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort01]> {
2056 let Latency = 21;
2057 let NumMicroOps = 4;
2058 let ReleaseAtCycles = [1,3];
2059 }
2060 def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>;
2062 def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {
2063 let Latency = 18;
2064 let NumMicroOps = 8;
2065 let ReleaseAtCycles = [1,1,1,5];
2066 }
2067 def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>;
2069 def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2070 let Latency = 18;
2071 let NumMicroOps = 11;
2072 let ReleaseAtCycles = [2,1,1,4,1,2];
2073 }
2074 def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
2076 def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort01]> {
2077 let Latency = 22;
2078 let NumMicroOps = 4;
2079 let ReleaseAtCycles = [1,3];
2080 }
2081 def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)")>;
2083 def SKXWriteResGroup211_1 : SchedWriteRes<[SKXPort23,SKXPort05]> {
2084 let Latency = 22;
2085 let NumMicroOps = 4;
2086 let ReleaseAtCycles = [1,3];
2087 }
2088 def: InstRW<[SKXWriteResGroup211_1], (instregex "VPMULLQZrm(b?)")>;
2090 def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> {
2091 let Latency = 20;
2092 let NumMicroOps = 1;
2093 let ReleaseAtCycles = [1];
2094 }
2095 def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
2097 def SKXWriteGatherEVEX2 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2098 let Latency = 17;
2099 let NumMicroOps = 5; // 2 uops perform multiple loads
2100 let ReleaseAtCycles = [1,2,1,1];
2101 }
2102 def: InstRW<[SKXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm,
2103 VGATHERDPDZ128rm, VPGATHERDQZ128rm,
2104 VGATHERQPDZ128rm, VPGATHERQQZ128rm)>;
2106 def SKXWriteGatherEVEX4 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2107 let Latency = 19;
2108 let NumMicroOps = 5; // 2 uops perform multiple loads
2109 let ReleaseAtCycles = [1,4,1,1];
2110 }
2111 def: InstRW<[SKXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm,
2112 VGATHERQPDZ256rm, VPGATHERQQZ256rm,
2113 VGATHERDPSZ128rm, VPGATHERDDZ128rm,
2114 VGATHERDPDZ256rm, VPGATHERDQZ256rm)>;
2116 def SKXWriteGatherEVEX8 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2117 let Latency = 21;
2118 let NumMicroOps = 5; // 2 uops perform multiple loads
2119 let ReleaseAtCycles = [1,8,1,1];
2120 }
2121 def: InstRW<[SKXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm,
2122 VGATHERDPDZrm, VPGATHERDQZrm,
2123 VGATHERQPDZrm, VPGATHERQQZrm,
2124 VGATHERQPSZrm, VPGATHERQDZrm)>;
2126 def SKXWriteGatherEVEX16 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2127 let Latency = 25;
2128 let NumMicroOps = 5; // 2 uops perform multiple loads
2129 let ReleaseAtCycles = [1,16,1,1];
2130 }
2131 def: InstRW<[SKXWriteGatherEVEX16], (instrs VGATHERDPSZrm, VPGATHERDDZrm)>;
2133 def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2134 let Latency = 20;
2135 let NumMicroOps = 8;
2136 let ReleaseAtCycles = [1,1,1,1,1,1,2];
2137 }
2138 def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>;
2140 def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> {
2141 let Latency = 20;
2142 let NumMicroOps = 10;
2143 let ReleaseAtCycles = [1,2,7];
2144 }
2145 def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>;
2147 def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2148 let Latency = 22;
2149 let NumMicroOps = 2;
2150 let ReleaseAtCycles = [1,1];
2151 }
2152 def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>;
2154 def SKXWriteResGroupVEX2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2155 let Latency = 18;
2156 let NumMicroOps = 5; // 2 uops perform multiple loads
2157 let ReleaseAtCycles = [1,2,1,1];
2158 }
2159 def: InstRW<[SKXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
2160 VGATHERQPDrm, VPGATHERQQrm,
2161 VGATHERQPSrm, VPGATHERQDrm)>;
2163 def SKXWriteResGroupVEX4 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2164 let Latency = 20;
2165 let NumMicroOps = 5; // 2 uops peform multiple loads
2166 let ReleaseAtCycles = [1,4,1,1];
2167 }
2168 def: InstRW<[SKXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
2169 VGATHERDPSrm, VPGATHERDDrm,
2170 VGATHERQPDYrm, VPGATHERQQYrm,
2171 VGATHERQPSYrm, VPGATHERQDYrm)>;
2173 def SKXWriteResGroupVEX8 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2174 let Latency = 22;
2175 let NumMicroOps = 5; // 2 uops perform multiple loads
2176 let ReleaseAtCycles = [1,8,1,1];
2177 }
2178 def: InstRW<[SKXWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
2180 def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2181 let Latency = 22;
2182 let NumMicroOps = 14;
2183 let ReleaseAtCycles = [5,5,4];
2184 }
2185 def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
2186 "VPCONFLICTQZ256rr")>;
2188 def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2189 let Latency = 23;
2190 let NumMicroOps = 19;
2191 let ReleaseAtCycles = [2,1,4,1,1,4,6];
2192 }
2193 def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>;
2195 def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2196 let Latency = 25;
2197 let NumMicroOps = 3;
2198 let ReleaseAtCycles = [1,1,1];
2199 }
2200 def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>;
2202 def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2203 let Latency = 27;
2204 let NumMicroOps = 2;
2205 let ReleaseAtCycles = [1,1];
2206 }
2207 def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>;
2209 def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2210 let Latency = 29;
2211 let NumMicroOps = 15;
2212 let ReleaseAtCycles = [5,5,1,4];
2213 }
2214 def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>;
2216 def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2217 let Latency = 30;
2218 let NumMicroOps = 3;
2219 let ReleaseAtCycles = [1,1,1];
2220 }
2221 def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>;
2223 def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> {
2224 let Latency = 35;
2225 let NumMicroOps = 23;
2226 let ReleaseAtCycles = [1,5,3,4,10];
2227 }
2228 def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri",
2229 "IN(8|16|32)rr")>;
2231 def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2232 let Latency = 35;
2233 let NumMicroOps = 23;
2234 let ReleaseAtCycles = [1,5,2,1,4,10];
2235 }
2236 def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir",
2237 "OUT(8|16|32)rr")>;
2239 def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2240 let Latency = 37;
2241 let NumMicroOps = 21;
2242 let ReleaseAtCycles = [9,7,5];
2243 }
2244 def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",
2245 "VPCONFLICTQZrr")>;
2247 def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
2248 let Latency = 37;
2249 let NumMicroOps = 31;
2250 let ReleaseAtCycles = [1,8,1,21];
2251 }
2252 def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>;
2254 def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> {
2255 let Latency = 40;
2256 let NumMicroOps = 18;
2257 let ReleaseAtCycles = [1,1,2,3,1,1,1,8];
2258 }
2259 def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>;
2261 def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2262 let Latency = 41;
2263 let NumMicroOps = 39;
2264 let ReleaseAtCycles = [1,10,1,1,26];
2265 }
2266 def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>;
2268 def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
2269 let Latency = 42;
2270 let NumMicroOps = 22;
2271 let ReleaseAtCycles = [2,20];
2272 }
2273 def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>;
2275 def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2276 let Latency = 42;
2277 let NumMicroOps = 40;
2278 let ReleaseAtCycles = [1,11,1,1,26];
2279 }
2280 def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>;
2281 def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
2283 def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2284 let Latency = 44;
2285 let NumMicroOps = 22;
2286 let ReleaseAtCycles = [9,7,1,5];
2287 }
2288 def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",
2289 "VPCONFLICTQZrm(b?)")>;
2291 def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> {
2292 let Latency = 62;
2293 let NumMicroOps = 64;
2294 let ReleaseAtCycles = [2,8,5,10,39];
2295 }
2296 def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>;
2298 def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2299 let Latency = 63;
2300 let NumMicroOps = 88;
2301 let ReleaseAtCycles = [4,4,31,1,2,1,45];
2302 }
2303 def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>;
2305 def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2306 let Latency = 63;
2307 let NumMicroOps = 90;
2308 let ReleaseAtCycles = [4,2,33,1,2,1,47];
2309 }
2310 def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>;
2312 def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2313 let Latency = 67;
2314 let NumMicroOps = 35;
2315 let ReleaseAtCycles = [17,11,7];
2316 }
2317 def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>;
2319 def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2320 let Latency = 74;
2321 let NumMicroOps = 36;
2322 let ReleaseAtCycles = [17,11,1,7];
2323 }
2324 def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>;
2326 def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> {
2327 let Latency = 75;
2328 let NumMicroOps = 15;
2329 let ReleaseAtCycles = [6,3,6];
2330 }
2331 def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>;
2333 def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> {
2334 let Latency = 106;
2335 let NumMicroOps = 100;
2336 let ReleaseAtCycles = [9,1,11,16,1,11,21,30];
2337 }
2338 def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>;
2340 def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
2341 let Latency = 140;
2342 let NumMicroOps = 4;
2343 let ReleaseAtCycles = [1,3];
2344 }
2345 def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>;
2347 def: InstRW<[WriteZero], (instrs CLC)>;
2350 // Instruction variants handled by the renamer. These might not need execution
2351 // ports in certain conditions.
2352 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
2353 // section "Skylake Pipeline" > "Register allocation and renaming".
2354 // These can be investigated with llvm-exegesis, e.g.
2355 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
2356 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
2358 def SKXWriteZeroLatency : SchedWriteRes<[]> {
2359 let Latency = 0;
2360 }
2362 def SKXWriteZeroIdiom : SchedWriteVariant<[
2363 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2364 SchedVar<NoSchedPred, [WriteALU]>
2365 ]>;
2366 def : InstRW<[SKXWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
2367 XOR32rr, XOR64rr)>;
2369 def SKXWriteFZeroIdiom : SchedWriteVariant<[
2370 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2371 SchedVar<NoSchedPred, [WriteFLogic]>
2372 ]>;
2373 def : InstRW<[SKXWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr,
2374 XORPDrr, VXORPDrr,
2375 VXORPSZ128rr,
2376 VXORPDZ128rr)>;
2378 def SKXWriteFZeroIdiomY : SchedWriteVariant<[
2379 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2380 SchedVar<NoSchedPred, [WriteFLogicY]>
2381 ]>;
2382 def : InstRW<[SKXWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr,
2383 VXORPSZ256rr, VXORPDZ256rr)>;
2385 def SKXWriteFZeroIdiomZ : SchedWriteVariant<[
2386 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2387 SchedVar<NoSchedPred, [WriteFLogicZ]>
2388 ]>;
2389 def : InstRW<[SKXWriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr)>;
2391 def SKXWriteVZeroIdiomLogicX : SchedWriteVariant<[
2392 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2393 SchedVar<NoSchedPred, [WriteVecLogicX]>
2394 ]>;
2395 def : InstRW<[SKXWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr,
2396 VPXORDZ128rr, VPXORQZ128rr)>;
2398 def SKXWriteVZeroIdiomLogicY : SchedWriteVariant<[
2399 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2400 SchedVar<NoSchedPred, [WriteVecLogicY]>
2401 ]>;
2402 def : InstRW<[SKXWriteVZeroIdiomLogicY], (instrs VPXORYrr,
2403 VPXORDZ256rr, VPXORQZ256rr)>;
2405 def SKXWriteVZeroIdiomLogicZ : SchedWriteVariant<[
2406 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2407 SchedVar<NoSchedPred, [WriteVecLogicZ]>
2408 ]>;
2409 def : InstRW<[SKXWriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr)>;
2411 def SKXWriteVZeroIdiomALUX : SchedWriteVariant<[
2412 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2413 SchedVar<NoSchedPred, [WriteVecALUX]>
2414 ]>;
2415 def : InstRW<[SKXWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr,
2416 PCMPGTDrr, VPCMPGTDrr,
2417 PCMPGTWrr, VPCMPGTWrr)>;
2419 def SKXWriteVZeroIdiomALUY : SchedWriteVariant<[
2420 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2421 SchedVar<NoSchedPred, [WriteVecALUY]>
2422 ]>;
2423 def : InstRW<[SKXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
2424 VPCMPGTDYrr,
2425 VPCMPGTWYrr)>;
2427 def SKXWritePSUB : SchedWriteRes<[SKXPort015]> {
2428 let Latency = 1;
2429 let NumMicroOps = 1;
2430 let ReleaseAtCycles = [1];
2431 }
2433 def SKXWriteVZeroIdiomPSUB : SchedWriteVariant<[
2434 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2435 SchedVar<NoSchedPred, [SKXWritePSUB]>
2436 ]>;
2438 def : InstRW<[SKXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr,
2439 PSUBDrr, VPSUBDrr, VPSUBDZ128rr,
2440 PSUBQrr, VPSUBQrr, VPSUBQZ128rr,
2441 PSUBWrr, VPSUBWrr, VPSUBWZ128rr,
2442 VPSUBBYrr, VPSUBBZ256rr,
2443 VPSUBDYrr, VPSUBDZ256rr,
2444 VPSUBQYrr, VPSUBQZ256rr,
2445 VPSUBWYrr, VPSUBWZ256rr,
2446 VPSUBBZrr,
2447 VPSUBDZrr,
2448 VPSUBQZrr,
2449 VPSUBWZrr)>;
2450 def SKXWritePCMPGTQ : SchedWriteRes<[SKXPort5]> {
2451 let Latency = 3;
2452 let NumMicroOps = 1;
2453 let ReleaseAtCycles = [1];
2454 }
2456 def SKXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
2457 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2458 SchedVar<NoSchedPred, [SKXWritePCMPGTQ]>
2459 ]>;
2460 def : InstRW<[SKXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
2461 VPCMPGTQYrr)>;
2464 // CMOVs that use both Z and C flag require an extra uop.
2465 def SKXWriteCMOVA_CMOVBErr : SchedWriteRes<[SKXPort06]> {
2466 let Latency = 2;
2467 let ReleaseAtCycles = [2];
2468 let NumMicroOps = 2;
2469 }
2471 def SKXWriteCMOVA_CMOVBErm : SchedWriteRes<[SKXPort23,SKXPort06]> {
2472 let Latency = 7;
2473 let ReleaseAtCycles = [1,2];
2474 let NumMicroOps = 3;
2475 }
2477 def SKXCMOVA_CMOVBErr : SchedWriteVariant<[
2478 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKXWriteCMOVA_CMOVBErr]>,
2479 SchedVar<NoSchedPred, [WriteCMOV]>
2480 ]>;
2482 def SKXCMOVA_CMOVBErm : SchedWriteVariant<[
2483 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKXWriteCMOVA_CMOVBErm]>,
2484 SchedVar<NoSchedPred, [WriteCMOV.Folded]>
2485 ]>;
2487 def : InstRW<[SKXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
2488 def : InstRW<[SKXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
2490 // SETCCs that use both Z and C flag require an extra uop.
2491 def SKXWriteSETA_SETBEr : SchedWriteRes<[SKXPort06]> {
2492 let Latency = 2;
2493 let ReleaseAtCycles = [2];
2494 let NumMicroOps = 2;
2495 }
2497 def SKXWriteSETA_SETBEm : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {
2498 let Latency = 3;
2499 let ReleaseAtCycles = [1,1,2];
2500 let NumMicroOps = 4;
2501 }
2503 def SKXSETA_SETBErr : SchedWriteVariant<[
2504 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKXWriteSETA_SETBEr]>,
2505 SchedVar<NoSchedPred, [WriteSETCC]>
2506 ]>;
2508 def SKXSETA_SETBErm : SchedWriteVariant<[
2509 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKXWriteSETA_SETBEm]>,
2510 SchedVar<NoSchedPred, [WriteSETCCStore]>
2511 ]>;
2513 def : InstRW<[SKXSETA_SETBErr], (instrs SETCCr)>;
2514 def : InstRW<[SKXSETA_SETBErm], (instrs SETCCm)>;
2516 ///////////////////////////////////////////////////////////////////////////////
2517 // Dependency breaking instructions.
2518 ///////////////////////////////////////////////////////////////////////////////
2520 def : IsZeroIdiomFunction<[
2521 // GPR Zero-idioms.
2522 DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>,
2524 // SSE Zero-idioms.
2525 DepBreakingClass<[
2526 // fp variants.
2527 XORPSrr, XORPDrr,
2529 // int variants.
2530 PXORrr,
2531 PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr,
2532 PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr
2533 ], ZeroIdiomPredicate>,
2535 // AVX Zero-idioms.
2536 DepBreakingClass<[
2537 // xmm fp variants.
2538 VXORPSrr, VXORPDrr,
2540 // xmm int variants.
2541 VPXORrr,
2542 VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,
2543 VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr,
2545 // ymm variants.
2546 VXORPSYrr, VXORPDYrr, VPXORYrr,
2547 VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr,
2548 VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr,
2550 // zmm variants.
2551 VXORPSZrr, VXORPDZrr, VPXORDZrr, VPXORQZrr,
2552 VXORPSZ128rr, VXORPDZ128rr, VPXORDZ128rr, VPXORQZ128rr,
2553 VXORPSZ256rr, VXORPDZ256rr, VPXORDZ256rr, VPXORQZ256rr,
2554 VPSUBBZrr, VPSUBWZrr, VPSUBDZrr, VPSUBQZrr,
2555 VPSUBBZ128rr, VPSUBWZ128rr, VPSUBDZ128rr, VPSUBQZ128rr,
2556 VPSUBBZ256rr, VPSUBWZ256rr, VPSUBDZ256rr, VPSUBQZ256rr,
2557 ], ZeroIdiomPredicate>,
2558 ]>;
2560 } // SchedModel