1 //===- XtensaISelLowering.cpp - Xtensa DAG Lowering Implementation --------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that Xtensa uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #include "XtensaISelLowering.h"
15 #include "XtensaConstantPoolValue.h"
16 #include "XtensaInstrInfo.h"
17 #include "XtensaMachineFunctionInfo.h"
18 #include "XtensaSubtarget.h"
19 #include "XtensaTargetMachine.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Support/raw_ostream.h"
35 #define DEBUG_TYPE "xtensa-lower"
37 // Return true if we must use long (in fact, indirect) function call.
38 // It's simplified version, production implimentation must
39 // resolve a functions in ROM (usually glibc functions)
40 static bool isLongCall(const char *str
) {
41 // Currently always use long calls
45 XtensaTargetLowering::XtensaTargetLowering(const TargetMachine
&TM
,
46 const XtensaSubtarget
&STI
)
47 : TargetLowering(TM
), Subtarget(STI
) {
49 // Set up the register classes.
50 addRegisterClass(MVT::i32
, &Xtensa::ARRegClass
);
52 // Set up special registers.
53 setStackPointerRegisterToSaveRestore(Xtensa::SP
);
55 setSchedulingPreference(Sched::RegPressure
);
57 setMinFunctionAlignment(Align(4));
59 setOperationAction(ISD::Constant
, MVT::i32
, Custom
);
60 setOperationAction(ISD::Constant
, MVT::i64
, Expand
);
62 setBooleanContents(ZeroOrOneBooleanContent
);
64 setOperationAction(ISD::SIGN_EXTEND_INREG
, MVT::i1
, Expand
);
65 setOperationAction(ISD::SIGN_EXTEND_INREG
, MVT::i8
, Expand
);
66 setOperationAction(ISD::SIGN_EXTEND_INREG
, MVT::i16
, Expand
);
68 setOperationAction(ISD::BITCAST
, MVT::i32
, Expand
);
69 setOperationAction(ISD::BITCAST
, MVT::f32
, Expand
);
70 setOperationAction(ISD::UINT_TO_FP
, MVT::i32
, Expand
);
71 setOperationAction(ISD::SINT_TO_FP
, MVT::i32
, Expand
);
72 setOperationAction(ISD::FP_TO_UINT
, MVT::i32
, Expand
);
73 setOperationAction(ISD::FP_TO_SINT
, MVT::i32
, Expand
);
75 // No sign extend instructions for i1 and sign extend load i8
76 for (MVT VT
: MVT::integer_valuetypes()) {
77 setLoadExtAction(ISD::SEXTLOAD
, VT
, MVT::i1
, Promote
);
78 setLoadExtAction(ISD::ZEXTLOAD
, VT
, MVT::i1
, Promote
);
79 setLoadExtAction(ISD::EXTLOAD
, VT
, MVT::i1
, Promote
);
80 setLoadExtAction(ISD::SEXTLOAD
, VT
, MVT::i8
, Expand
);
83 setOperationAction(ISD::ConstantPool
, PtrVT
, Custom
);
84 setOperationAction(ISD::GlobalAddress
, PtrVT
, Custom
);
85 setOperationAction(ISD::BlockAddress
, PtrVT
, Custom
);
86 setOperationAction(ISD::JumpTable
, PtrVT
, Custom
);
88 // Expand jump table branches as address arithmetic followed by an
90 setOperationAction(ISD::BR_JT
, MVT::Other
, Custom
);
92 setOperationAction(ISD::BR_CC
, MVT::i32
, Legal
);
93 setOperationAction(ISD::BR_CC
, MVT::i64
, Expand
);
94 setOperationAction(ISD::BR_CC
, MVT::f32
, Expand
);
96 setOperationAction(ISD::SELECT
, MVT::i32
, Expand
);
97 setOperationAction(ISD::SELECT_CC
, MVT::i32
, Custom
);
98 setOperationAction(ISD::SETCC
, MVT::i32
, Expand
);
100 setCondCodeAction(ISD::SETGT
, MVT::i32
, Expand
);
101 setCondCodeAction(ISD::SETLE
, MVT::i32
, Expand
);
102 setCondCodeAction(ISD::SETUGT
, MVT::i32
, Expand
);
103 setCondCodeAction(ISD::SETULE
, MVT::i32
, Expand
);
105 setOperationAction(ISD::MUL
, MVT::i32
, Expand
);
106 setOperationAction(ISD::MULHU
, MVT::i32
, Expand
);
107 setOperationAction(ISD::MULHS
, MVT::i32
, Expand
);
108 setOperationAction(ISD::SMUL_LOHI
, MVT::i32
, Expand
);
109 setOperationAction(ISD::UMUL_LOHI
, MVT::i32
, Expand
);
111 setOperationAction(ISD::SDIV
, MVT::i32
, Expand
);
112 setOperationAction(ISD::UDIV
, MVT::i32
, Expand
);
113 setOperationAction(ISD::SREM
, MVT::i32
, Expand
);
114 setOperationAction(ISD::UREM
, MVT::i32
, Expand
);
115 setOperationAction(ISD::SDIVREM
, MVT::i32
, Expand
);
116 setOperationAction(ISD::UDIVREM
, MVT::i32
, Expand
);
118 setOperationAction(ISD::SHL_PARTS
, MVT::i32
, Custom
);
119 setOperationAction(ISD::SRA_PARTS
, MVT::i32
, Custom
);
120 setOperationAction(ISD::SRL_PARTS
, MVT::i32
, Custom
);
122 setOperationAction(ISD::BSWAP
, MVT::i32
, Expand
);
123 setOperationAction(ISD::ROTL
, MVT::i32
, Expand
);
124 setOperationAction(ISD::ROTR
, MVT::i32
, Expand
);
125 setOperationAction(ISD::CTPOP
, MVT::i32
, Custom
);
126 setOperationAction(ISD::CTTZ
, MVT::i32
, Expand
);
127 setOperationAction(ISD::CTLZ
, MVT::i32
, Expand
);
128 setOperationAction(ISD::CTTZ_ZERO_UNDEF
, MVT::i32
, Expand
);
129 setOperationAction(ISD::CTLZ_ZERO_UNDEF
, MVT::i32
, Expand
);
131 // Implement custom stack allocations
132 setOperationAction(ISD::DYNAMIC_STACKALLOC
, PtrVT
, Custom
);
133 // Implement custom stack save and restore
134 setOperationAction(ISD::STACKSAVE
, MVT::Other
, Custom
);
135 setOperationAction(ISD::STACKRESTORE
, MVT::Other
, Custom
);
137 // VASTART, VAARG and VACOPY need to deal with the Xtensa-specific varargs
138 // structure, but VAEND is a no-op.
139 setOperationAction(ISD::VASTART
, MVT::Other
, Custom
);
140 setOperationAction(ISD::VAARG
, MVT::Other
, Custom
);
141 setOperationAction(ISD::VACOPY
, MVT::Other
, Custom
);
142 setOperationAction(ISD::VAEND
, MVT::Other
, Expand
);
144 // Compute derived properties from the register classes
145 computeRegisterProperties(STI
.getRegisterInfo());
148 bool XtensaTargetLowering::isOffsetFoldingLegal(
149 const GlobalAddressSDNode
*GA
) const {
150 // The Xtensa target isn't yet aware of offsets.
154 //===----------------------------------------------------------------------===//
155 // Inline asm support
156 //===----------------------------------------------------------------------===//
157 TargetLowering::ConstraintType
158 XtensaTargetLowering::getConstraintType(StringRef Constraint
) const {
159 if (Constraint
.size() == 1) {
160 switch (Constraint
[0]) {
162 return C_RegisterClass
;
167 return TargetLowering::getConstraintType(Constraint
);
170 TargetLowering::ConstraintWeight
171 XtensaTargetLowering::getSingleConstraintMatchWeight(
172 AsmOperandInfo
&Info
, const char *Constraint
) const {
173 ConstraintWeight Weight
= CW_Invalid
;
174 Value
*CallOperandVal
= Info
.CallOperandVal
;
175 // If we don't have a value, we can't do a match,
176 // but allow it at the lowest weight.
180 Type
*Ty
= CallOperandVal
->getType();
182 // Look at the constraint type.
183 switch (*Constraint
) {
185 Weight
= TargetLowering::getSingleConstraintMatchWeight(Info
, Constraint
);
188 if (Ty
->isIntegerTy())
189 Weight
= CW_Register
;
195 std::pair
<unsigned, const TargetRegisterClass
*>
196 XtensaTargetLowering::getRegForInlineAsmConstraint(
197 const TargetRegisterInfo
*TRI
, StringRef Constraint
, MVT VT
) const {
198 if (Constraint
.size() == 1) {
199 // GCC Constraint Letters
200 switch (Constraint
[0]) {
203 case 'r': // General-purpose register
204 return std::make_pair(0U, &Xtensa::ARRegClass
);
207 return TargetLowering::getRegForInlineAsmConstraint(TRI
, Constraint
, VT
);
210 void XtensaTargetLowering::LowerAsmOperandForConstraint(
211 SDValue Op
, StringRef Constraint
, std::vector
<SDValue
> &Ops
,
212 SelectionDAG
&DAG
) const {
215 // Only support length 1 constraints for now.
216 if (Constraint
.size() > 1)
219 TargetLowering::LowerAsmOperandForConstraint(Op
, Constraint
, Ops
, DAG
);
222 //===----------------------------------------------------------------------===//
223 // Calling conventions
224 //===----------------------------------------------------------------------===//
226 #include "XtensaGenCallingConv.inc"
228 static const MCPhysReg IntRegs
[] = {Xtensa::A2
, Xtensa::A3
, Xtensa::A4
,
229 Xtensa::A5
, Xtensa::A6
, Xtensa::A7
};
231 static bool CC_Xtensa_Custom(unsigned ValNo
, MVT ValVT
, MVT LocVT
,
232 CCValAssign::LocInfo LocInfo
,
233 ISD::ArgFlagsTy ArgFlags
, CCState
&State
) {
234 if (ArgFlags
.isByVal()) {
235 Align ByValAlign
= ArgFlags
.getNonZeroByValAlign();
236 unsigned ByValSize
= ArgFlags
.getByValSize();
240 if (ByValAlign
< Align(4)) {
241 ByValAlign
= Align(4);
243 unsigned Offset
= State
.AllocateStack(ByValSize
, ByValAlign
);
244 State
.addLoc(CCValAssign::getMem(ValNo
, ValVT
, Offset
, LocVT
, LocInfo
));
245 // Mark all unused registers as allocated to avoid misuse
246 // of such registers.
247 while (State
.AllocateReg(IntRegs
))
252 // Promote i8 and i16
253 if (LocVT
== MVT::i8
|| LocVT
== MVT::i16
) {
255 if (ArgFlags
.isSExt())
256 LocInfo
= CCValAssign::SExt
;
257 else if (ArgFlags
.isZExt())
258 LocInfo
= CCValAssign::ZExt
;
260 LocInfo
= CCValAssign::AExt
;
265 Align OrigAlign
= ArgFlags
.getNonZeroOrigAlign();
266 bool needs64BitAlign
= (ValVT
== MVT::i32
&& OrigAlign
== Align(8));
267 bool needs128BitAlign
= (ValVT
== MVT::i32
&& OrigAlign
== Align(16));
269 if (ValVT
== MVT::i32
) {
270 Register
= State
.AllocateReg(IntRegs
);
271 // If this is the first part of an i64 arg,
272 // the allocated register must be either A2, A4 or A6.
273 if (needs64BitAlign
&& (Register
== Xtensa::A3
|| Register
== Xtensa::A5
||
274 Register
== Xtensa::A7
))
275 Register
= State
.AllocateReg(IntRegs
);
276 // arguments with 16byte alignment must be passed in the first register or
278 if (needs128BitAlign
&& (Register
!= Xtensa::A2
))
279 while ((Register
= State
.AllocateReg(IntRegs
)))
282 } else if (ValVT
== MVT::f64
) {
283 // Allocate int register and shadow next int register.
284 Register
= State
.AllocateReg(IntRegs
);
285 if (Register
== Xtensa::A3
|| Register
== Xtensa::A5
||
286 Register
== Xtensa::A7
)
287 Register
= State
.AllocateReg(IntRegs
);
288 State
.AllocateReg(IntRegs
);
291 report_fatal_error("Cannot handle this ValVT.");
295 unsigned Offset
= State
.AllocateStack(ValVT
.getStoreSize(), OrigAlign
);
296 State
.addLoc(CCValAssign::getMem(ValNo
, ValVT
, Offset
, LocVT
, LocInfo
));
298 State
.addLoc(CCValAssign::getReg(ValNo
, ValVT
, Register
, LocVT
, LocInfo
));
304 CCAssignFn
*XtensaTargetLowering::CCAssignFnForCall(CallingConv::ID CC
,
305 bool IsVarArg
) const {
306 return CC_Xtensa_Custom
;
309 SDValue
XtensaTargetLowering::LowerFormalArguments(
310 SDValue Chain
, CallingConv::ID CallConv
, bool IsVarArg
,
311 const SmallVectorImpl
<ISD::InputArg
> &Ins
, const SDLoc
&DL
,
312 SelectionDAG
&DAG
, SmallVectorImpl
<SDValue
> &InVals
) const {
313 MachineFunction
&MF
= DAG
.getMachineFunction();
314 MachineFrameInfo
&MFI
= MF
.getFrameInfo();
315 XtensaMachineFunctionInfo
*XtensaFI
= MF
.getInfo
<XtensaMachineFunctionInfo
>();
317 // Used with vargs to acumulate store chains.
318 std::vector
<SDValue
> OutChains
;
320 // Assign locations to all of the incoming arguments.
321 SmallVector
<CCValAssign
, 16> ArgLocs
;
322 CCState
CCInfo(CallConv
, IsVarArg
, DAG
.getMachineFunction(), ArgLocs
,
325 CCInfo
.AnalyzeFormalArguments(Ins
, CCAssignFnForCall(CallConv
, IsVarArg
));
327 for (unsigned i
= 0, e
= ArgLocs
.size(); i
!= e
; ++i
) {
328 CCValAssign
&VA
= ArgLocs
[i
];
329 // Arguments stored on registers
331 EVT RegVT
= VA
.getLocVT();
333 if (RegVT
!= MVT::i32
)
334 report_fatal_error("RegVT not supported by FormalArguments Lowering");
336 // Transform the arguments stored on
337 // physical registers into virtual ones
338 Register Reg
= MF
.addLiveIn(VA
.getLocReg(), &Xtensa::ARRegClass
);
339 SDValue ArgValue
= DAG
.getCopyFromReg(Chain
, DL
, Reg
, RegVT
);
341 // If this is an 8 or 16-bit value, it has been passed promoted
342 // to 32 bits. Insert an assert[sz]ext to capture this, then
343 // truncate to the right size.
344 if (VA
.getLocInfo() != CCValAssign::Full
) {
346 if (VA
.getLocInfo() == CCValAssign::SExt
)
347 Opcode
= ISD::AssertSext
;
348 else if (VA
.getLocInfo() == CCValAssign::ZExt
)
349 Opcode
= ISD::AssertZext
;
351 ArgValue
= DAG
.getNode(Opcode
, DL
, RegVT
, ArgValue
,
352 DAG
.getValueType(VA
.getValVT()));
353 ArgValue
= DAG
.getNode((VA
.getValVT() == MVT::f32
) ? ISD::BITCAST
355 DL
, VA
.getValVT(), ArgValue
);
358 InVals
.push_back(ArgValue
);
361 assert(VA
.isMemLoc());
363 EVT ValVT
= VA
.getValVT();
365 // The stack pointer offset is relative to the caller stack frame.
366 int FI
= MFI
.CreateFixedObject(ValVT
.getStoreSize(), VA
.getLocMemOffset(),
369 if (Ins
[VA
.getValNo()].Flags
.isByVal()) {
370 // Assume that in this case load operation is created
371 SDValue FIN
= DAG
.getFrameIndex(FI
, MVT::i32
);
372 InVals
.push_back(FIN
);
374 // Create load nodes to retrieve arguments from the stack
376 DAG
.getFrameIndex(FI
, getFrameIndexTy(DAG
.getDataLayout()));
377 InVals
.push_back(DAG
.getLoad(
378 ValVT
, DL
, Chain
, FIN
,
379 MachinePointerInfo::getFixedStack(DAG
.getMachineFunction(), FI
)));
385 unsigned Idx
= CCInfo
.getFirstUnallocated(IntRegs
);
386 unsigned ArgRegsNum
= std::size(IntRegs
);
387 const TargetRegisterClass
*RC
= &Xtensa::ARRegClass
;
388 MachineFrameInfo
&MFI
= MF
.getFrameInfo();
389 MachineRegisterInfo
&RegInfo
= MF
.getRegInfo();
390 unsigned RegSize
= 4;
391 MVT RegTy
= MVT::i32
;
392 MVT FITy
= getFrameIndexTy(DAG
.getDataLayout());
394 XtensaFI
->setVarArgsFirstGPR(Idx
+ 2); // 2 - number of a2 register
396 XtensaFI
->setVarArgsOnStackFrameIndex(
397 MFI
.CreateFixedObject(4, CCInfo
.getStackSize(), true));
399 // Offset of the first variable argument from stack pointer, and size of
400 // the vararg save area. For now, the varargs save area is either zero or
401 // large enough to hold a0-a7.
402 int VaArgOffset
, VarArgsSaveSize
;
404 // If all registers are allocated, then all varargs must be passed on the
405 // stack and we don't need to save any argregs.
406 if (ArgRegsNum
== Idx
) {
407 VaArgOffset
= CCInfo
.getStackSize();
410 VarArgsSaveSize
= RegSize
* (ArgRegsNum
- Idx
);
411 VaArgOffset
= -VarArgsSaveSize
;
413 // Record the frame index of the first variable argument
414 // which is a value necessary to VASTART.
415 int FI
= MFI
.CreateFixedObject(RegSize
, VaArgOffset
, true);
416 XtensaFI
->setVarArgsInRegsFrameIndex(FI
);
418 // Copy the integer registers that may have been used for passing varargs
419 // to the vararg save area.
420 for (unsigned I
= Idx
; I
< ArgRegsNum
; ++I
, VaArgOffset
+= RegSize
) {
421 const Register Reg
= RegInfo
.createVirtualRegister(RC
);
422 RegInfo
.addLiveIn(IntRegs
[I
], Reg
);
424 SDValue ArgValue
= DAG
.getCopyFromReg(Chain
, DL
, Reg
, RegTy
);
425 FI
= MFI
.CreateFixedObject(RegSize
, VaArgOffset
, true);
426 SDValue PtrOff
= DAG
.getFrameIndex(FI
, FITy
);
427 SDValue Store
= DAG
.getStore(Chain
, DL
, ArgValue
, PtrOff
,
428 MachinePointerInfo::getFixedStack(MF
, FI
));
429 OutChains
.push_back(Store
);
434 // All stores are grouped in one node to allow the matching between
435 // the size of Ins and InVals. This only happens when on varg functions
436 if (!OutChains
.empty()) {
437 OutChains
.push_back(Chain
);
438 Chain
= DAG
.getNode(ISD::TokenFactor
, DL
, MVT::Other
, OutChains
);
445 XtensaTargetLowering::LowerCall(CallLoweringInfo
&CLI
,
446 SmallVectorImpl
<SDValue
> &InVals
) const {
447 SelectionDAG
&DAG
= CLI
.DAG
;
449 SmallVector
<ISD::OutputArg
, 32> &Outs
= CLI
.Outs
;
450 SmallVector
<SDValue
, 32> &OutVals
= CLI
.OutVals
;
451 SmallVector
<ISD::InputArg
, 32> &Ins
= CLI
.Ins
;
452 SDValue Chain
= CLI
.Chain
;
453 SDValue Callee
= CLI
.Callee
;
454 bool &IsTailCall
= CLI
.IsTailCall
;
455 CallingConv::ID CallConv
= CLI
.CallConv
;
456 bool IsVarArg
= CLI
.IsVarArg
;
458 MachineFunction
&MF
= DAG
.getMachineFunction();
459 EVT PtrVT
= getPointerTy(DAG
.getDataLayout());
460 const TargetFrameLowering
*TFL
= Subtarget
.getFrameLowering();
462 // TODO: Support tail call optimization.
465 // Analyze the operands of the call, assigning locations to each operand.
466 SmallVector
<CCValAssign
, 16> ArgLocs
;
467 CCState
CCInfo(CallConv
, IsVarArg
, MF
, ArgLocs
, *DAG
.getContext());
469 CCAssignFn
*CC
= CCAssignFnForCall(CallConv
, IsVarArg
);
471 CCInfo
.AnalyzeCallOperands(Outs
, CC
);
473 // Get a count of how many bytes are to be pushed on the stack.
474 unsigned NumBytes
= CCInfo
.getStackSize();
476 Align StackAlignment
= TFL
->getStackAlign();
477 unsigned NextStackOffset
= alignTo(NumBytes
, StackAlignment
);
479 Chain
= DAG
.getCALLSEQ_START(Chain
, NextStackOffset
, 0, DL
);
481 // Copy argument values to their designated locations.
482 std::deque
<std::pair
<unsigned, SDValue
>> RegsToPass
;
483 SmallVector
<SDValue
, 8> MemOpChains
;
485 for (unsigned I
= 0, E
= ArgLocs
.size(); I
!= E
; ++I
) {
486 CCValAssign
&VA
= ArgLocs
[I
];
487 SDValue ArgValue
= OutVals
[I
];
488 ISD::ArgFlagsTy Flags
= Outs
[I
].Flags
;
491 // Queue up the argument copies and emit them at the end.
492 RegsToPass
.push_back(std::make_pair(VA
.getLocReg(), ArgValue
));
493 else if (Flags
.isByVal()) {
494 assert(VA
.isMemLoc());
495 assert(Flags
.getByValSize() &&
496 "ByVal args of size 0 should have been ignored by front-end.");
497 assert(!IsTailCall
&&
498 "Do not tail-call optimize if there is a byval argument.");
500 if (!StackPtr
.getNode())
501 StackPtr
= DAG
.getCopyFromReg(Chain
, DL
, Xtensa::SP
, PtrVT
);
502 unsigned Offset
= VA
.getLocMemOffset();
503 SDValue Address
= DAG
.getNode(ISD::ADD
, DL
, PtrVT
, StackPtr
,
504 DAG
.getIntPtrConstant(Offset
, DL
));
505 SDValue SizeNode
= DAG
.getConstant(Flags
.getByValSize(), DL
, MVT::i32
);
506 SDValue Memcpy
= DAG
.getMemcpy(
507 Chain
, DL
, Address
, ArgValue
, SizeNode
, Flags
.getNonZeroByValAlign(),
508 /*isVolatile=*/false, /*AlwaysInline=*/false,
509 /*CI=*/nullptr, std::nullopt
, MachinePointerInfo(),
510 MachinePointerInfo());
511 MemOpChains
.push_back(Memcpy
);
513 assert(VA
.isMemLoc() && "Argument not register or memory");
515 // Work out the address of the stack slot. Unpromoted ints and
516 // floats are passed as right-justified 8-byte values.
517 if (!StackPtr
.getNode())
518 StackPtr
= DAG
.getCopyFromReg(Chain
, DL
, Xtensa::SP
, PtrVT
);
519 unsigned Offset
= VA
.getLocMemOffset();
520 SDValue Address
= DAG
.getNode(ISD::ADD
, DL
, PtrVT
, StackPtr
,
521 DAG
.getIntPtrConstant(Offset
, DL
));
524 MemOpChains
.push_back(
525 DAG
.getStore(Chain
, DL
, ArgValue
, Address
, MachinePointerInfo()));
529 // Join the stores, which are independent of one another.
530 if (!MemOpChains
.empty())
531 Chain
= DAG
.getNode(ISD::TokenFactor
, DL
, MVT::Other
, MemOpChains
);
533 // Build a sequence of copy-to-reg nodes, chained and glued together.
535 for (unsigned I
= 0, E
= RegsToPass
.size(); I
!= E
; ++I
) {
536 unsigned Reg
= RegsToPass
[I
].first
;
537 Chain
= DAG
.getCopyToReg(Chain
, DL
, Reg
, RegsToPass
[I
].second
, Glue
);
538 Glue
= Chain
.getValue(1);
541 unsigned char TF
= 0;
543 // Accept direct calls by converting symbolic call addresses to the
544 // associated Target* opcodes.
545 if (ExternalSymbolSDNode
*E
= dyn_cast
<ExternalSymbolSDNode
>(Callee
)) {
546 name
= E
->getSymbol();
547 TF
= E
->getTargetFlags();
548 if (isPositionIndependent()) {
549 report_fatal_error("PIC relocations is not supported");
551 Callee
= DAG
.getTargetExternalSymbol(E
->getSymbol(), PtrVT
, TF
);
552 } else if (GlobalAddressSDNode
*G
= dyn_cast
<GlobalAddressSDNode
>(Callee
)) {
553 const GlobalValue
*GV
= G
->getGlobal();
554 name
= GV
->getName().str();
557 if ((!name
.empty()) && isLongCall(name
.c_str())) {
558 // Create a constant pool entry for the callee address
559 XtensaCP::XtensaCPModifier Modifier
= XtensaCP::no_modifier
;
561 XtensaConstantPoolValue
*CPV
= XtensaConstantPoolSymbol::Create(
562 *DAG
.getContext(), name
.c_str(), 0 /* XtensaCLabelIndex */, false,
565 // Get the address of the callee into a register
566 SDValue CPAddr
= DAG
.getTargetConstantPool(CPV
, PtrVT
, Align(4), 0, TF
);
567 SDValue CPWrap
= getAddrPCRel(CPAddr
, DAG
);
571 // The first call operand is the chain and the second is the target address.
572 SmallVector
<SDValue
, 8> Ops
;
573 Ops
.push_back(Chain
);
574 Ops
.push_back(Callee
);
576 // Add a register mask operand representing the call-preserved registers.
577 const TargetRegisterInfo
*TRI
= Subtarget
.getRegisterInfo();
578 const uint32_t *Mask
= TRI
->getCallPreservedMask(MF
, CallConv
);
579 assert(Mask
&& "Missing call preserved mask for calling convention");
580 Ops
.push_back(DAG
.getRegisterMask(Mask
));
582 // Add argument registers to the end of the list so that they are
583 // known live into the call.
584 for (unsigned I
= 0, E
= RegsToPass
.size(); I
!= E
; ++I
) {
585 unsigned Reg
= RegsToPass
[I
].first
;
586 Ops
.push_back(DAG
.getRegister(Reg
, RegsToPass
[I
].second
.getValueType()));
589 // Glue the call to the argument copies, if any.
593 SDVTList NodeTys
= DAG
.getVTList(MVT::Other
, MVT::Glue
);
594 Chain
= DAG
.getNode(XtensaISD::CALL
, DL
, NodeTys
, Ops
);
595 Glue
= Chain
.getValue(1);
597 // Mark the end of the call, which is glued to the call itself.
598 Chain
= DAG
.getCALLSEQ_END(Chain
, DAG
.getConstant(NumBytes
, DL
, PtrVT
, true),
599 DAG
.getConstant(0, DL
, PtrVT
, true), Glue
, DL
);
600 Glue
= Chain
.getValue(1);
602 // Assign locations to each value returned by this call.
603 SmallVector
<CCValAssign
, 16> RetLocs
;
604 CCState
RetCCInfo(CallConv
, IsVarArg
, MF
, RetLocs
, *DAG
.getContext());
605 RetCCInfo
.AnalyzeCallResult(Ins
, RetCC_Xtensa
);
607 // Copy all of the result registers out of their specified physreg.
608 for (unsigned I
= 0, E
= RetLocs
.size(); I
!= E
; ++I
) {
609 CCValAssign
&VA
= RetLocs
[I
];
611 // Copy the value out, gluing the copy to the end of the call sequence.
612 unsigned Reg
= VA
.getLocReg();
613 SDValue RetValue
= DAG
.getCopyFromReg(Chain
, DL
, Reg
, VA
.getLocVT(), Glue
);
614 Chain
= RetValue
.getValue(1);
615 Glue
= RetValue
.getValue(2);
617 InVals
.push_back(RetValue
);
622 bool XtensaTargetLowering::CanLowerReturn(
623 CallingConv::ID CallConv
, MachineFunction
&MF
, bool IsVarArg
,
624 const SmallVectorImpl
<ISD::OutputArg
> &Outs
, LLVMContext
&Context
,
625 const Type
*RetTy
) const {
626 SmallVector
<CCValAssign
, 16> RVLocs
;
627 CCState
CCInfo(CallConv
, IsVarArg
, MF
, RVLocs
, Context
);
628 return CCInfo
.CheckReturn(Outs
, RetCC_Xtensa
);
632 XtensaTargetLowering::LowerReturn(SDValue Chain
, CallingConv::ID CallConv
,
634 const SmallVectorImpl
<ISD::OutputArg
> &Outs
,
635 const SmallVectorImpl
<SDValue
> &OutVals
,
636 const SDLoc
&DL
, SelectionDAG
&DAG
) const {
637 MachineFunction
&MF
= DAG
.getMachineFunction();
639 // Assign locations to each returned value.
640 SmallVector
<CCValAssign
, 16> RetLocs
;
641 CCState
RetCCInfo(CallConv
, IsVarArg
, MF
, RetLocs
, *DAG
.getContext());
642 RetCCInfo
.AnalyzeReturn(Outs
, RetCC_Xtensa
);
645 // Quick exit for void returns
647 return DAG
.getNode(XtensaISD::RET
, DL
, MVT::Other
, Chain
);
649 // Copy the result values into the output registers.
650 SmallVector
<SDValue
, 4> RetOps
;
651 RetOps
.push_back(Chain
);
652 for (unsigned I
= 0, E
= RetLocs
.size(); I
!= E
; ++I
) {
653 CCValAssign
&VA
= RetLocs
[I
];
654 SDValue RetValue
= OutVals
[I
];
656 // Make the return register live on exit.
657 assert(VA
.isRegLoc() && "Can only return in registers!");
659 // Chain and glue the copies together.
660 unsigned Register
= VA
.getLocReg();
661 Chain
= DAG
.getCopyToReg(Chain
, DL
, Register
, RetValue
, Glue
);
662 Glue
= Chain
.getValue(1);
663 RetOps
.push_back(DAG
.getRegister(Register
, VA
.getLocVT()));
666 // Update chain and glue.
669 RetOps
.push_back(Glue
);
671 return DAG
.getNode(XtensaISD::RET
, DL
, MVT::Other
, RetOps
);
674 static unsigned getBranchOpcode(ISD::CondCode Cond
) {
697 llvm_unreachable("Unknown branch kind");
701 SDValue
XtensaTargetLowering::LowerSELECT_CC(SDValue Op
,
702 SelectionDAG
&DAG
) const {
704 EVT Ty
= Op
.getOperand(0).getValueType();
705 SDValue LHS
= Op
.getOperand(0);
706 SDValue RHS
= Op
.getOperand(1);
707 SDValue TrueValue
= Op
.getOperand(2);
708 SDValue FalseValue
= Op
.getOperand(3);
709 ISD::CondCode CC
= cast
<CondCodeSDNode
>(Op
->getOperand(4))->get();
711 unsigned BrOpcode
= getBranchOpcode(CC
);
712 SDValue TargetCC
= DAG
.getConstant(BrOpcode
, DL
, MVT::i32
);
714 return DAG
.getNode(XtensaISD::SELECT_CC
, DL
, Ty
, LHS
, RHS
, TrueValue
,
715 FalseValue
, TargetCC
);
718 SDValue
XtensaTargetLowering::LowerRETURNADDR(SDValue Op
,
719 SelectionDAG
&DAG
) const {
720 // This nodes represent llvm.returnaddress on the DAG.
721 // It takes one operand, the index of the return address to return.
722 // An index of zero corresponds to the current function's return address.
723 // An index of one to the parent's return address, and so on.
724 // Depths > 0 not supported yet!
725 if (Op
.getConstantOperandVal(0) != 0)
728 MachineFunction
&MF
= DAG
.getMachineFunction();
729 MachineFrameInfo
&MFI
= MF
.getFrameInfo();
730 EVT VT
= Op
.getValueType();
731 MFI
.setReturnAddressIsTaken(true);
733 // Return RA, which contains the return address. Mark it an implicit
735 Register RA
= MF
.addLiveIn(Xtensa::A0
, getRegClassFor(MVT::i32
));
736 return DAG
.getCopyFromReg(DAG
.getEntryNode(), SDLoc(Op
), RA
, VT
);
739 SDValue
XtensaTargetLowering::LowerImmediate(SDValue Op
,
740 SelectionDAG
&DAG
) const {
741 const ConstantSDNode
*CN
= cast
<ConstantSDNode
>(Op
);
743 APInt APVal
= CN
->getAPIntValue();
744 int64_t Value
= APVal
.getSExtValue();
745 if (Op
.getValueType() == MVT::i32
) {
746 // Check if use node maybe lowered to the MOVI instruction
747 if (Value
> -2048 && Value
<= 2047)
749 // Check if use node maybe lowered to the ADDMI instruction
750 SDNode
&OpNode
= *Op
.getNode();
751 if ((OpNode
.hasOneUse() && OpNode
.user_begin()->getOpcode() == ISD::ADD
) &&
752 isShiftedInt
<16, 8>(Value
))
754 Type
*Ty
= Type::getInt32Ty(*DAG
.getContext());
755 Constant
*CV
= ConstantInt::get(Ty
, Value
);
756 SDValue CP
= DAG
.getConstantPool(CV
, MVT::i32
);
762 SDValue
XtensaTargetLowering::LowerGlobalAddress(SDValue Op
,
763 SelectionDAG
&DAG
) const {
764 const GlobalAddressSDNode
*G
= cast
<GlobalAddressSDNode
>(Op
);
766 auto PtrVT
= Op
.getValueType();
767 const GlobalValue
*GV
= G
->getGlobal();
769 SDValue CPAddr
= DAG
.getTargetConstantPool(GV
, PtrVT
, Align(4));
770 SDValue CPWrap
= getAddrPCRel(CPAddr
, DAG
);
775 SDValue
XtensaTargetLowering::LowerBlockAddress(SDValue Op
,
776 SelectionDAG
&DAG
) const {
777 BlockAddressSDNode
*Node
= cast
<BlockAddressSDNode
>(Op
);
778 const BlockAddress
*BA
= Node
->getBlockAddress();
779 EVT PtrVT
= Op
.getValueType();
781 XtensaConstantPoolValue
*CPV
=
782 XtensaConstantPoolConstant::Create(BA
, 0, XtensaCP::CPBlockAddress
);
783 SDValue CPAddr
= DAG
.getTargetConstantPool(CPV
, PtrVT
, Align(4));
784 SDValue CPWrap
= getAddrPCRel(CPAddr
, DAG
);
789 SDValue
XtensaTargetLowering::LowerBR_JT(SDValue Op
, SelectionDAG
&DAG
) const {
790 SDValue Chain
= Op
.getOperand(0);
791 SDValue Table
= Op
.getOperand(1);
792 SDValue Index
= Op
.getOperand(2);
794 JumpTableSDNode
*JT
= cast
<JumpTableSDNode
>(Table
);
795 MachineFunction
&MF
= DAG
.getMachineFunction();
796 const MachineJumpTableInfo
*MJTI
= MF
.getJumpTableInfo();
797 SDValue TargetJT
= DAG
.getTargetJumpTable(JT
->getIndex(), MVT::i32
);
798 const DataLayout
&TD
= DAG
.getDataLayout();
799 EVT PtrVT
= Table
.getValueType();
800 unsigned EntrySize
= MJTI
->getEntrySize(TD
);
802 assert((MJTI
->getEntrySize(TD
) == 4) && "Unsupported jump-table entry size");
805 ISD::SHL
, DL
, Index
.getValueType(), Index
,
806 DAG
.getConstant(Log2_32(EntrySize
), DL
, Index
.getValueType()));
808 SDValue Addr
= DAG
.getNode(ISD::ADD
, DL
, Index
.getValueType(), Index
, Table
);
810 DAG
.getLoad(PtrVT
, DL
, Chain
, Addr
,
811 MachinePointerInfo::getJumpTable(DAG
.getMachineFunction()));
813 return DAG
.getNode(XtensaISD::BR_JT
, DL
, MVT::Other
, LD
.getValue(1), LD
,
817 SDValue
XtensaTargetLowering::LowerJumpTable(SDValue Op
,
818 SelectionDAG
&DAG
) const {
819 JumpTableSDNode
*JT
= cast
<JumpTableSDNode
>(Op
);
820 EVT PtrVT
= Op
.getValueType();
822 // Create a constant pool entry for the callee address
823 XtensaConstantPoolValue
*CPV
=
824 XtensaConstantPoolJumpTable::Create(*DAG
.getContext(), JT
->getIndex());
826 // Get the address of the callee into a register
827 SDValue CPAddr
= DAG
.getTargetConstantPool(CPV
, PtrVT
, Align(4));
829 return getAddrPCRel(CPAddr
, DAG
);
832 SDValue
XtensaTargetLowering::getAddrPCRel(SDValue Op
,
833 SelectionDAG
&DAG
) const {
835 EVT Ty
= Op
.getValueType();
836 return DAG
.getNode(XtensaISD::PCREL_WRAPPER
, DL
, Ty
, Op
);
839 SDValue
XtensaTargetLowering::LowerConstantPool(SDValue Op
,
840 SelectionDAG
&DAG
) const {
841 EVT PtrVT
= Op
.getValueType();
842 ConstantPoolSDNode
*CP
= cast
<ConstantPoolSDNode
>(Op
);
845 if (!CP
->isMachineConstantPoolEntry()) {
846 Result
= DAG
.getTargetConstantPool(CP
->getConstVal(), PtrVT
, CP
->getAlign(),
849 report_fatal_error("This constantpool type is not supported yet");
852 return getAddrPCRel(Result
, DAG
);
855 SDValue
XtensaTargetLowering::LowerSTACKSAVE(SDValue Op
,
856 SelectionDAG
&DAG
) const {
857 return DAG
.getCopyFromReg(Op
.getOperand(0), SDLoc(Op
), Xtensa::SP
,
861 SDValue
XtensaTargetLowering::LowerSTACKRESTORE(SDValue Op
,
862 SelectionDAG
&DAG
) const {
863 return DAG
.getCopyToReg(Op
.getOperand(0), SDLoc(Op
), Xtensa::SP
,
867 SDValue
XtensaTargetLowering::LowerFRAMEADDR(SDValue Op
,
868 SelectionDAG
&DAG
) const {
869 // This nodes represent llvm.frameaddress on the DAG.
870 // It takes one operand, the index of the frame address to return.
871 // An index of zero corresponds to the current function's frame address.
872 // An index of one to the parent's frame address, and so on.
873 // Depths > 0 not supported yet!
874 if (Op
.getConstantOperandVal(0) != 0)
877 MachineFunction
&MF
= DAG
.getMachineFunction();
878 MachineFrameInfo
&MFI
= MF
.getFrameInfo();
879 MFI
.setFrameAddressIsTaken(true);
880 EVT VT
= Op
.getValueType();
883 Register FrameRegister
= Subtarget
.getRegisterInfo()->getFrameRegister(MF
);
885 DAG
.getCopyFromReg(DAG
.getEntryNode(), DL
, FrameRegister
, VT
);
889 SDValue
XtensaTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op
,
890 SelectionDAG
&DAG
) const {
891 SDValue Chain
= Op
.getOperand(0); // Legalize the chain.
892 SDValue Size
= Op
.getOperand(1); // Legalize the size.
893 EVT VT
= Size
->getValueType(0);
896 // Round up Size to 32
898 DAG
.getNode(ISD::ADD
, DL
, VT
, Size
, DAG
.getConstant(31, DL
, MVT::i32
));
899 SDValue SizeRoundUp
= DAG
.getNode(ISD::AND
, DL
, VT
, SizeTmp
,
900 DAG
.getSignedConstant(~31, DL
, MVT::i32
));
902 unsigned SPReg
= Xtensa::SP
;
903 SDValue SP
= DAG
.getCopyFromReg(Chain
, DL
, SPReg
, VT
);
904 SDValue NewSP
= DAG
.getNode(ISD::SUB
, DL
, VT
, SP
, SizeRoundUp
); // Value
905 Chain
= DAG
.getCopyToReg(SP
.getValue(1), DL
, SPReg
, NewSP
); // Output chain
907 SDValue NewVal
= DAG
.getCopyFromReg(Chain
, DL
, SPReg
, MVT::i32
);
908 Chain
= NewVal
.getValue(1);
910 SDValue Ops
[2] = {NewVal
, Chain
};
911 return DAG
.getMergeValues(Ops
, DL
);
914 SDValue
XtensaTargetLowering::LowerVASTART(SDValue Op
,
915 SelectionDAG
&DAG
) const {
916 MachineFunction
&MF
= DAG
.getMachineFunction();
917 XtensaMachineFunctionInfo
*XtensaFI
= MF
.getInfo
<XtensaMachineFunctionInfo
>();
918 SDValue Chain
= Op
.getOperand(0);
919 SDValue Addr
= Op
.getOperand(1);
920 EVT PtrVT
= Addr
.getValueType();
923 // Struct va_list_tag
924 // int32 *va_stk - points to the arguments passed in memory
925 // int32 *va_reg - points to the registers with arguments saved in memory
926 // int32 va_ndx - offset from va_stk or va_reg pointers which points to the
927 // next variable argument
930 SDValue StackOffsetFI
=
931 DAG
.getFrameIndex(XtensaFI
->getVarArgsOnStackFrameIndex(), PtrVT
);
932 unsigned ArgWords
= XtensaFI
->getVarArgsFirstGPR() - 2;
934 // If first variable argument passed in registers (maximum words in registers
935 // is 6) then set va_ndx to the position of this argument in registers area
936 // stored in memory (va_reg pointer). Otherwise va_ndx should point to the
937 // position of the first variable argument on stack (va_stk pointer).
939 VAIndex
= DAG
.getConstant(ArgWords
* 4, DL
, MVT::i32
);
941 VAIndex
= DAG
.getConstant(32, DL
, MVT::i32
);
945 DAG
.getFrameIndex(XtensaFI
->getVarArgsInRegsFrameIndex(), PtrVT
);
946 uint64_t FrameOffset
= PtrVT
.getStoreSize();
947 const Value
*SV
= cast
<SrcValueSDNode
>(Op
.getOperand(2))->getValue();
949 // Store pointer to arguments given on stack (va_stk)
950 SDValue StackPtr
= DAG
.getNode(ISD::SUB
, DL
, PtrVT
, StackOffsetFI
,
951 DAG
.getConstant(32, DL
, PtrVT
));
953 SDValue StoreStackPtr
=
954 DAG
.getStore(Chain
, DL
, StackPtr
, Addr
, MachinePointerInfo(SV
));
956 uint64_t NextOffset
= FrameOffset
;
958 DAG
.getObjectPtrOffset(DL
, Addr
, TypeSize::getFixed(NextOffset
));
960 // Store pointer to arguments given on registers (va_reg)
961 SDValue StoreRegPtr
= DAG
.getStore(StoreStackPtr
, DL
, FrameIndex
, NextPtr
,
962 MachinePointerInfo(SV
, NextOffset
));
963 NextOffset
+= FrameOffset
;
964 NextPtr
= DAG
.getObjectPtrOffset(DL
, Addr
, TypeSize::getFixed(NextOffset
));
966 // Store third word : position in bytes of the first VA argument (va_ndx)
967 return DAG
.getStore(StoreRegPtr
, DL
, VAIndex
, NextPtr
,
968 MachinePointerInfo(SV
, NextOffset
));
971 SDValue
XtensaTargetLowering::LowerVACOPY(SDValue Op
, SelectionDAG
&DAG
) const {
972 // Size of the va_list_tag structure
973 constexpr unsigned VAListSize
= 3 * 4;
974 SDValue Chain
= Op
.getOperand(0);
975 SDValue DstPtr
= Op
.getOperand(1);
976 SDValue SrcPtr
= Op
.getOperand(2);
977 const Value
*DstSV
= cast
<SrcValueSDNode
>(Op
.getOperand(3))->getValue();
978 const Value
*SrcSV
= cast
<SrcValueSDNode
>(Op
.getOperand(4))->getValue();
981 return DAG
.getMemcpy(Chain
, DL
, DstPtr
, SrcPtr
,
982 DAG
.getConstant(VAListSize
, SDLoc(Op
), MVT::i32
),
983 Align(4), /*isVolatile*/ false, /*AlwaysInline*/ true,
984 /*CI=*/nullptr, std::nullopt
, MachinePointerInfo(DstSV
),
985 MachinePointerInfo(SrcSV
));
988 SDValue
XtensaTargetLowering::LowerVAARG(SDValue Op
, SelectionDAG
&DAG
) const {
989 SDNode
*Node
= Op
.getNode();
990 EVT VT
= Node
->getValueType(0);
991 Type
*Ty
= VT
.getTypeForEVT(*DAG
.getContext());
992 EVT PtrVT
= Op
.getValueType();
993 SDValue InChain
= Node
->getOperand(0);
994 SDValue VAListPtr
= Node
->getOperand(1);
995 const Value
*SV
= cast
<SrcValueSDNode
>(Node
->getOperand(2))->getValue();
997 auto &TD
= DAG
.getDataLayout();
998 Align ArgAlignment
= TD
.getABITypeAlign(Ty
);
999 unsigned ArgAlignInBytes
= ArgAlignment
.value();
1000 unsigned ArgSizeInBytes
= TD
.getTypeAllocSize(Ty
);
1001 unsigned VASizeInBytes
= llvm::alignTo(ArgSizeInBytes
, 4);
1005 DAG
.getLoad(MVT::i32
, DL
, InChain
, VAListPtr
, MachinePointerInfo());
1006 InChain
= VAStack
.getValue(1);
1010 DAG
.getObjectPtrOffset(DL
, VAListPtr
, TypeSize::getFixed(4));
1012 DAG
.getLoad(MVT::i32
, DL
, InChain
, VARegPtr
, MachinePointerInfo());
1013 InChain
= VAReg
.getValue(1);
1016 SDValue VarArgIndexPtr
=
1017 DAG
.getObjectPtrOffset(DL
, VARegPtr
, TypeSize::getFixed(4));
1019 DAG
.getLoad(MVT::i32
, DL
, InChain
, VarArgIndexPtr
, MachinePointerInfo());
1020 InChain
= VAIndex
.getValue(1);
1022 SDValue OrigIndex
= VAIndex
;
1024 if (ArgAlignInBytes
> 4) {
1025 OrigIndex
= DAG
.getNode(ISD::ADD
, DL
, PtrVT
, OrigIndex
,
1026 DAG
.getConstant(ArgAlignInBytes
- 1, DL
, MVT::i32
));
1028 DAG
.getNode(ISD::AND
, DL
, PtrVT
, OrigIndex
,
1029 DAG
.getSignedConstant(-ArgAlignInBytes
, DL
, MVT::i32
));
1032 VAIndex
= DAG
.getNode(ISD::ADD
, DL
, PtrVT
, OrigIndex
,
1033 DAG
.getConstant(VASizeInBytes
, DL
, MVT::i32
));
1035 SDValue CC
= DAG
.getSetCC(DL
, MVT::i32
, OrigIndex
,
1036 DAG
.getConstant(6 * 4, DL
, MVT::i32
), ISD::SETLE
);
1039 DAG
.getNode(ISD::ADD
, DL
, PtrVT
, VAIndex
,
1040 DAG
.getConstant(32 + VASizeInBytes
, DL
, MVT::i32
));
1042 CC
= DAG
.getSetCC(DL
, MVT::i32
, VAIndex
, DAG
.getConstant(6 * 4, DL
, MVT::i32
),
1045 SDValue Array
= DAG
.getNode(ISD::SELECT
, DL
, MVT::i32
, CC
, VAReg
, VAStack
);
1047 VAIndex
= DAG
.getNode(ISD::SELECT
, DL
, MVT::i32
, CC
, VAIndex
, StkIndex
);
1049 CC
= DAG
.getSetCC(DL
, MVT::i32
, VAIndex
, DAG
.getConstant(6 * 4, DL
, MVT::i32
),
1052 SDValue VAIndexStore
= DAG
.getStore(InChain
, DL
, VAIndex
, VarArgIndexPtr
,
1053 MachinePointerInfo(SV
));
1054 InChain
= VAIndexStore
;
1056 SDValue Addr
= DAG
.getNode(ISD::SUB
, DL
, PtrVT
, VAIndex
,
1057 DAG
.getConstant(VASizeInBytes
, DL
, MVT::i32
));
1059 Addr
= DAG
.getNode(ISD::ADD
, DL
, PtrVT
, Array
, Addr
);
1061 return DAG
.getLoad(VT
, DL
, InChain
, Addr
, MachinePointerInfo());
1064 SDValue
XtensaTargetLowering::LowerShiftLeftParts(SDValue Op
,
1065 SelectionDAG
&DAG
) const {
1068 SDValue Lo
= Op
.getOperand(0), Hi
= Op
.getOperand(1);
1069 SDValue Shamt
= Op
.getOperand(2);
1071 // if Shamt - register size < 0: // Shamt < register size
1073 // Hi = (Hi << Shamt) | (Lo >>u (register size - Shamt))
1076 // Hi = Lo << (Shamt - register size)
1078 SDValue MinusRegisterSize
= DAG
.getSignedConstant(-32, DL
, VT
);
1079 SDValue ShamtMinusRegisterSize
=
1080 DAG
.getNode(ISD::ADD
, DL
, VT
, Shamt
, MinusRegisterSize
);
1082 SDValue LoTrue
= DAG
.getNode(ISD::SHL
, DL
, VT
, Lo
, Shamt
);
1083 SDValue HiTrue
= DAG
.getNode(XtensaISD::SRCL
, DL
, VT
, Hi
, Lo
, Shamt
);
1084 SDValue Zero
= DAG
.getConstant(0, DL
, VT
);
1085 SDValue HiFalse
= DAG
.getNode(ISD::SHL
, DL
, VT
, Lo
, ShamtMinusRegisterSize
);
1087 SDValue Cond
= DAG
.getSetCC(DL
, VT
, ShamtMinusRegisterSize
, Zero
, ISD::SETLT
);
1088 Lo
= DAG
.getNode(ISD::SELECT
, DL
, VT
, Cond
, LoTrue
, Zero
);
1089 Hi
= DAG
.getNode(ISD::SELECT
, DL
, VT
, Cond
, HiTrue
, HiFalse
);
1091 return DAG
.getMergeValues({Lo
, Hi
}, DL
);
1094 SDValue
XtensaTargetLowering::LowerShiftRightParts(SDValue Op
,
1098 SDValue Lo
= Op
.getOperand(0), Hi
= Op
.getOperand(1);
1099 SDValue Shamt
= Op
.getOperand(2);
1103 // if Shamt - register size < 0: // Shamt < register size
1104 // Lo = (Lo >>u Shamt) | (Hi << u (register size - Shamt))
1105 // Hi = Hi >>s Shamt
1107 // Lo = Hi >>s (Shamt - register size);
1108 // Hi = Hi >>s (register size - 1)
1111 // if Shamt - register size < 0: // Shamt < register size
1112 // Lo = (Lo >>u Shamt) | (Hi << u (register size - Shamt))
1113 // Hi = Hi >>u Shamt
1115 // Lo = Hi >>u (Shamt - register size);
1118 unsigned ShiftRightOp
= IsSRA
? ISD::SRA
: ISD::SRL
;
1119 SDValue MinusRegisterSize
= DAG
.getSignedConstant(-32, DL
, VT
);
1120 SDValue RegisterSizeMinus1
= DAG
.getConstant(32 - 1, DL
, VT
);
1121 SDValue ShamtMinusRegisterSize
=
1122 DAG
.getNode(ISD::ADD
, DL
, VT
, Shamt
, MinusRegisterSize
);
1124 SDValue LoTrue
= DAG
.getNode(XtensaISD::SRCR
, DL
, VT
, Hi
, Lo
, Shamt
);
1125 SDValue HiTrue
= DAG
.getNode(ShiftRightOp
, DL
, VT
, Hi
, Shamt
);
1126 SDValue Zero
= DAG
.getConstant(0, DL
, VT
);
1128 DAG
.getNode(ShiftRightOp
, DL
, VT
, Hi
, ShamtMinusRegisterSize
);
1132 HiFalse
= DAG
.getNode(ShiftRightOp
, DL
, VT
, Hi
, RegisterSizeMinus1
);
1137 SDValue Cond
= DAG
.getSetCC(DL
, VT
, ShamtMinusRegisterSize
, Zero
, ISD::SETLT
);
1138 Lo
= DAG
.getNode(ISD::SELECT
, DL
, VT
, Cond
, LoTrue
, LoFalse
);
1139 Hi
= DAG
.getNode(ISD::SELECT
, DL
, VT
, Cond
, HiTrue
, HiFalse
);
1141 return DAG
.getMergeValues({Lo
, Hi
}, DL
);
1144 SDValue
XtensaTargetLowering::LowerCTPOP(SDValue Op
, SelectionDAG
&DAG
) const {
1145 auto &TLI
= DAG
.getTargetLoweringInfo();
1146 return TLI
.expandCTPOP(Op
.getNode(), DAG
);
1149 bool XtensaTargetLowering::decomposeMulByConstant(LLVMContext
&Context
, EVT VT
,
1152 unsigned EltSizeInBits
;
1154 if (ISD::isConstantSplatVector(C
.getNode(), Imm
)) {
1155 EltSizeInBits
= VT
.getScalarSizeInBits();
1156 } else if (VT
.isScalarInteger()) {
1157 EltSizeInBits
= VT
.getSizeInBits();
1158 if (auto *ConstNode
= dyn_cast
<ConstantSDNode
>(C
.getNode()))
1159 Imm
= ConstNode
->getAPIntValue();
1166 // Omit if data size exceeds.
1167 if (EltSizeInBits
> 32)
1170 // Convert MULT to LSL.
1171 if (Imm
.isPowerOf2() && Imm
.isIntN(5))
1177 SDValue
XtensaTargetLowering::LowerOperation(SDValue Op
,
1178 SelectionDAG
&DAG
) const {
1179 switch (Op
.getOpcode()) {
1181 return LowerBR_JT(Op
, DAG
);
1183 return LowerImmediate(Op
, DAG
);
1184 case ISD::RETURNADDR
:
1185 return LowerRETURNADDR(Op
, DAG
);
1186 case ISD::GlobalAddress
:
1187 return LowerGlobalAddress(Op
, DAG
);
1188 case ISD::BlockAddress
:
1189 return LowerBlockAddress(Op
, DAG
);
1190 case ISD::JumpTable
:
1191 return LowerJumpTable(Op
, DAG
);
1193 return LowerCTPOP(Op
, DAG
);
1194 case ISD::ConstantPool
:
1195 return LowerConstantPool(Op
, DAG
);
1196 case ISD::SELECT_CC
:
1197 return LowerSELECT_CC(Op
, DAG
);
1198 case ISD::STACKSAVE
:
1199 return LowerSTACKSAVE(Op
, DAG
);
1200 case ISD::STACKRESTORE
:
1201 return LowerSTACKRESTORE(Op
, DAG
);
1202 case ISD::FRAMEADDR
:
1203 return LowerFRAMEADDR(Op
, DAG
);
1204 case ISD::DYNAMIC_STACKALLOC
:
1205 return LowerDYNAMIC_STACKALLOC(Op
, DAG
);
1207 return LowerVASTART(Op
, DAG
);
1209 return LowerVAARG(Op
, DAG
);
1211 return LowerVACOPY(Op
, DAG
);
1212 case ISD::SHL_PARTS
:
1213 return LowerShiftLeftParts(Op
, DAG
);
1214 case ISD::SRA_PARTS
:
1215 return LowerShiftRightParts(Op
, DAG
, true);
1216 case ISD::SRL_PARTS
:
1217 return LowerShiftRightParts(Op
, DAG
, false);
1219 report_fatal_error("Unexpected node to lower");
1223 const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode
) const {
1225 case XtensaISD::BR_JT
:
1226 return "XtensaISD::BR_JT";
1227 case XtensaISD::CALL
:
1228 return "XtensaISD::CALL";
1229 case XtensaISD::EXTUI
:
1230 return "XtensaISD::EXTUI";
1231 case XtensaISD::PCREL_WRAPPER
:
1232 return "XtensaISD::PCREL_WRAPPER";
1233 case XtensaISD::RET
:
1234 return "XtensaISD::RET";
1235 case XtensaISD::SELECT_CC
:
1236 return "XtensaISD::SELECT_CC";
1237 case XtensaISD::SRCL
:
1238 return "XtensaISD::SRCL";
1239 case XtensaISD::SRCR
:
1240 return "XtensaISD::SRCR";
1245 //===----------------------------------------------------------------------===//
1247 //===----------------------------------------------------------------------===//
1250 XtensaTargetLowering::emitSelectCC(MachineInstr
&MI
,
1251 MachineBasicBlock
*MBB
) const {
1252 const TargetInstrInfo
&TII
= *Subtarget
.getInstrInfo();
1253 DebugLoc DL
= MI
.getDebugLoc();
1255 MachineOperand
&LHS
= MI
.getOperand(1);
1256 MachineOperand
&RHS
= MI
.getOperand(2);
1257 MachineOperand
&TrueValue
= MI
.getOperand(3);
1258 MachineOperand
&FalseValue
= MI
.getOperand(4);
1259 unsigned BrKind
= MI
.getOperand(5).getImm();
1261 // To "insert" a SELECT_CC instruction, we actually have to insert
1262 // CopyMBB and SinkMBB blocks and add branch to MBB. We build phi
1263 // operation in SinkMBB like phi (TrueVakue,FalseValue), where TrueValue
1264 // is passed from MMB and FalseValue is passed from CopyMBB.
1270 // The incoming instruction knows the
1271 // destination vreg to set, the condition code register to branch on, the
1272 // true/false values to select between, and a branch opcode to use.
1273 const BasicBlock
*LLVM_BB
= MBB
->getBasicBlock();
1274 MachineFunction::iterator It
= ++MBB
->getIterator();
1276 MachineFunction
*F
= MBB
->getParent();
1277 MachineBasicBlock
*CopyMBB
= F
->CreateMachineBasicBlock(LLVM_BB
);
1278 MachineBasicBlock
*SinkMBB
= F
->CreateMachineBasicBlock(LLVM_BB
);
1280 F
->insert(It
, CopyMBB
);
1281 F
->insert(It
, SinkMBB
);
1283 // Transfer the remainder of MBB and its successor edges to SinkMBB.
1284 SinkMBB
->splice(SinkMBB
->begin(), MBB
,
1285 std::next(MachineBasicBlock::iterator(MI
)), MBB
->end());
1286 SinkMBB
->transferSuccessorsAndUpdatePHIs(MBB
);
1288 MBB
->addSuccessor(CopyMBB
);
1289 MBB
->addSuccessor(SinkMBB
);
1291 BuildMI(MBB
, DL
, TII
.get(BrKind
))
1292 .addReg(LHS
.getReg())
1293 .addReg(RHS
.getReg())
1296 CopyMBB
->addSuccessor(SinkMBB
);
1299 // %Result = phi [ %FalseValue, CopyMBB ], [ %TrueValue, MBB ]
1302 BuildMI(*SinkMBB
, SinkMBB
->begin(), DL
, TII
.get(Xtensa::PHI
),
1303 MI
.getOperand(0).getReg())
1304 .addReg(FalseValue
.getReg())
1306 .addReg(TrueValue
.getReg())
1309 MI
.eraseFromParent(); // The pseudo instruction is gone now.
1313 MachineBasicBlock
*XtensaTargetLowering::EmitInstrWithCustomInserter(
1314 MachineInstr
&MI
, MachineBasicBlock
*MBB
) const {
1315 DebugLoc DL
= MI
.getDebugLoc();
1316 const XtensaInstrInfo
&TII
= *Subtarget
.getInstrInfo();
1318 switch (MI
.getOpcode()) {
1319 case Xtensa::SELECT
:
1320 return emitSelectCC(MI
, MBB
);
1324 case Xtensa::S32I_N
:
1329 case Xtensa::L32I_N
: {
1330 // Insert memory wait instruction "memw" before volatile load/store as it is
1331 // implemented in gcc. If memoperands is empty then assume that it aslo
1332 // maybe volatile load/store and insert "memw".
1333 if (MI
.memoperands_empty() || (*MI
.memoperands_begin())->isVolatile()) {
1334 BuildMI(*MBB
, MI
, DL
, TII
.get(Xtensa::MEMW
));
1339 llvm_unreachable("Unexpected instr type to insert");