llvm/lib/Target/Xtensa/XtensaInstrInfo.h

   1 //===-- XtensaInstrInfo.h - Xtensa Instruction Information ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   6 // See https://llvm.org/LICENSE.txt for license information.
   7 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   8 //
   9 //===----------------------------------------------------------------------===//
  10 //
  11 // This file contains the Xtensa implementation of the TargetInstrInfo class.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H
  16 #define LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H
  17
  18 #include "Xtensa.h"
  19 #include "XtensaRegisterInfo.h"
  20 #include "llvm/CodeGen/TargetInstrInfo.h"
  21 #include "llvm/CodeGen/TargetRegisterInfo.h"
  22
  23 #define GET_INSTRINFO_HEADER
  24
  25 #include "XtensaGenInstrInfo.inc"
  26
  27 namespace llvm {
  28
  29 class XtensaTargetMachine;
  30 class XtensaSubtarget;
  31 class XtensaInstrInfo : public XtensaGenInstrInfo {
  32   const XtensaRegisterInfo RI;
  33   const XtensaSubtarget &STI;
  34
  35 public:
  36   XtensaInstrInfo(const XtensaSubtarget &STI);
  37
  38   void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
  39                       MachineBasicBlock::iterator I) const;
  40
  41   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
  42
  43   // Return the XtensaRegisterInfo, which this class owns.
  44   const XtensaRegisterInfo &getRegisterInfo() const { return RI; }
  45
  46   Register isLoadFromStackSlot(const MachineInstr &MI,
  47                                int &FrameIndex) const override;
  48
  49   Register isStoreToStackSlot(const MachineInstr &MI,
  50                               int &FrameIndex) const override;
  51
  52   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
  53                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
  54                    bool KillSrc, bool RenamableDest = false,
  55                    bool RenamableSrc = false) const override;
  56
  57   void storeRegToStackSlot(MachineBasicBlock &MBB,
  58                            MachineBasicBlock::iterator MBBI, Register SrcReg,
  59                            bool isKill, int FrameIndex,
  60                            const TargetRegisterClass *RC,
  61                            const TargetRegisterInfo *TRI,
  62                            Register VReg) const override;
  63
  64   void loadRegFromStackSlot(MachineBasicBlock &MBB,
  65                             MachineBasicBlock::iterator MBBI, Register DestReg,
  66                             int FrameIdx, const TargetRegisterClass *RC,
  67                             const TargetRegisterInfo *TRI,
  68                             Register VReg) const override;
  69
  70   // Get the load and store opcodes for a given register class and offset.
  71   void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode,
  72                            unsigned &StoreOpcode, int64_t offset) const;
  73
  74   // Emit code before MBBI in MI to move immediate value Value into
  75   // physical register Reg.
  76   void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
  77                      unsigned *Reg, int64_t Value) const;
  78
  79   bool
  80   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
  81
  82   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
  83
  84   bool isBranchOffsetInRange(unsigned BranchOpc,
  85                              int64_t BrOffset) const override;
  86
  87   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  88                      MachineBasicBlock *&FBB,
  89                      SmallVectorImpl<MachineOperand> &Cond,
  90                      bool AllowModify) const override;
  91
  92   unsigned removeBranch(MachineBasicBlock &MBB,
  93                         int *BytesRemoved = nullptr) const override;
  94
  95   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  96                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
  97                         const DebugLoc &DL,
  98                         int *BytesAdded = nullptr) const override;
  99
 100   void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &DestBB,
 101                             MachineBasicBlock &RestoreBB, const DebugLoc &DL,
 102                             int64_t BrOffset = 0,
 103                             RegScavenger *RS = nullptr) const override;
 104
 105   unsigned insertBranchAtInst(MachineBasicBlock &MBB,
 106                               MachineBasicBlock::iterator I,
 107                               MachineBasicBlock *TBB,
 108                               ArrayRef<MachineOperand> Cond, const DebugLoc &DL,
 109                               int *BytesAdded) const;
 110
 111   unsigned insertConstBranchAtInst(MachineBasicBlock &MBB, MachineInstr *I,
 112                                    int64_t offset,
 113                                    ArrayRef<MachineOperand> Cond, DebugLoc DL,
 114                                    int *BytesAdded) const;
 115
 116   // Return true if MI is a conditional or unconditional branch.
 117   // When returning true, set Cond to the mask of condition-code
 118   // values on which the instruction will branch, and set Target
 119   // to the operand that contains the branch target.  This target
 120   // can be a register or a basic block.
 121   bool isBranch(const MachineBasicBlock::iterator &MI,
 122                 SmallVectorImpl<MachineOperand> &Cond,
 123                 const MachineOperand *&Target) const;
 124
 125   const XtensaSubtarget &getSubtarget() const { return STI; }
 126 };
 127 } // end namespace llvm
 128
 129 #endif /* LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H */