AMDGPU: Mark test as XFAIL in expensive_checks builds
[llvm-project.git] / llvm / lib / Target / Xtensa / XtensaRegisterInfo.h
blobede0eeb90b42ded03093716a0bf1c47f64ce3e91
1 //===-- XtensaRegisterInfo.h - Xtensa Register Information Impl -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Xtensa implementation of the TargetRegisterInfo class.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_XTENSA_XTENSAREGISTERINFO_H
14 #define LLVM_LIB_TARGET_XTENSA_XTENSAREGISTERINFO_H
16 #include "Xtensa.h"
17 #include "llvm/CodeGen/TargetRegisterInfo.h"
19 #define GET_REGINFO_HEADER
20 #include "XtensaGenRegisterInfo.inc"
22 namespace llvm {
23 class TargetRegisterClass;
24 class XtensaInstrInfo;
25 class XtensaSubtarget;
27 class XtensaRegisterInfo : public XtensaGenRegisterInfo {
28 public:
29 const XtensaSubtarget &Subtarget;
31 XtensaRegisterInfo(const XtensaSubtarget &STI);
33 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
34 return true;
37 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
38 return true;
41 bool trackLivenessAfterRegAlloc(const MachineFunction &) const override {
42 return true;
45 const uint16_t *
46 getCalleeSavedRegs(const MachineFunction *MF = 0) const override;
47 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
48 CallingConv::ID) const override;
49 BitVector getReservedRegs(const MachineFunction &MF) const override;
51 bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
52 unsigned FIOperandNum,
53 RegScavenger *RS = nullptr) const override;
55 Register getFrameRegister(const MachineFunction &MF) const override;
58 } // end namespace llvm
60 #endif // LLVM_LIB_TARGET_XTENSA_REGISTERINFO_H