1 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements a target parser to recognise ARM hardware features
10 // such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/TargetParser/ARMTargetParser.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/Support/Format.h"
17 #include "llvm/Support/raw_ostream.h"
18 #include "llvm/TargetParser/ARMTargetParserCommon.h"
19 #include "llvm/TargetParser/Triple.h"
24 static StringRef
getHWDivSynonym(StringRef HWDiv
) {
25 return StringSwitch
<StringRef
>(HWDiv
)
26 .Case("thumb,arm", "arm,thumb")
30 // Allows partial match, ex. "v7a" matches "armv7a".
31 ARM::ArchKind
ARM::parseArch(StringRef Arch
) {
32 Arch
= getCanonicalArchName(Arch
);
33 StringRef Syn
= getArchSynonym(Arch
);
34 for (const auto &A
: ARMArchNames
) {
35 if (A
.Name
.ends_with(Syn
))
38 return ArchKind::INVALID
;
41 // Version number (ex. v7 = 7).
42 unsigned ARM::parseArchVersion(StringRef Arch
) {
43 Arch
= getCanonicalArchName(Arch
);
44 switch (parseArch(Arch
)) {
46 case ArchKind::ARMV4T
:
48 case ArchKind::ARMV5T
:
49 case ArchKind::ARMV5TE
:
50 case ArchKind::IWMMXT
:
51 case ArchKind::IWMMXT2
:
52 case ArchKind::XSCALE
:
53 case ArchKind::ARMV5TEJ
:
56 case ArchKind::ARMV6K
:
57 case ArchKind::ARMV6T2
:
58 case ArchKind::ARMV6KZ
:
59 case ArchKind::ARMV6M
:
61 case ArchKind::ARMV7A
:
62 case ArchKind::ARMV7VE
:
63 case ArchKind::ARMV7R
:
64 case ArchKind::ARMV7M
:
65 case ArchKind::ARMV7S
:
66 case ArchKind::ARMV7EM
:
67 case ArchKind::ARMV7K
:
69 case ArchKind::ARMV8A
:
70 case ArchKind::ARMV8_1A
:
71 case ArchKind::ARMV8_2A
:
72 case ArchKind::ARMV8_3A
:
73 case ArchKind::ARMV8_4A
:
74 case ArchKind::ARMV8_5A
:
75 case ArchKind::ARMV8_6A
:
76 case ArchKind::ARMV8_7A
:
77 case ArchKind::ARMV8_8A
:
78 case ArchKind::ARMV8_9A
:
79 case ArchKind::ARMV8R
:
80 case ArchKind::ARMV8MBaseline
:
81 case ArchKind::ARMV8MMainline
:
82 case ArchKind::ARMV8_1MMainline
:
84 case ArchKind::ARMV9A
:
85 case ArchKind::ARMV9_1A
:
86 case ArchKind::ARMV9_2A
:
87 case ArchKind::ARMV9_3A
:
88 case ArchKind::ARMV9_4A
:
89 case ArchKind::ARMV9_5A
:
90 case ArchKind::ARMV9_6A
:
92 case ArchKind::INVALID
:
95 llvm_unreachable("Unhandled architecture");
98 static ARM::ProfileKind
getProfileKind(ARM::ArchKind AK
) {
100 case ARM::ArchKind::ARMV6M
:
101 case ARM::ArchKind::ARMV7M
:
102 case ARM::ArchKind::ARMV7EM
:
103 case ARM::ArchKind::ARMV8MMainline
:
104 case ARM::ArchKind::ARMV8MBaseline
:
105 case ARM::ArchKind::ARMV8_1MMainline
:
106 return ARM::ProfileKind::M
;
107 case ARM::ArchKind::ARMV7R
:
108 case ARM::ArchKind::ARMV8R
:
109 return ARM::ProfileKind::R
;
110 case ARM::ArchKind::ARMV7A
:
111 case ARM::ArchKind::ARMV7VE
:
112 case ARM::ArchKind::ARMV7K
:
113 case ARM::ArchKind::ARMV8A
:
114 case ARM::ArchKind::ARMV8_1A
:
115 case ARM::ArchKind::ARMV8_2A
:
116 case ARM::ArchKind::ARMV8_3A
:
117 case ARM::ArchKind::ARMV8_4A
:
118 case ARM::ArchKind::ARMV8_5A
:
119 case ARM::ArchKind::ARMV8_6A
:
120 case ARM::ArchKind::ARMV8_7A
:
121 case ARM::ArchKind::ARMV8_8A
:
122 case ARM::ArchKind::ARMV8_9A
:
123 case ARM::ArchKind::ARMV9A
:
124 case ARM::ArchKind::ARMV9_1A
:
125 case ARM::ArchKind::ARMV9_2A
:
126 case ARM::ArchKind::ARMV9_3A
:
127 case ARM::ArchKind::ARMV9_4A
:
128 case ARM::ArchKind::ARMV9_5A
:
129 case ARM::ArchKind::ARMV9_6A
:
130 return ARM::ProfileKind::A
;
131 case ARM::ArchKind::ARMV4
:
132 case ARM::ArchKind::ARMV4T
:
133 case ARM::ArchKind::ARMV5T
:
134 case ARM::ArchKind::ARMV5TE
:
135 case ARM::ArchKind::ARMV5TEJ
:
136 case ARM::ArchKind::ARMV6
:
137 case ARM::ArchKind::ARMV6K
:
138 case ARM::ArchKind::ARMV6T2
:
139 case ARM::ArchKind::ARMV6KZ
:
140 case ARM::ArchKind::ARMV7S
:
141 case ARM::ArchKind::IWMMXT
:
142 case ARM::ArchKind::IWMMXT2
:
143 case ARM::ArchKind::XSCALE
:
144 case ARM::ArchKind::INVALID
:
145 return ARM::ProfileKind::INVALID
;
147 llvm_unreachable("Unhandled architecture");
151 ARM::ProfileKind
ARM::parseArchProfile(StringRef Arch
) {
152 Arch
= getCanonicalArchName(Arch
);
153 return getProfileKind(parseArch(Arch
));
156 bool ARM::getFPUFeatures(ARM::FPUKind FPUKind
,
157 std::vector
<StringRef
> &Features
) {
159 if (FPUKind
>= FK_LAST
|| FPUKind
== FK_INVALID
)
162 static const struct FPUFeatureNameInfo
{
163 const char *PlusName
, *MinusName
;
164 FPUVersion MinVersion
;
165 FPURestriction MaxRestriction
;
166 } FPUFeatureInfoList
[] = {
167 // We have to specify the + and - versions of the name in full so
168 // that we can return them as static StringRefs.
170 // Also, the SubtargetFeatures ending in just "sp" are listed here
171 // under FPURestriction::None, which is the only FPURestriction in
172 // which they would be valid (since FPURestriction::SP doesn't
174 {"+vfp2", "-vfp2", FPUVersion::VFPV2
, FPURestriction::D16
},
175 {"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2
, FPURestriction::SP_D16
},
176 {"+vfp3", "-vfp3", FPUVersion::VFPV3
, FPURestriction::None
},
177 {"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3
, FPURestriction::D16
},
178 {"+vfp3d16sp", "-vfp3d16sp", FPUVersion::VFPV3
, FPURestriction::SP_D16
},
179 {"+vfp3sp", "-vfp3sp", FPUVersion::VFPV3
, FPURestriction::None
},
180 {"+fp16", "-fp16", FPUVersion::VFPV3_FP16
, FPURestriction::SP_D16
},
181 {"+vfp4", "-vfp4", FPUVersion::VFPV4
, FPURestriction::None
},
182 {"+vfp4d16", "-vfp4d16", FPUVersion::VFPV4
, FPURestriction::D16
},
183 {"+vfp4d16sp", "-vfp4d16sp", FPUVersion::VFPV4
, FPURestriction::SP_D16
},
184 {"+vfp4sp", "-vfp4sp", FPUVersion::VFPV4
, FPURestriction::None
},
185 {"+fp-armv8", "-fp-armv8", FPUVersion::VFPV5
, FPURestriction::None
},
186 {"+fp-armv8d16", "-fp-armv8d16", FPUVersion::VFPV5
, FPURestriction::D16
},
187 {"+fp-armv8d16sp", "-fp-armv8d16sp", FPUVersion::VFPV5
, FPURestriction::SP_D16
},
188 {"+fp-armv8sp", "-fp-armv8sp", FPUVersion::VFPV5
, FPURestriction::None
},
189 {"+fullfp16", "-fullfp16", FPUVersion::VFPV5_FULLFP16
, FPURestriction::SP_D16
},
190 {"+fp64", "-fp64", FPUVersion::VFPV2
, FPURestriction::D16
},
191 {"+d32", "-d32", FPUVersion::VFPV3
, FPURestriction::None
},
194 for (const auto &Info
: FPUFeatureInfoList
) {
195 if (FPUNames
[FPUKind
].FPUVer
>= Info
.MinVersion
&&
196 FPUNames
[FPUKind
].Restriction
<= Info
.MaxRestriction
)
197 Features
.push_back(Info
.PlusName
);
199 Features
.push_back(Info
.MinusName
);
202 static const struct NeonFeatureNameInfo
{
203 const char *PlusName
, *MinusName
;
204 NeonSupportLevel MinSupportLevel
;
205 } NeonFeatureInfoList
[] = {
206 {"+neon", "-neon", NeonSupportLevel::Neon
},
207 {"+sha2", "-sha2", NeonSupportLevel::Crypto
},
208 {"+aes", "-aes", NeonSupportLevel::Crypto
},
211 for (const auto &Info
: NeonFeatureInfoList
) {
212 if (FPUNames
[FPUKind
].NeonSupport
>= Info
.MinSupportLevel
)
213 Features
.push_back(Info
.PlusName
);
215 Features
.push_back(Info
.MinusName
);
221 ARM::FPUKind
ARM::parseFPU(StringRef FPU
) {
222 StringRef Syn
= getFPUSynonym(FPU
);
223 for (const auto &F
: FPUNames
) {
230 ARM::NeonSupportLevel
ARM::getFPUNeonSupportLevel(ARM::FPUKind FPUKind
) {
231 if (FPUKind
>= FK_LAST
)
232 return NeonSupportLevel::None
;
233 return FPUNames
[FPUKind
].NeonSupport
;
236 StringRef
ARM::getFPUSynonym(StringRef FPU
) {
237 return StringSwitch
<StringRef
>(FPU
)
238 .Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported
239 .Case("vfp2", "vfpv2")
240 .Case("vfp3", "vfpv3")
241 .Case("vfp4", "vfpv4")
242 .Case("vfp3-d16", "vfpv3-d16")
243 .Case("vfp4-d16", "vfpv4-d16")
244 .Cases("fp4-sp-d16", "vfpv4-sp-d16", "fpv4-sp-d16")
245 .Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16")
246 .Case("fp5-sp-d16", "fpv5-sp-d16")
247 .Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16")
248 // FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
249 .Case("neon-vfpv3", "neon")
253 StringRef
ARM::getFPUName(ARM::FPUKind FPUKind
) {
254 if (FPUKind
>= FK_LAST
)
256 return FPUNames
[FPUKind
].Name
;
259 ARM::FPUVersion
ARM::getFPUVersion(ARM::FPUKind FPUKind
) {
260 if (FPUKind
>= FK_LAST
)
261 return FPUVersion::NONE
;
262 return FPUNames
[FPUKind
].FPUVer
;
265 ARM::FPURestriction
ARM::getFPURestriction(ARM::FPUKind FPUKind
) {
266 if (FPUKind
>= FK_LAST
)
267 return FPURestriction::None
;
268 return FPUNames
[FPUKind
].Restriction
;
271 ARM::FPUKind
ARM::getDefaultFPU(StringRef CPU
, ARM::ArchKind AK
) {
272 if (CPU
== "generic")
273 return ARM::ARMArchNames
[static_cast<unsigned>(AK
)].DefaultFPU
;
275 return StringSwitch
<ARM::FPUKind
>(CPU
)
276 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
277 .Case(NAME, DEFAULT_FPU)
278 #include "llvm/TargetParser/ARMTargetParser.def"
279 .Default(ARM::FK_INVALID
);
282 uint64_t ARM::getDefaultExtensions(StringRef CPU
, ARM::ArchKind AK
) {
283 if (CPU
== "generic")
284 return ARM::ARMArchNames
[static_cast<unsigned>(AK
)].ArchBaseExtensions
;
286 return StringSwitch
<uint64_t>(CPU
)
287 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
289 ARMArchNames[static_cast<unsigned>(ArchKind::ID)].ArchBaseExtensions | \
291 #include "llvm/TargetParser/ARMTargetParser.def"
292 .Default(ARM::AEK_INVALID
);
295 bool ARM::getHWDivFeatures(uint64_t HWDivKind
,
296 std::vector
<StringRef
> &Features
) {
298 if (HWDivKind
== AEK_INVALID
)
301 if (HWDivKind
& AEK_HWDIVARM
)
302 Features
.push_back("+hwdiv-arm");
304 Features
.push_back("-hwdiv-arm");
306 if (HWDivKind
& AEK_HWDIVTHUMB
)
307 Features
.push_back("+hwdiv");
309 Features
.push_back("-hwdiv");
314 bool ARM::getExtensionFeatures(uint64_t Extensions
,
315 std::vector
<StringRef
> &Features
) {
317 if (Extensions
== AEK_INVALID
)
320 for (const auto &AE
: ARCHExtNames
) {
321 if ((Extensions
& AE
.ID
) == AE
.ID
&& !AE
.Feature
.empty())
322 Features
.push_back(AE
.Feature
);
323 else if (!AE
.NegFeature
.empty())
324 Features
.push_back(AE
.NegFeature
);
327 return getHWDivFeatures(Extensions
, Features
);
330 StringRef
ARM::getArchName(ARM::ArchKind AK
) {
331 return ARMArchNames
[static_cast<unsigned>(AK
)].Name
;
334 StringRef
ARM::getCPUAttr(ARM::ArchKind AK
) {
335 return ARMArchNames
[static_cast<unsigned>(AK
)].CPUAttr
;
338 StringRef
ARM::getSubArch(ARM::ArchKind AK
) {
339 return ARMArchNames
[static_cast<unsigned>(AK
)].getSubArch();
342 unsigned ARM::getArchAttr(ARM::ArchKind AK
) {
343 return ARMArchNames
[static_cast<unsigned>(AK
)].ArchAttr
;
346 StringRef
ARM::getArchExtName(uint64_t ArchExtKind
) {
347 for (const auto &AE
: ARCHExtNames
) {
348 if (ArchExtKind
== AE
.ID
)
354 static bool stripNegationPrefix(StringRef
&Name
) {
355 return Name
.consume_front("no");
358 StringRef
ARM::getArchExtFeature(StringRef ArchExt
) {
359 bool Negated
= stripNegationPrefix(ArchExt
);
360 for (const auto &AE
: ARCHExtNames
) {
361 if (!AE
.Feature
.empty() && ArchExt
== AE
.Name
)
362 return StringRef(Negated
? AE
.NegFeature
: AE
.Feature
);
368 static ARM::FPUKind
findDoublePrecisionFPU(ARM::FPUKind InputFPUKind
) {
369 if (InputFPUKind
== ARM::FK_INVALID
|| InputFPUKind
== ARM::FK_NONE
)
370 return ARM::FK_INVALID
;
372 const ARM::FPUName
&InputFPU
= ARM::FPUNames
[InputFPUKind
];
374 // If the input FPU already supports double-precision, then there
375 // isn't any different FPU we can return here.
376 if (ARM::isDoublePrecision(InputFPU
.Restriction
))
379 // Otherwise, look for an FPU entry with all the same fields, except
380 // that it supports double precision.
381 for (const ARM::FPUName
&CandidateFPU
: ARM::FPUNames
) {
382 if (CandidateFPU
.FPUVer
== InputFPU
.FPUVer
&&
383 CandidateFPU
.NeonSupport
== InputFPU
.NeonSupport
&&
384 ARM::has32Regs(CandidateFPU
.Restriction
) ==
385 ARM::has32Regs(InputFPU
.Restriction
) &&
386 ARM::isDoublePrecision(CandidateFPU
.Restriction
)) {
387 return CandidateFPU
.ID
;
392 return ARM::FK_INVALID
;
395 static ARM::FPUKind
findSinglePrecisionFPU(ARM::FPUKind InputFPUKind
) {
396 if (InputFPUKind
== ARM::FK_INVALID
|| InputFPUKind
== ARM::FK_NONE
)
397 return ARM::FK_INVALID
;
399 const ARM::FPUName
&InputFPU
= ARM::FPUNames
[InputFPUKind
];
401 // If the input FPU already is single-precision only, then there
402 // isn't any different FPU we can return here.
403 if (!ARM::isDoublePrecision(InputFPU
.Restriction
))
406 // Otherwise, look for an FPU entry with all the same fields, except
407 // that it does not support double precision.
408 for (const ARM::FPUName
&CandidateFPU
: ARM::FPUNames
) {
409 if (CandidateFPU
.FPUVer
== InputFPU
.FPUVer
&&
410 CandidateFPU
.NeonSupport
== InputFPU
.NeonSupport
&&
411 ARM::has32Regs(CandidateFPU
.Restriction
) ==
412 ARM::has32Regs(InputFPU
.Restriction
) &&
413 !ARM::isDoublePrecision(CandidateFPU
.Restriction
)) {
414 return CandidateFPU
.ID
;
419 return ARM::FK_INVALID
;
422 bool ARM::appendArchExtFeatures(StringRef CPU
, ARM::ArchKind AK
,
424 std::vector
<StringRef
> &Features
,
425 ARM::FPUKind
&ArgFPUKind
) {
427 size_t StartingNumFeatures
= Features
.size();
428 const bool Negated
= stripNegationPrefix(ArchExt
);
429 uint64_t ID
= parseArchExt(ArchExt
);
431 if (ID
== AEK_INVALID
)
434 for (const auto &AE
: ARCHExtNames
) {
436 if ((AE
.ID
& ID
) == ID
&& !AE
.NegFeature
.empty())
437 Features
.push_back(AE
.NegFeature
);
439 if ((AE
.ID
& ID
) == AE
.ID
&& !AE
.Feature
.empty())
440 Features
.push_back(AE
.Feature
);
447 if (ArchExt
== "fp" || ArchExt
== "fp.dp") {
448 const ARM::FPUKind DefaultFPU
= getDefaultFPU(CPU
, AK
);
449 ARM::FPUKind FPUKind
;
450 if (ArchExt
== "fp.dp") {
451 const bool IsDP
= ArgFPUKind
!= ARM::FK_INVALID
&&
452 ArgFPUKind
!= ARM::FK_NONE
&&
453 isDoublePrecision(getFPURestriction(ArgFPUKind
));
455 /* If there is no FPU selected yet, we still need to set ArgFPUKind, as
456 * leaving it as FK_INVALID, would cause default FPU to be selected
457 * later and that could be double precision one. */
458 if (ArgFPUKind
!= ARM::FK_INVALID
&& !IsDP
)
460 FPUKind
= findSinglePrecisionFPU(DefaultFPU
);
461 if (FPUKind
== ARM::FK_INVALID
)
462 FPUKind
= ARM::FK_NONE
;
466 FPUKind
= findDoublePrecisionFPU(DefaultFPU
);
467 if (FPUKind
== ARM::FK_INVALID
)
470 } else if (Negated
) {
471 FPUKind
= ARM::FK_NONE
;
473 FPUKind
= DefaultFPU
;
475 ArgFPUKind
= FPUKind
;
478 return StartingNumFeatures
!= Features
.size();
481 ARM::ArchKind
ARM::convertV9toV8(ARM::ArchKind AK
) {
482 if (getProfileKind(AK
) != ProfileKind::A
)
483 return ARM::ArchKind::INVALID
;
484 if (AK
< ARM::ArchKind::ARMV9A
|| AK
> ARM::ArchKind::ARMV9_3A
)
485 return ARM::ArchKind::INVALID
;
486 unsigned AK_v8
= static_cast<unsigned>(ARM::ArchKind::ARMV8_5A
);
487 AK_v8
+= static_cast<unsigned>(AK
) -
488 static_cast<unsigned>(ARM::ArchKind::ARMV9A
);
489 return static_cast<ARM::ArchKind
>(AK_v8
);
492 StringRef
ARM::getDefaultCPU(StringRef Arch
) {
493 ArchKind AK
= parseArch(Arch
);
494 if (AK
== ArchKind::INVALID
)
497 // Look for multiple AKs to find the default for pair AK+Name.
498 for (const auto &CPU
: CPUNames
) {
499 if (CPU
.ArchID
== AK
&& CPU
.Default
)
503 // If we can't find a default then target the architecture instead
507 uint64_t ARM::parseHWDiv(StringRef HWDiv
) {
508 StringRef Syn
= getHWDivSynonym(HWDiv
);
509 for (const auto &D
: HWDivNames
) {
516 uint64_t ARM::parseArchExt(StringRef ArchExt
) {
517 for (const auto &A
: ARCHExtNames
) {
518 if (ArchExt
== A
.Name
)
524 ARM::ArchKind
ARM::parseCPUArch(StringRef CPU
) {
525 for (const auto &C
: CPUNames
) {
529 return ArchKind::INVALID
;
532 void ARM::fillValidCPUArchList(SmallVectorImpl
<StringRef
> &Values
) {
533 for (const auto &Arch
: CPUNames
) {
534 if (Arch
.ArchID
!= ArchKind::INVALID
)
535 Values
.push_back(Arch
.Name
);
539 StringRef
ARM::computeDefaultTargetABI(const Triple
&TT
, StringRef CPU
) {
541 CPU
.empty() ? TT
.getArchName() : getArchName(parseCPUArch(CPU
));
543 if (TT
.isOSBinFormatMachO()) {
544 if (TT
.getEnvironment() == Triple::EABI
||
545 TT
.getOS() == Triple::UnknownOS
||
546 parseArchProfile(ArchName
) == ProfileKind::M
)
551 } else if (TT
.isOSWindows())
552 // FIXME: this is invalid for WindowsCE.
555 // Select the default based on the platform.
556 switch (TT
.getEnvironment()) {
557 case Triple::Android
:
558 case Triple::GNUEABI
:
559 case Triple::GNUEABIT64
:
560 case Triple::GNUEABIHF
:
561 case Triple::GNUEABIHFT64
:
562 case Triple::MuslEABI
:
563 case Triple::MuslEABIHF
:
564 case Triple::OpenHOS
:
565 return "aapcs-linux";
572 if (TT
.isOSFreeBSD() || TT
.isOSOpenBSD() || TT
.isOSHaiku() ||
574 return "aapcs-linux";
579 StringRef
ARM::getARMCPUForArch(const llvm::Triple
&Triple
, StringRef MArch
) {
581 MArch
= Triple
.getArchName();
582 MArch
= llvm::ARM::getCanonicalArchName(MArch
);
584 // Some defaults are forced.
585 switch (Triple
.getOS()) {
586 case llvm::Triple::FreeBSD
:
587 case llvm::Triple::NetBSD
:
588 case llvm::Triple::OpenBSD
:
589 case llvm::Triple::Haiku
:
590 if (!MArch
.empty() && MArch
== "v6")
591 return "arm1176jzf-s";
592 if (!MArch
.empty() && MArch
== "v7")
595 case llvm::Triple::Win32
:
596 // FIXME: this is invalid for WindowsCE
597 if (llvm::ARM::parseArchVersion(MArch
) <= 7)
600 case llvm::Triple::IOS
:
601 case llvm::Triple::MacOSX
:
602 case llvm::Triple::TvOS
:
603 case llvm::Triple::WatchOS
:
604 case llvm::Triple::DriverKit
:
605 case llvm::Triple::XROS
:
616 StringRef CPU
= llvm::ARM::getDefaultCPU(MArch
);
617 if (!CPU
.empty() && CPU
!= "invalid")
620 // If no specific architecture version is requested, return the minimum CPU
621 // required by the OS and environment.
622 switch (Triple
.getOS()) {
623 case llvm::Triple::Haiku
:
624 return "arm1176jzf-s";
625 case llvm::Triple::NetBSD
:
626 switch (Triple
.getEnvironment()) {
627 case llvm::Triple::EABI
:
628 case llvm::Triple::EABIHF
:
629 case llvm::Triple::GNUEABI
:
630 case llvm::Triple::GNUEABIHF
:
635 case llvm::Triple::NaCl
:
636 case llvm::Triple::OpenBSD
:
639 switch (Triple
.getEnvironment()) {
640 case llvm::Triple::EABIHF
:
641 case llvm::Triple::GNUEABIHF
:
642 case llvm::Triple::GNUEABIHFT64
:
643 case llvm::Triple::MuslEABIHF
:
644 return "arm1176jzf-s";
650 llvm_unreachable("invalid arch name");
653 void ARM::PrintSupportedExtensions(StringMap
<StringRef
> DescMap
) {
654 outs() << "All available -march extensions for ARM\n\n"
655 << " " << left_justify("Name", 20)
656 << (DescMap
.empty() ? "\n" : "Description\n");
657 for (const auto &Ext
: ARCHExtNames
) {
658 // Extensions without a feature cannot be used with -march.
659 if (!Ext
.Feature
.empty()) {
660 std::string Description
= DescMap
[Ext
.Name
].str();
662 << format(Description
.empty() ? "%s\n" : "%-20s%s\n",
663 Ext
.Name
.str().c_str(), Description
.c_str());