| blob | 0dea7be5052d03e8b31b286b4eb1a51990ae7209 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-CVT
3 ; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-FP16
4 ; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-CVT
5 ; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
7 ;
8 ; 32-bit float to unsigned integer
9 ;
11 declare i1 @llvm.fptoui.sat.i1.f32 (float)
12 declare i8 @llvm.fptoui.sat.i8.f32 (float)
13 declare i13 @llvm.fptoui.sat.i13.f32 (float)
14 declare i16 @llvm.fptoui.sat.i16.f32 (float)
15 declare i19 @llvm.fptoui.sat.i19.f32 (float)
16 declare i32 @llvm.fptoui.sat.i32.f32 (float)
17 declare i50 @llvm.fptoui.sat.i50.f32 (float)
18 declare i64 @llvm.fptoui.sat.i64.f32 (float)
19 declare i100 @llvm.fptoui.sat.i100.f32(float)
20 declare i128 @llvm.fptoui.sat.i128.f32(float)
22 define i1 @test_unsigned_i1_f32(float %f) nounwind {
23 ; CHECK-SD-LABEL: test_unsigned_i1_f32:
24 ; CHECK-SD: // %bb.0:
25 ; CHECK-SD-NEXT: fcvtzu w8, s0
26 ; CHECK-SD-NEXT: cmp w8, #1
27 ; CHECK-SD-NEXT: csinc w0, w8, wzr, lo
28 ; CHECK-SD-NEXT: ret
29 ;
30 ; CHECK-GI-LABEL: test_unsigned_i1_f32:
31 ; CHECK-GI: // %bb.0:
32 ; CHECK-GI-NEXT: fcvtzu w8, s0
33 ; CHECK-GI-NEXT: cmp w8, #1
34 ; CHECK-GI-NEXT: csinc w8, w8, wzr, lo
35 ; CHECK-GI-NEXT: and w0, w8, #0x1
36 ; CHECK-GI-NEXT: ret
37 %x = call i1 @llvm.fptoui.sat.i1.f32(float %f)
38 ret i1 %x
39 }
41 define i8 @test_unsigned_i8_f32(float %f) nounwind {
42 ; CHECK-LABEL: test_unsigned_i8_f32:
43 ; CHECK: // %bb.0:
44 ; CHECK-NEXT: fcvtzu w9, s0
45 ; CHECK-NEXT: mov w8, #255 // =0xff
46 ; CHECK-NEXT: cmp w9, #255
47 ; CHECK-NEXT: csel w0, w9, w8, lo
48 ; CHECK-NEXT: ret
49 %x = call i8 @llvm.fptoui.sat.i8.f32(float %f)
50 ret i8 %x
51 }
53 define i13 @test_unsigned_i13_f32(float %f) nounwind {
54 ; CHECK-LABEL: test_unsigned_i13_f32:
55 ; CHECK: // %bb.0:
56 ; CHECK-NEXT: fcvtzu w8, s0
57 ; CHECK-NEXT: mov w9, #8191 // =0x1fff
58 ; CHECK-NEXT: cmp w8, w9
59 ; CHECK-NEXT: csel w0, w8, w9, lo
60 ; CHECK-NEXT: ret
61 %x = call i13 @llvm.fptoui.sat.i13.f32(float %f)
62 ret i13 %x
63 }
65 define i16 @test_unsigned_i16_f32(float %f) nounwind {
66 ; CHECK-LABEL: test_unsigned_i16_f32:
67 ; CHECK: // %bb.0:
68 ; CHECK-NEXT: fcvtzu w8, s0
69 ; CHECK-NEXT: mov w9, #65535 // =0xffff
70 ; CHECK-NEXT: cmp w8, w9
71 ; CHECK-NEXT: csel w0, w8, w9, lo
72 ; CHECK-NEXT: ret
73 %x = call i16 @llvm.fptoui.sat.i16.f32(float %f)
74 ret i16 %x
75 }
77 define i19 @test_unsigned_i19_f32(float %f) nounwind {
78 ; CHECK-LABEL: test_unsigned_i19_f32:
79 ; CHECK: // %bb.0:
80 ; CHECK-NEXT: fcvtzu w8, s0
81 ; CHECK-NEXT: mov w9, #524287 // =0x7ffff
82 ; CHECK-NEXT: cmp w8, w9
83 ; CHECK-NEXT: csel w0, w8, w9, lo
84 ; CHECK-NEXT: ret
85 %x = call i19 @llvm.fptoui.sat.i19.f32(float %f)
86 ret i19 %x
87 }
89 define i32 @test_unsigned_i32_f32(float %f) nounwind {
90 ; CHECK-LABEL: test_unsigned_i32_f32:
91 ; CHECK: // %bb.0:
92 ; CHECK-NEXT: fcvtzu w0, s0
93 ; CHECK-NEXT: ret
94 %x = call i32 @llvm.fptoui.sat.i32.f32(float %f)
95 ret i32 %x
96 }
98 define i50 @test_unsigned_i50_f32(float %f) nounwind {
99 ; CHECK-LABEL: test_unsigned_i50_f32:
100 ; CHECK: // %bb.0:
101 ; CHECK-NEXT: fcvtzu x8, s0
102 ; CHECK-NEXT: mov x9, #1125899906842623 // =0x3ffffffffffff
103 ; CHECK-NEXT: cmp x8, x9
104 ; CHECK-NEXT: csel x0, x8, x9, lo
105 ; CHECK-NEXT: ret
106 %x = call i50 @llvm.fptoui.sat.i50.f32(float %f)
107 ret i50 %x
108 }
110 define i64 @test_unsigned_i64_f32(float %f) nounwind {
111 ; CHECK-LABEL: test_unsigned_i64_f32:
112 ; CHECK: // %bb.0:
113 ; CHECK-NEXT: fcvtzu x0, s0
114 ; CHECK-NEXT: ret
115 %x = call i64 @llvm.fptoui.sat.i64.f32(float %f)
116 ret i64 %x
117 }
119 define i100 @test_unsigned_i100_f32(float %f) nounwind {
120 ; CHECK-SD-LABEL: test_unsigned_i100_f32:
121 ; CHECK-SD: // %bb.0:
122 ; CHECK-SD-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
123 ; CHECK-SD-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
124 ; CHECK-SD-NEXT: fmov s8, s0
125 ; CHECK-SD-NEXT: bl __fixunssfti
126 ; CHECK-SD-NEXT: mov w8, #1904214015 // =0x717fffff
127 ; CHECK-SD-NEXT: fcmp s8, #0.0
128 ; CHECK-SD-NEXT: mov x10, #68719476735 // =0xfffffffff
129 ; CHECK-SD-NEXT: fmov s0, w8
130 ; CHECK-SD-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
131 ; CHECK-SD-NEXT: csel x8, xzr, x0, lt
132 ; CHECK-SD-NEXT: csel x9, xzr, x1, lt
133 ; CHECK-SD-NEXT: fcmp s8, s0
134 ; CHECK-SD-NEXT: csel x1, x10, x9, gt
135 ; CHECK-SD-NEXT: csinv x0, x8, xzr, le
136 ; CHECK-SD-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
137 ; CHECK-SD-NEXT: ret
138 ;
139 ; CHECK-GI-LABEL: test_unsigned_i100_f32:
140 ; CHECK-GI: // %bb.0:
141 ; CHECK-GI-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
142 ; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
143 ; CHECK-GI-NEXT: fmov s8, s0
144 ; CHECK-GI-NEXT: bl __fixunssfti
145 ; CHECK-GI-NEXT: mov w8, #1904214015 // =0x717fffff
146 ; CHECK-GI-NEXT: fcmp s8, #0.0
147 ; CHECK-GI-NEXT: mov x10, #68719476735 // =0xfffffffff
148 ; CHECK-GI-NEXT: fmov s0, w8
149 ; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
150 ; CHECK-GI-NEXT: csel x8, xzr, x0, lt
151 ; CHECK-GI-NEXT: csel x9, xzr, x1, lt
152 ; CHECK-GI-NEXT: fcmp s8, s0
153 ; CHECK-GI-NEXT: csinv x0, x8, xzr, le
154 ; CHECK-GI-NEXT: csel x1, x10, x9, gt
155 ; CHECK-GI-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
156 ; CHECK-GI-NEXT: ret
157 %x = call i100 @llvm.fptoui.sat.i100.f32(float %f)
158 ret i100 %x
159 }
161 define i128 @test_unsigned_i128_f32(float %f) nounwind {
162 ; CHECK-SD-LABEL: test_unsigned_i128_f32:
163 ; CHECK-SD: // %bb.0:
164 ; CHECK-SD-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
165 ; CHECK-SD-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
166 ; CHECK-SD-NEXT: fmov s8, s0
167 ; CHECK-SD-NEXT: bl __fixunssfti
168 ; CHECK-SD-NEXT: mov w8, #2139095039 // =0x7f7fffff
169 ; CHECK-SD-NEXT: fcmp s8, #0.0
170 ; CHECK-SD-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
171 ; CHECK-SD-NEXT: fmov s0, w8
172 ; CHECK-SD-NEXT: csel x8, xzr, x1, lt
173 ; CHECK-SD-NEXT: csel x9, xzr, x0, lt
174 ; CHECK-SD-NEXT: fcmp s8, s0
175 ; CHECK-SD-NEXT: csinv x0, x9, xzr, le
176 ; CHECK-SD-NEXT: csinv x1, x8, xzr, le
177 ; CHECK-SD-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
178 ; CHECK-SD-NEXT: ret
179 ;
180 ; CHECK-GI-LABEL: test_unsigned_i128_f32:
181 ; CHECK-GI: // %bb.0:
182 ; CHECK-GI-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
183 ; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
184 ; CHECK-GI-NEXT: fmov s8, s0
185 ; CHECK-GI-NEXT: bl __fixunssfti
186 ; CHECK-GI-NEXT: mov w8, #2139095039 // =0x7f7fffff
187 ; CHECK-GI-NEXT: fcmp s8, #0.0
188 ; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
189 ; CHECK-GI-NEXT: fmov s0, w8
190 ; CHECK-GI-NEXT: csel x8, xzr, x0, lt
191 ; CHECK-GI-NEXT: csel x9, xzr, x1, lt
192 ; CHECK-GI-NEXT: fcmp s8, s0
193 ; CHECK-GI-NEXT: csinv x0, x8, xzr, le
194 ; CHECK-GI-NEXT: csinv x1, x9, xzr, le
195 ; CHECK-GI-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
196 ; CHECK-GI-NEXT: ret
197 %x = call i128 @llvm.fptoui.sat.i128.f32(float %f)
198 ret i128 %x
199 }
201 ;
202 ; 64-bit float to unsigned integer
203 ;
205 declare i1 @llvm.fptoui.sat.i1.f64 (double)
206 declare i8 @llvm.fptoui.sat.i8.f64 (double)
207 declare i13 @llvm.fptoui.sat.i13.f64 (double)
208 declare i16 @llvm.fptoui.sat.i16.f64 (double)
209 declare i19 @llvm.fptoui.sat.i19.f64 (double)
210 declare i32 @llvm.fptoui.sat.i32.f64 (double)
211 declare i50 @llvm.fptoui.sat.i50.f64 (double)
212 declare i64 @llvm.fptoui.sat.i64.f64 (double)
213 declare i100 @llvm.fptoui.sat.i100.f64(double)
214 declare i128 @llvm.fptoui.sat.i128.f64(double)
216 define i1 @test_unsigned_i1_f64(double %f) nounwind {
217 ; CHECK-SD-LABEL: test_unsigned_i1_f64:
218 ; CHECK-SD: // %bb.0:
219 ; CHECK-SD-NEXT: fcvtzu w8, d0
220 ; CHECK-SD-NEXT: cmp w8, #1
221 ; CHECK-SD-NEXT: csinc w0, w8, wzr, lo
222 ; CHECK-SD-NEXT: ret
223 ;
224 ; CHECK-GI-LABEL: test_unsigned_i1_f64:
225 ; CHECK-GI: // %bb.0:
226 ; CHECK-GI-NEXT: fcvtzu w8, d0
227 ; CHECK-GI-NEXT: cmp w8, #1
228 ; CHECK-GI-NEXT: csinc w8, w8, wzr, lo
229 ; CHECK-GI-NEXT: and w0, w8, #0x1
230 ; CHECK-GI-NEXT: ret
231 %x = call i1 @llvm.fptoui.sat.i1.f64(double %f)
232 ret i1 %x
233 }
235 define i8 @test_unsigned_i8_f64(double %f) nounwind {
236 ; CHECK-LABEL: test_unsigned_i8_f64:
237 ; CHECK: // %bb.0:
238 ; CHECK-NEXT: fcvtzu w9, d0
239 ; CHECK-NEXT: mov w8, #255 // =0xff
240 ; CHECK-NEXT: cmp w9, #255
241 ; CHECK-NEXT: csel w0, w9, w8, lo
242 ; CHECK-NEXT: ret
243 %x = call i8 @llvm.fptoui.sat.i8.f64(double %f)
244 ret i8 %x
245 }
247 define i13 @test_unsigned_i13_f64(double %f) nounwind {
248 ; CHECK-LABEL: test_unsigned_i13_f64:
249 ; CHECK: // %bb.0:
250 ; CHECK-NEXT: fcvtzu w8, d0
251 ; CHECK-NEXT: mov w9, #8191 // =0x1fff
252 ; CHECK-NEXT: cmp w8, w9
253 ; CHECK-NEXT: csel w0, w8, w9, lo
254 ; CHECK-NEXT: ret
255 %x = call i13 @llvm.fptoui.sat.i13.f64(double %f)
256 ret i13 %x
257 }
259 define i16 @test_unsigned_i16_f64(double %f) nounwind {
260 ; CHECK-LABEL: test_unsigned_i16_f64:
261 ; CHECK: // %bb.0:
262 ; CHECK-NEXT: fcvtzu w8, d0
263 ; CHECK-NEXT: mov w9, #65535 // =0xffff
264 ; CHECK-NEXT: cmp w8, w9
265 ; CHECK-NEXT: csel w0, w8, w9, lo
266 ; CHECK-NEXT: ret
267 %x = call i16 @llvm.fptoui.sat.i16.f64(double %f)
268 ret i16 %x
269 }
271 define i19 @test_unsigned_i19_f64(double %f) nounwind {
272 ; CHECK-LABEL: test_unsigned_i19_f64:
273 ; CHECK: // %bb.0:
274 ; CHECK-NEXT: fcvtzu w8, d0
275 ; CHECK-NEXT: mov w9, #524287 // =0x7ffff
276 ; CHECK-NEXT: cmp w8, w9
277 ; CHECK-NEXT: csel w0, w8, w9, lo
278 ; CHECK-NEXT: ret
279 %x = call i19 @llvm.fptoui.sat.i19.f64(double %f)
280 ret i19 %x
281 }
283 define i32 @test_unsigned_i32_f64(double %f) nounwind {
284 ; CHECK-LABEL: test_unsigned_i32_f64:
285 ; CHECK: // %bb.0:
286 ; CHECK-NEXT: fcvtzu w0, d0
287 ; CHECK-NEXT: ret
288 %x = call i32 @llvm.fptoui.sat.i32.f64(double %f)
289 ret i32 %x
290 }
292 define i50 @test_unsigned_i50_f64(double %f) nounwind {
293 ; CHECK-LABEL: test_unsigned_i50_f64:
294 ; CHECK: // %bb.0:
295 ; CHECK-NEXT: fcvtzu x8, d0
296 ; CHECK-NEXT: mov x9, #1125899906842623 // =0x3ffffffffffff
297 ; CHECK-NEXT: cmp x8, x9
298 ; CHECK-NEXT: csel x0, x8, x9, lo
299 ; CHECK-NEXT: ret
300 %x = call i50 @llvm.fptoui.sat.i50.f64(double %f)
301 ret i50 %x
302 }
304 define i64 @test_unsigned_i64_f64(double %f) nounwind {
305 ; CHECK-LABEL: test_unsigned_i64_f64:
306 ; CHECK: // %bb.0:
307 ; CHECK-NEXT: fcvtzu x0, d0
308 ; CHECK-NEXT: ret
309 %x = call i64 @llvm.fptoui.sat.i64.f64(double %f)
310 ret i64 %x
311 }
313 define i100 @test_unsigned_i100_f64(double %f) nounwind {
314 ; CHECK-SD-LABEL: test_unsigned_i100_f64:
315 ; CHECK-SD: // %bb.0:
316 ; CHECK-SD-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
317 ; CHECK-SD-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
318 ; CHECK-SD-NEXT: fmov d8, d0
319 ; CHECK-SD-NEXT: bl __fixunsdfti
320 ; CHECK-SD-NEXT: mov x8, #5057542381537067007 // =0x462fffffffffffff
321 ; CHECK-SD-NEXT: fcmp d8, #0.0
322 ; CHECK-SD-NEXT: mov x10, #68719476735 // =0xfffffffff
323 ; CHECK-SD-NEXT: fmov d0, x8
324 ; CHECK-SD-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
325 ; CHECK-SD-NEXT: csel x8, xzr, x0, lt
326 ; CHECK-SD-NEXT: csel x9, xzr, x1, lt
327 ; CHECK-SD-NEXT: fcmp d8, d0
328 ; CHECK-SD-NEXT: csel x1, x10, x9, gt
329 ; CHECK-SD-NEXT: csinv x0, x8, xzr, le
330 ; CHECK-SD-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
331 ; CHECK-SD-NEXT: ret
332 ;
333 ; CHECK-GI-LABEL: test_unsigned_i100_f64:
334 ; CHECK-GI: // %bb.0:
335 ; CHECK-GI-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
336 ; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
337 ; CHECK-GI-NEXT: fmov d8, d0
338 ; CHECK-GI-NEXT: bl __fixunsdfti
339 ; CHECK-GI-NEXT: mov x8, #5057542381537067007 // =0x462fffffffffffff
340 ; CHECK-GI-NEXT: fcmp d8, #0.0
341 ; CHECK-GI-NEXT: mov x10, #68719476735 // =0xfffffffff
342 ; CHECK-GI-NEXT: fmov d0, x8
343 ; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
344 ; CHECK-GI-NEXT: csel x8, xzr, x0, lt
345 ; CHECK-GI-NEXT: csel x9, xzr, x1, lt
346 ; CHECK-GI-NEXT: fcmp d8, d0
347 ; CHECK-GI-NEXT: csinv x0, x8, xzr, le
348 ; CHECK-GI-NEXT: csel x1, x10, x9, gt
349 ; CHECK-GI-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
350 ; CHECK-GI-NEXT: ret
351 %x = call i100 @llvm.fptoui.sat.i100.f64(double %f)
352 ret i100 %x
353 }
355 define i128 @test_unsigned_i128_f64(double %f) nounwind {
356 ; CHECK-SD-LABEL: test_unsigned_i128_f64:
357 ; CHECK-SD: // %bb.0:
358 ; CHECK-SD-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
359 ; CHECK-SD-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
360 ; CHECK-SD-NEXT: fmov d8, d0
361 ; CHECK-SD-NEXT: bl __fixunsdfti
362 ; CHECK-SD-NEXT: mov x8, #5183643171103440895 // =0x47efffffffffffff
363 ; CHECK-SD-NEXT: fcmp d8, #0.0
364 ; CHECK-SD-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
365 ; CHECK-SD-NEXT: fmov d0, x8
366 ; CHECK-SD-NEXT: csel x8, xzr, x1, lt
367 ; CHECK-SD-NEXT: csel x9, xzr, x0, lt
368 ; CHECK-SD-NEXT: fcmp d8, d0
369 ; CHECK-SD-NEXT: csinv x0, x9, xzr, le
370 ; CHECK-SD-NEXT: csinv x1, x8, xzr, le
371 ; CHECK-SD-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
372 ; CHECK-SD-NEXT: ret
373 ;
374 ; CHECK-GI-LABEL: test_unsigned_i128_f64:
375 ; CHECK-GI: // %bb.0:
376 ; CHECK-GI-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
377 ; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
378 ; CHECK-GI-NEXT: fmov d8, d0
379 ; CHECK-GI-NEXT: bl __fixunsdfti
380 ; CHECK-GI-NEXT: mov x8, #5183643171103440895 // =0x47efffffffffffff
381 ; CHECK-GI-NEXT: fcmp d8, #0.0
382 ; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
383 ; CHECK-GI-NEXT: fmov d0, x8
384 ; CHECK-GI-NEXT: csel x8, xzr, x0, lt
385 ; CHECK-GI-NEXT: csel x9, xzr, x1, lt
386 ; CHECK-GI-NEXT: fcmp d8, d0
387 ; CHECK-GI-NEXT: csinv x0, x8, xzr, le
388 ; CHECK-GI-NEXT: csinv x1, x9, xzr, le
389 ; CHECK-GI-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
390 ; CHECK-GI-NEXT: ret
391 %x = call i128 @llvm.fptoui.sat.i128.f64(double %f)
392 ret i128 %x
393 }
395 ;
396 ; 16-bit float to unsigned integer
397 ;
399 declare i1 @llvm.fptoui.sat.i1.f16 (half)
400 declare i8 @llvm.fptoui.sat.i8.f16 (half)
401 declare i13 @llvm.fptoui.sat.i13.f16 (half)
402 declare i16 @llvm.fptoui.sat.i16.f16 (half)
403 declare i19 @llvm.fptoui.sat.i19.f16 (half)
404 declare i32 @llvm.fptoui.sat.i32.f16 (half)
405 declare i50 @llvm.fptoui.sat.i50.f16 (half)
406 declare i64 @llvm.fptoui.sat.i64.f16 (half)
407 declare i100 @llvm.fptoui.sat.i100.f16(half)
408 declare i128 @llvm.fptoui.sat.i128.f16(half)
410 define i1 @test_unsigned_i1_f16(half %f) nounwind {
411 ; CHECK-SD-CVT-LABEL: test_unsigned_i1_f16:
412 ; CHECK-SD-CVT: // %bb.0:
413 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
414 ; CHECK-SD-CVT-NEXT: fcvtzu w8, s0
415 ; CHECK-SD-CVT-NEXT: cmp w8, #1
416 ; CHECK-SD-CVT-NEXT: csinc w0, w8, wzr, lo
417 ; CHECK-SD-CVT-NEXT: ret
418 ;
419 ; CHECK-SD-FP16-LABEL: test_unsigned_i1_f16:
420 ; CHECK-SD-FP16: // %bb.0:
421 ; CHECK-SD-FP16-NEXT: fcvtzu w8, h0
422 ; CHECK-SD-FP16-NEXT: cmp w8, #1
423 ; CHECK-SD-FP16-NEXT: csinc w0, w8, wzr, lo
424 ; CHECK-SD-FP16-NEXT: ret
425 ;
426 ; CHECK-GI-CVT-LABEL: test_unsigned_i1_f16:
427 ; CHECK-GI-CVT: // %bb.0:
428 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
429 ; CHECK-GI-CVT-NEXT: fcvtzu w8, s0
430 ; CHECK-GI-CVT-NEXT: cmp w8, #1
431 ; CHECK-GI-CVT-NEXT: csinc w8, w8, wzr, lo
432 ; CHECK-GI-CVT-NEXT: and w0, w8, #0x1
433 ; CHECK-GI-CVT-NEXT: ret
434 ;
435 ; CHECK-GI-FP16-LABEL: test_unsigned_i1_f16:
436 ; CHECK-GI-FP16: // %bb.0:
437 ; CHECK-GI-FP16-NEXT: fcvtzu w8, h0
438 ; CHECK-GI-FP16-NEXT: cmp w8, #1
439 ; CHECK-GI-FP16-NEXT: csinc w8, w8, wzr, lo
440 ; CHECK-GI-FP16-NEXT: and w0, w8, #0x1
441 ; CHECK-GI-FP16-NEXT: ret
442 %x = call i1 @llvm.fptoui.sat.i1.f16(half %f)
443 ret i1 %x
444 }
446 define i8 @test_unsigned_i8_f16(half %f) nounwind {
447 ; CHECK-SD-CVT-LABEL: test_unsigned_i8_f16:
448 ; CHECK-SD-CVT: // %bb.0:
449 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
450 ; CHECK-SD-CVT-NEXT: mov w8, #255 // =0xff
451 ; CHECK-SD-CVT-NEXT: fcvtzu w9, s0
452 ; CHECK-SD-CVT-NEXT: cmp w9, #255
453 ; CHECK-SD-CVT-NEXT: csel w0, w9, w8, lo
454 ; CHECK-SD-CVT-NEXT: ret
455 ;
456 ; CHECK-SD-FP16-LABEL: test_unsigned_i8_f16:
457 ; CHECK-SD-FP16: // %bb.0:
458 ; CHECK-SD-FP16-NEXT: fcvtzu w9, h0
459 ; CHECK-SD-FP16-NEXT: mov w8, #255 // =0xff
460 ; CHECK-SD-FP16-NEXT: cmp w9, #255
461 ; CHECK-SD-FP16-NEXT: csel w0, w9, w8, lo
462 ; CHECK-SD-FP16-NEXT: ret
463 ;
464 ; CHECK-GI-CVT-LABEL: test_unsigned_i8_f16:
465 ; CHECK-GI-CVT: // %bb.0:
466 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
467 ; CHECK-GI-CVT-NEXT: mov w8, #255 // =0xff
468 ; CHECK-GI-CVT-NEXT: fcvtzu w9, s0
469 ; CHECK-GI-CVT-NEXT: cmp w9, #255
470 ; CHECK-GI-CVT-NEXT: csel w0, w9, w8, lo
471 ; CHECK-GI-CVT-NEXT: ret
472 ;
473 ; CHECK-GI-FP16-LABEL: test_unsigned_i8_f16:
474 ; CHECK-GI-FP16: // %bb.0:
475 ; CHECK-GI-FP16-NEXT: fcvtzu w9, h0
476 ; CHECK-GI-FP16-NEXT: mov w8, #255 // =0xff
477 ; CHECK-GI-FP16-NEXT: cmp w9, #255
478 ; CHECK-GI-FP16-NEXT: csel w0, w9, w8, lo
479 ; CHECK-GI-FP16-NEXT: ret
480 %x = call i8 @llvm.fptoui.sat.i8.f16(half %f)
481 ret i8 %x
482 }
484 define i13 @test_unsigned_i13_f16(half %f) nounwind {
485 ; CHECK-SD-CVT-LABEL: test_unsigned_i13_f16:
486 ; CHECK-SD-CVT: // %bb.0:
487 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
488 ; CHECK-SD-CVT-NEXT: mov w9, #8191 // =0x1fff
489 ; CHECK-SD-CVT-NEXT: fcvtzu w8, s0
490 ; CHECK-SD-CVT-NEXT: cmp w8, w9
491 ; CHECK-SD-CVT-NEXT: csel w0, w8, w9, lo
492 ; CHECK-SD-CVT-NEXT: ret
493 ;
494 ; CHECK-SD-FP16-LABEL: test_unsigned_i13_f16:
495 ; CHECK-SD-FP16: // %bb.0:
496 ; CHECK-SD-FP16-NEXT: fcvtzu w8, h0
497 ; CHECK-SD-FP16-NEXT: mov w9, #8191 // =0x1fff
498 ; CHECK-SD-FP16-NEXT: cmp w8, w9
499 ; CHECK-SD-FP16-NEXT: csel w0, w8, w9, lo
500 ; CHECK-SD-FP16-NEXT: ret
501 ;
502 ; CHECK-GI-CVT-LABEL: test_unsigned_i13_f16:
503 ; CHECK-GI-CVT: // %bb.0:
504 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
505 ; CHECK-GI-CVT-NEXT: mov w9, #8191 // =0x1fff
506 ; CHECK-GI-CVT-NEXT: fcvtzu w8, s0
507 ; CHECK-GI-CVT-NEXT: cmp w8, w9
508 ; CHECK-GI-CVT-NEXT: csel w0, w8, w9, lo
509 ; CHECK-GI-CVT-NEXT: ret
510 ;
511 ; CHECK-GI-FP16-LABEL: test_unsigned_i13_f16:
512 ; CHECK-GI-FP16: // %bb.0:
513 ; CHECK-GI-FP16-NEXT: fcvtzu w8, h0
514 ; CHECK-GI-FP16-NEXT: mov w9, #8191 // =0x1fff
515 ; CHECK-GI-FP16-NEXT: cmp w8, w9
516 ; CHECK-GI-FP16-NEXT: csel w0, w8, w9, lo
517 ; CHECK-GI-FP16-NEXT: ret
518 %x = call i13 @llvm.fptoui.sat.i13.f16(half %f)
519 ret i13 %x
520 }
522 define i16 @test_unsigned_i16_f16(half %f) nounwind {
523 ; CHECK-SD-CVT-LABEL: test_unsigned_i16_f16:
524 ; CHECK-SD-CVT: // %bb.0:
525 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
526 ; CHECK-SD-CVT-NEXT: mov w9, #65535 // =0xffff
527 ; CHECK-SD-CVT-NEXT: fcvtzu w8, s0
528 ; CHECK-SD-CVT-NEXT: cmp w8, w9
529 ; CHECK-SD-CVT-NEXT: csel w0, w8, w9, lo
530 ; CHECK-SD-CVT-NEXT: ret
531 ;
532 ; CHECK-SD-FP16-LABEL: test_unsigned_i16_f16:
533 ; CHECK-SD-FP16: // %bb.0:
534 ; CHECK-SD-FP16-NEXT: fcvtzu w8, h0
535 ; CHECK-SD-FP16-NEXT: mov w9, #65535 // =0xffff
536 ; CHECK-SD-FP16-NEXT: cmp w8, w9
537 ; CHECK-SD-FP16-NEXT: csel w0, w8, w9, lo
538 ; CHECK-SD-FP16-NEXT: ret
539 ;
540 ; CHECK-GI-CVT-LABEL: test_unsigned_i16_f16:
541 ; CHECK-GI-CVT: // %bb.0:
542 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
543 ; CHECK-GI-CVT-NEXT: mov w9, #65535 // =0xffff
544 ; CHECK-GI-CVT-NEXT: fcvtzu w8, s0
545 ; CHECK-GI-CVT-NEXT: cmp w8, w9
546 ; CHECK-GI-CVT-NEXT: csel w0, w8, w9, lo
547 ; CHECK-GI-CVT-NEXT: ret
548 ;
549 ; CHECK-GI-FP16-LABEL: test_unsigned_i16_f16:
550 ; CHECK-GI-FP16: // %bb.0:
551 ; CHECK-GI-FP16-NEXT: fcvtzu w8, h0
552 ; CHECK-GI-FP16-NEXT: mov w9, #65535 // =0xffff
553 ; CHECK-GI-FP16-NEXT: cmp w8, w9
554 ; CHECK-GI-FP16-NEXT: csel w0, w8, w9, lo
555 ; CHECK-GI-FP16-NEXT: ret
556 %x = call i16 @llvm.fptoui.sat.i16.f16(half %f)
557 ret i16 %x
558 }
560 define i19 @test_unsigned_i19_f16(half %f) nounwind {
561 ; CHECK-SD-CVT-LABEL: test_unsigned_i19_f16:
562 ; CHECK-SD-CVT: // %bb.0:
563 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
564 ; CHECK-SD-CVT-NEXT: mov w9, #524287 // =0x7ffff
565 ; CHECK-SD-CVT-NEXT: fcvtzu w8, s0
566 ; CHECK-SD-CVT-NEXT: cmp w8, w9
567 ; CHECK-SD-CVT-NEXT: csel w0, w8, w9, lo
568 ; CHECK-SD-CVT-NEXT: ret
569 ;
570 ; CHECK-SD-FP16-LABEL: test_unsigned_i19_f16:
571 ; CHECK-SD-FP16: // %bb.0:
572 ; CHECK-SD-FP16-NEXT: fcvtzu w8, h0
573 ; CHECK-SD-FP16-NEXT: mov w9, #524287 // =0x7ffff
574 ; CHECK-SD-FP16-NEXT: cmp w8, w9
575 ; CHECK-SD-FP16-NEXT: csel w0, w8, w9, lo
576 ; CHECK-SD-FP16-NEXT: ret
577 ;
578 ; CHECK-GI-CVT-LABEL: test_unsigned_i19_f16:
579 ; CHECK-GI-CVT: // %bb.0:
580 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
581 ; CHECK-GI-CVT-NEXT: mov w9, #524287 // =0x7ffff
582 ; CHECK-GI-CVT-NEXT: fcvtzu w8, s0
583 ; CHECK-GI-CVT-NEXT: cmp w8, w9
584 ; CHECK-GI-CVT-NEXT: csel w0, w8, w9, lo
585 ; CHECK-GI-CVT-NEXT: ret
586 ;
587 ; CHECK-GI-FP16-LABEL: test_unsigned_i19_f16:
588 ; CHECK-GI-FP16: // %bb.0:
589 ; CHECK-GI-FP16-NEXT: fcvtzu w8, h0
590 ; CHECK-GI-FP16-NEXT: mov w9, #524287 // =0x7ffff
591 ; CHECK-GI-FP16-NEXT: cmp w8, w9
592 ; CHECK-GI-FP16-NEXT: csel w0, w8, w9, lo
593 ; CHECK-GI-FP16-NEXT: ret
594 %x = call i19 @llvm.fptoui.sat.i19.f16(half %f)
595 ret i19 %x
596 }
598 define i32 @test_unsigned_i32_f16(half %f) nounwind {
599 ; CHECK-SD-CVT-LABEL: test_unsigned_i32_f16:
600 ; CHECK-SD-CVT: // %bb.0:
601 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
602 ; CHECK-SD-CVT-NEXT: fcvtzu w0, s0
603 ; CHECK-SD-CVT-NEXT: ret
604 ;
605 ; CHECK-SD-FP16-LABEL: test_unsigned_i32_f16:
606 ; CHECK-SD-FP16: // %bb.0:
607 ; CHECK-SD-FP16-NEXT: fcvtzu w0, h0
608 ; CHECK-SD-FP16-NEXT: ret
609 ;
610 ; CHECK-GI-CVT-LABEL: test_unsigned_i32_f16:
611 ; CHECK-GI-CVT: // %bb.0:
612 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
613 ; CHECK-GI-CVT-NEXT: fcvtzu w0, s0
614 ; CHECK-GI-CVT-NEXT: ret
615 ;
616 ; CHECK-GI-FP16-LABEL: test_unsigned_i32_f16:
617 ; CHECK-GI-FP16: // %bb.0:
618 ; CHECK-GI-FP16-NEXT: fcvtzu w0, h0
619 ; CHECK-GI-FP16-NEXT: ret
620 %x = call i32 @llvm.fptoui.sat.i32.f16(half %f)
621 ret i32 %x
622 }
624 define i50 @test_unsigned_i50_f16(half %f) nounwind {
625 ; CHECK-SD-CVT-LABEL: test_unsigned_i50_f16:
626 ; CHECK-SD-CVT: // %bb.0:
627 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
628 ; CHECK-SD-CVT-NEXT: mov x9, #1125899906842623 // =0x3ffffffffffff
629 ; CHECK-SD-CVT-NEXT: fcvtzu x8, s0
630 ; CHECK-SD-CVT-NEXT: cmp x8, x9
631 ; CHECK-SD-CVT-NEXT: csel x0, x8, x9, lo
632 ; CHECK-SD-CVT-NEXT: ret
633 ;
634 ; CHECK-SD-FP16-LABEL: test_unsigned_i50_f16:
635 ; CHECK-SD-FP16: // %bb.0:
636 ; CHECK-SD-FP16-NEXT: fcvtzu x8, h0
637 ; CHECK-SD-FP16-NEXT: mov x9, #1125899906842623 // =0x3ffffffffffff
638 ; CHECK-SD-FP16-NEXT: cmp x8, x9
639 ; CHECK-SD-FP16-NEXT: csel x0, x8, x9, lo
640 ; CHECK-SD-FP16-NEXT: ret
641 ;
642 ; CHECK-GI-CVT-LABEL: test_unsigned_i50_f16:
643 ; CHECK-GI-CVT: // %bb.0:
644 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
645 ; CHECK-GI-CVT-NEXT: mov x9, #1125899906842623 // =0x3ffffffffffff
646 ; CHECK-GI-CVT-NEXT: fcvtzu x8, s0
647 ; CHECK-GI-CVT-NEXT: cmp x8, x9
648 ; CHECK-GI-CVT-NEXT: csel x0, x8, x9, lo
649 ; CHECK-GI-CVT-NEXT: ret
650 ;
651 ; CHECK-GI-FP16-LABEL: test_unsigned_i50_f16:
652 ; CHECK-GI-FP16: // %bb.0:
653 ; CHECK-GI-FP16-NEXT: fcvtzu x8, h0
654 ; CHECK-GI-FP16-NEXT: mov x9, #1125899906842623 // =0x3ffffffffffff
655 ; CHECK-GI-FP16-NEXT: cmp x8, x9
656 ; CHECK-GI-FP16-NEXT: csel x0, x8, x9, lo
657 ; CHECK-GI-FP16-NEXT: ret
658 %x = call i50 @llvm.fptoui.sat.i50.f16(half %f)
659 ret i50 %x
660 }
662 define i64 @test_unsigned_i64_f16(half %f) nounwind {
663 ; CHECK-SD-CVT-LABEL: test_unsigned_i64_f16:
664 ; CHECK-SD-CVT: // %bb.0:
665 ; CHECK-SD-CVT-NEXT: fcvt s0, h0
666 ; CHECK-SD-CVT-NEXT: fcvtzu x0, s0
667 ; CHECK-SD-CVT-NEXT: ret
668 ;
669 ; CHECK-SD-FP16-LABEL: test_unsigned_i64_f16:
670 ; CHECK-SD-FP16: // %bb.0:
671 ; CHECK-SD-FP16-NEXT: fcvtzu x0, h0
672 ; CHECK-SD-FP16-NEXT: ret
673 ;
674 ; CHECK-GI-CVT-LABEL: test_unsigned_i64_f16:
675 ; CHECK-GI-CVT: // %bb.0:
676 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
677 ; CHECK-GI-CVT-NEXT: fcvtzu x0, s0
678 ; CHECK-GI-CVT-NEXT: ret
679 ;
680 ; CHECK-GI-FP16-LABEL: test_unsigned_i64_f16:
681 ; CHECK-GI-FP16: // %bb.0:
682 ; CHECK-GI-FP16-NEXT: fcvtzu x0, h0
683 ; CHECK-GI-FP16-NEXT: ret
684 %x = call i64 @llvm.fptoui.sat.i64.f16(half %f)
685 ret i64 %x
686 }
688 define i100 @test_unsigned_i100_f16(half %f) nounwind {
689 ; CHECK-SD-LABEL: test_unsigned_i100_f16:
690 ; CHECK-SD: // %bb.0:
691 ; CHECK-SD-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
692 ; CHECK-SD-NEXT: fcvt s8, h0
693 ; CHECK-SD-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
694 ; CHECK-SD-NEXT: fmov s0, s8
695 ; CHECK-SD-NEXT: bl __fixunssfti
696 ; CHECK-SD-NEXT: mov w8, #1904214015 // =0x717fffff
697 ; CHECK-SD-NEXT: fcmp s8, #0.0
698 ; CHECK-SD-NEXT: mov x10, #68719476735 // =0xfffffffff
699 ; CHECK-SD-NEXT: fmov s0, w8
700 ; CHECK-SD-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
701 ; CHECK-SD-NEXT: csel x8, xzr, x0, lt
702 ; CHECK-SD-NEXT: csel x9, xzr, x1, lt
703 ; CHECK-SD-NEXT: fcmp s8, s0
704 ; CHECK-SD-NEXT: csel x1, x10, x9, gt
705 ; CHECK-SD-NEXT: csinv x0, x8, xzr, le
706 ; CHECK-SD-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
707 ; CHECK-SD-NEXT: ret
708 ;
709 ; CHECK-GI-CVT-LABEL: test_unsigned_i100_f16:
710 ; CHECK-GI-CVT: // %bb.0:
711 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
712 ; CHECK-GI-CVT-NEXT: mov x1, xzr
713 ; CHECK-GI-CVT-NEXT: fcvtzu x0, s0
714 ; CHECK-GI-CVT-NEXT: ret
715 ;
716 ; CHECK-GI-FP16-LABEL: test_unsigned_i100_f16:
717 ; CHECK-GI-FP16: // %bb.0:
718 ; CHECK-GI-FP16-NEXT: fcvtzu x0, h0
719 ; CHECK-GI-FP16-NEXT: mov x1, xzr
720 ; CHECK-GI-FP16-NEXT: ret
721 %x = call i100 @llvm.fptoui.sat.i100.f16(half %f)
722 ret i100 %x
723 }
725 define i128 @test_unsigned_i128_f16(half %f) nounwind {
726 ; CHECK-SD-LABEL: test_unsigned_i128_f16:
727 ; CHECK-SD: // %bb.0:
728 ; CHECK-SD-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
729 ; CHECK-SD-NEXT: fcvt s8, h0
730 ; CHECK-SD-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
731 ; CHECK-SD-NEXT: fmov s0, s8
732 ; CHECK-SD-NEXT: bl __fixunssfti
733 ; CHECK-SD-NEXT: mov w8, #2139095039 // =0x7f7fffff
734 ; CHECK-SD-NEXT: fcmp s8, #0.0
735 ; CHECK-SD-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
736 ; CHECK-SD-NEXT: fmov s0, w8
737 ; CHECK-SD-NEXT: csel x8, xzr, x1, lt
738 ; CHECK-SD-NEXT: csel x9, xzr, x0, lt
739 ; CHECK-SD-NEXT: fcmp s8, s0
740 ; CHECK-SD-NEXT: csinv x0, x9, xzr, le
741 ; CHECK-SD-NEXT: csinv x1, x8, xzr, le
742 ; CHECK-SD-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
743 ; CHECK-SD-NEXT: ret
744 ;
745 ; CHECK-GI-CVT-LABEL: test_unsigned_i128_f16:
746 ; CHECK-GI-CVT: // %bb.0:
747 ; CHECK-GI-CVT-NEXT: fcvt s0, h0
748 ; CHECK-GI-CVT-NEXT: mov x1, xzr
749 ; CHECK-GI-CVT-NEXT: fcvtzu x0, s0
750 ; CHECK-GI-CVT-NEXT: ret
751 ;
752 ; CHECK-GI-FP16-LABEL: test_unsigned_i128_f16:
753 ; CHECK-GI-FP16: // %bb.0:
754 ; CHECK-GI-FP16-NEXT: fcvtzu x0, h0
755 ; CHECK-GI-FP16-NEXT: mov x1, xzr
756 ; CHECK-GI-FP16-NEXT: ret
757 %x = call i128 @llvm.fptoui.sat.i128.f16(half %f)
758 ret i128 %x
759 }
761 define i32 @test_unsigned_f128_i32(fp128 %f) {
762 ; CHECK-SD-LABEL: test_unsigned_f128_i32:
763 ; CHECK-SD: // %bb.0:
764 ; CHECK-SD-NEXT: sub sp, sp, #32
765 ; CHECK-SD-NEXT: stp x30, x19, [sp, #16] // 16-byte Folded Spill
766 ; CHECK-SD-NEXT: .cfi_def_cfa_offset 32
767 ; CHECK-SD-NEXT: .cfi_offset w19, -8
768 ; CHECK-SD-NEXT: .cfi_offset w30, -16
769 ; CHECK-SD-NEXT: adrp x8, .LCPI30_0
770 ; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
771 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI30_0]
772 ; CHECK-SD-NEXT: bl __getf2
773 ; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
774 ; CHECK-SD-NEXT: mov w19, w0
775 ; CHECK-SD-NEXT: bl __fixunstfsi
776 ; CHECK-SD-NEXT: adrp x8, .LCPI30_1
777 ; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
778 ; CHECK-SD-NEXT: cmp w19, #0
779 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
780 ; CHECK-SD-NEXT: csel w19, wzr, w0, lt
781 ; CHECK-SD-NEXT: bl __gttf2
782 ; CHECK-SD-NEXT: cmp w0, #0
783 ; CHECK-SD-NEXT: csinv w0, w19, wzr, le
784 ; CHECK-SD-NEXT: ldp x30, x19, [sp, #16] // 16-byte Folded Reload
785 ; CHECK-SD-NEXT: add sp, sp, #32
786 ; CHECK-SD-NEXT: ret
787 ;
788 ; CHECK-GI-LABEL: test_unsigned_f128_i32:
789 ; CHECK-GI: // %bb.0:
790 ; CHECK-GI-NEXT: sub sp, sp, #48
791 ; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
792 ; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
793 ; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
794 ; CHECK-GI-NEXT: .cfi_offset w19, -8
795 ; CHECK-GI-NEXT: .cfi_offset w20, -16
796 ; CHECK-GI-NEXT: .cfi_offset w30, -32
797 ; CHECK-GI-NEXT: adrp x8, .LCPI30_1
798 ; CHECK-GI-NEXT: str q0, [sp] // 16-byte Folded Spill
799 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
800 ; CHECK-GI-NEXT: bl __getf2
801 ; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Folded Reload
802 ; CHECK-GI-NEXT: cmp w0, #0
803 ; CHECK-GI-NEXT: fmov x8, d0
804 ; CHECK-GI-NEXT: csel x19, x8, xzr, lt
805 ; CHECK-GI-NEXT: mov x8, v0.d[1]
806 ; CHECK-GI-NEXT: mov v0.d[0], x19
807 ; CHECK-GI-NEXT: csel x20, x8, xzr, lt
808 ; CHECK-GI-NEXT: adrp x8, .LCPI30_0
809 ; CHECK-GI-NEXT: mov v0.d[1], x20
810 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_0]
811 ; CHECK-GI-NEXT: bl __gttf2
812 ; CHECK-GI-NEXT: cmp w0, #0
813 ; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
814 ; CHECK-GI-NEXT: csel x8, x19, xzr, gt
815 ; CHECK-GI-NEXT: mov v0.d[0], x8
816 ; CHECK-GI-NEXT: mov x8, #281474976579584 // =0xfffffffe0000
817 ; CHECK-GI-NEXT: movk x8, #16414, lsl #48
818 ; CHECK-GI-NEXT: csel x8, x20, x8, gt
819 ; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
820 ; CHECK-GI-NEXT: mov v0.d[1], x8
821 ; CHECK-GI-NEXT: add sp, sp, #48
822 ; CHECK-GI-NEXT: b __fixunstfsi
823 %x = call i32 @llvm.fptoui.sat.i32.f128(fp128 %f)
824 ret i32 %x
825 }