| blob | f6dbf5251fc27204066b40f12c37c24e5bc5651d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
5 define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) {
6 ; CHECK-LABEL: and8xi8:
7 ; CHECK: // %bb.0:
8 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
9 ; CHECK-NEXT: ret
10 %tmp1 = and <8 x i8> %a, %b;
11 ret <8 x i8> %tmp1
12 }
14 define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) {
15 ; CHECK-LABEL: and16xi8:
16 ; CHECK: // %bb.0:
17 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
18 ; CHECK-NEXT: ret
19 %tmp1 = and <16 x i8> %a, %b;
20 ret <16 x i8> %tmp1
21 }
24 define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) {
25 ; CHECK-LABEL: orr8xi8:
26 ; CHECK: // %bb.0:
27 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
28 ; CHECK-NEXT: ret
29 %tmp1 = or <8 x i8> %a, %b;
30 ret <8 x i8> %tmp1
31 }
33 define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) {
34 ; CHECK-LABEL: orr16xi8:
35 ; CHECK: // %bb.0:
36 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
37 ; CHECK-NEXT: ret
38 %tmp1 = or <16 x i8> %a, %b;
39 ret <16 x i8> %tmp1
40 }
43 define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) {
44 ; CHECK-LABEL: xor8xi8:
45 ; CHECK: // %bb.0:
46 ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
47 ; CHECK-NEXT: ret
48 %tmp1 = xor <8 x i8> %a, %b;
49 ret <8 x i8> %tmp1
50 }
52 define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) {
53 ; CHECK-LABEL: xor16xi8:
54 ; CHECK: // %bb.0:
55 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
56 ; CHECK-NEXT: ret
57 %tmp1 = xor <16 x i8> %a, %b;
58 ret <16 x i8> %tmp1
59 }
61 define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) {
62 ; CHECK-SD-LABEL: bsl8xi8_const:
63 ; CHECK-SD: // %bb.0:
64 ; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
65 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
66 ; CHECK-SD-NEXT: ret
67 ;
68 ; CHECK-GI-LABEL: bsl8xi8_const:
69 ; CHECK-GI: // %bb.0:
70 ; CHECK-GI-NEXT: adrp x8, .LCPI6_0
71 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI6_0]
72 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
73 ; CHECK-GI-NEXT: ret
74 %tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0 >
75 %tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1 >
76 %tmp3 = or <8 x i8> %tmp1, %tmp2
77 ret <8 x i8> %tmp3
78 }
80 define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) {
81 ; CHECK-SD-LABEL: bsl16xi8_const:
82 ; CHECK-SD: // %bb.0:
83 ; CHECK-SD-NEXT: movi v2.2d, #0x000000ffffffff
84 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
85 ; CHECK-SD-NEXT: ret
86 ;
87 ; CHECK-GI-LABEL: bsl16xi8_const:
88 ; CHECK-GI: // %bb.0:
89 ; CHECK-GI-NEXT: adrp x8, .LCPI7_0
90 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI7_0]
91 ; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
92 ; CHECK-GI-NEXT: ret
93 %tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0 >
94 %tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1 >
95 %tmp3 = or <16 x i8> %tmp1, %tmp2
96 ret <16 x i8> %tmp3
97 }
99 define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) {
100 ; CHECK-LABEL: orn8xi8:
101 ; CHECK: // %bb.0:
102 ; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
103 ; CHECK-NEXT: ret
104 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
105 %tmp2 = or <8 x i8> %a, %tmp1
106 ret <8 x i8> %tmp2
107 }
109 define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) {
110 ; CHECK-LABEL: orn16xi8:
111 ; CHECK: // %bb.0:
112 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
113 ; CHECK-NEXT: ret
114 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
115 %tmp2 = or <16 x i8> %a, %tmp1
116 ret <16 x i8> %tmp2
117 }
119 define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) {
120 ; CHECK-LABEL: bic8xi8:
121 ; CHECK: // %bb.0:
122 ; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
123 ; CHECK-NEXT: ret
124 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
125 %tmp2 = and <8 x i8> %a, %tmp1
126 ret <8 x i8> %tmp2
127 }
129 define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) {
130 ; CHECK-LABEL: bic16xi8:
131 ; CHECK: // %bb.0:
132 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
133 ; CHECK-NEXT: ret
134 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
135 %tmp2 = and <16 x i8> %a, %tmp1
136 ret <16 x i8> %tmp2
137 }
139 define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) {
140 ; CHECK-SD-LABEL: orrimm2s_lsl0:
141 ; CHECK-SD: // %bb.0:
142 ; CHECK-SD-NEXT: orr v0.2s, #255
143 ; CHECK-SD-NEXT: ret
144 ;
145 ; CHECK-GI-LABEL: orrimm2s_lsl0:
146 ; CHECK-GI: // %bb.0:
147 ; CHECK-GI-NEXT: movi d1, #0x0000ff000000ff
148 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
149 ; CHECK-GI-NEXT: ret
150 %tmp1 = or <2 x i32> %a, < i32 255, i32 255>
151 ret <2 x i32> %tmp1
152 }
154 define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) {
155 ; CHECK-SD-LABEL: orrimm2s_lsl8:
156 ; CHECK-SD: // %bb.0:
157 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
158 ; CHECK-SD-NEXT: ret
159 ;
160 ; CHECK-GI-LABEL: orrimm2s_lsl8:
161 ; CHECK-GI: // %bb.0:
162 ; CHECK-GI-NEXT: movi d1, #0x00ff000000ff00
163 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
164 ; CHECK-GI-NEXT: ret
165 %tmp1 = or <2 x i32> %a, < i32 65280, i32 65280>
166 ret <2 x i32> %tmp1
167 }
169 define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) {
170 ; CHECK-SD-LABEL: orrimm2s_lsl16:
171 ; CHECK-SD: // %bb.0:
172 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
173 ; CHECK-SD-NEXT: ret
174 ;
175 ; CHECK-GI-LABEL: orrimm2s_lsl16:
176 ; CHECK-GI: // %bb.0:
177 ; CHECK-GI-NEXT: movi d1, #0xff000000ff0000
178 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
179 ; CHECK-GI-NEXT: ret
180 %tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680>
181 ret <2 x i32> %tmp1
182 }
184 define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) {
185 ; CHECK-SD-LABEL: orrimm2s_lsl24:
186 ; CHECK-SD: // %bb.0:
187 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
188 ; CHECK-SD-NEXT: ret
189 ;
190 ; CHECK-GI-LABEL: orrimm2s_lsl24:
191 ; CHECK-GI: // %bb.0:
192 ; CHECK-GI-NEXT: movi d1, #0xff000000ff000000
193 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
194 ; CHECK-GI-NEXT: ret
195 %tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080>
196 ret <2 x i32> %tmp1
197 }
199 define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) {
200 ; CHECK-SD-LABEL: orrimm4s_lsl0:
201 ; CHECK-SD: // %bb.0:
202 ; CHECK-SD-NEXT: orr v0.4s, #255
203 ; CHECK-SD-NEXT: ret
204 ;
205 ; CHECK-GI-LABEL: orrimm4s_lsl0:
206 ; CHECK-GI: // %bb.0:
207 ; CHECK-GI-NEXT: movi v1.2d, #0x0000ff000000ff
208 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
209 ; CHECK-GI-NEXT: ret
210 %tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255>
211 ret <4 x i32> %tmp1
212 }
214 define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) {
215 ; CHECK-SD-LABEL: orrimm4s_lsl8:
216 ; CHECK-SD: // %bb.0:
217 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
218 ; CHECK-SD-NEXT: ret
219 ;
220 ; CHECK-GI-LABEL: orrimm4s_lsl8:
221 ; CHECK-GI: // %bb.0:
222 ; CHECK-GI-NEXT: movi v1.2d, #0x00ff000000ff00
223 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
224 ; CHECK-GI-NEXT: ret
225 %tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280>
226 ret <4 x i32> %tmp1
227 }
229 define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) {
230 ; CHECK-SD-LABEL: orrimm4s_lsl16:
231 ; CHECK-SD: // %bb.0:
232 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
233 ; CHECK-SD-NEXT: ret
234 ;
235 ; CHECK-GI-LABEL: orrimm4s_lsl16:
236 ; CHECK-GI: // %bb.0:
237 ; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff0000
238 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
239 ; CHECK-GI-NEXT: ret
240 %tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680>
241 ret <4 x i32> %tmp1
242 }
244 define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) {
245 ; CHECK-SD-LABEL: orrimm4s_lsl24:
246 ; CHECK-SD: // %bb.0:
247 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
248 ; CHECK-SD-NEXT: ret
249 ;
250 ; CHECK-GI-LABEL: orrimm4s_lsl24:
251 ; CHECK-GI: // %bb.0:
252 ; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff000000
253 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
254 ; CHECK-GI-NEXT: ret
255 %tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080>
256 ret <4 x i32> %tmp1
257 }
259 define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) {
260 ; CHECK-SD-LABEL: orrimm4h_lsl0:
261 ; CHECK-SD: // %bb.0:
262 ; CHECK-SD-NEXT: orr v0.4h, #255
263 ; CHECK-SD-NEXT: ret
264 ;
265 ; CHECK-GI-LABEL: orrimm4h_lsl0:
266 ; CHECK-GI: // %bb.0:
267 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
268 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
269 ; CHECK-GI-NEXT: ret
270 %tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 >
271 ret <4 x i16> %tmp1
272 }
274 define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) {
275 ; CHECK-SD-LABEL: orrimm4h_lsl8:
276 ; CHECK-SD: // %bb.0:
277 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
278 ; CHECK-SD-NEXT: ret
279 ;
280 ; CHECK-GI-LABEL: orrimm4h_lsl8:
281 ; CHECK-GI: // %bb.0:
282 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff00
283 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
284 ; CHECK-GI-NEXT: ret
285 %tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
286 ret <4 x i16> %tmp1
287 }
289 define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) {
290 ; CHECK-SD-LABEL: orrimm8h_lsl0:
291 ; CHECK-SD: // %bb.0:
292 ; CHECK-SD-NEXT: orr v0.8h, #255
293 ; CHECK-SD-NEXT: ret
294 ;
295 ; CHECK-GI-LABEL: orrimm8h_lsl0:
296 ; CHECK-GI: // %bb.0:
297 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
298 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
299 ; CHECK-GI-NEXT: ret
300 %tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
301 ret <8 x i16> %tmp1
302 }
304 define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) {
305 ; CHECK-SD-LABEL: orrimm8h_lsl8:
306 ; CHECK-SD: // %bb.0:
307 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
308 ; CHECK-SD-NEXT: ret
309 ;
310 ; CHECK-GI-LABEL: orrimm8h_lsl8:
311 ; CHECK-GI: // %bb.0:
312 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
313 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
314 ; CHECK-GI-NEXT: ret
315 %tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
316 ret <8 x i16> %tmp1
317 }
319 define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) {
320 ; CHECK-SD-LABEL: bicimm2s_lsl0:
321 ; CHECK-SD: // %bb.0:
322 ; CHECK-SD-NEXT: bic v0.2s, #16
323 ; CHECK-SD-NEXT: ret
324 ;
325 ; CHECK-GI-LABEL: bicimm2s_lsl0:
326 ; CHECK-GI: // %bb.0:
327 ; CHECK-GI-NEXT: mvni v1.2s, #16
328 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
329 ; CHECK-GI-NEXT: ret
330 %tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 >
331 ret <2 x i32> %tmp1
332 }
334 define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) {
335 ; CHECK-SD-LABEL: bicimm2s_lsl8:
336 ; CHECK-SD: // %bb.0:
337 ; CHECK-SD-NEXT: bic v0.2s, #16, lsl #8
338 ; CHECK-SD-NEXT: ret
339 ;
340 ; CHECK-GI-LABEL: bicimm2s_lsl8:
341 ; CHECK-GI: // %bb.0:
342 ; CHECK-GI-NEXT: mvni v1.2s, #16, lsl #8
343 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
344 ; CHECK-GI-NEXT: ret
345 %tmp1 = and <2 x i32> %a, < i32 4294963199, i32 4294963199 >
346 ret <2 x i32> %tmp1
347 }
349 define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) {
350 ; CHECK-SD-LABEL: bicimm2s_lsl16:
351 ; CHECK-SD: // %bb.0:
352 ; CHECK-SD-NEXT: bic v0.2s, #16, lsl #16
353 ; CHECK-SD-NEXT: ret
354 ;
355 ; CHECK-GI-LABEL: bicimm2s_lsl16:
356 ; CHECK-GI: // %bb.0:
357 ; CHECK-GI-NEXT: mvni v1.2s, #16, lsl #16
358 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
359 ; CHECK-GI-NEXT: ret
360 %tmp1 = and <2 x i32> %a, < i32 4293918719, i32 4293918719 >
361 ret <2 x i32> %tmp1
362 }
364 define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) {
365 ; CHECK-SD-LABEL: bicimm2s_lsl124:
366 ; CHECK-SD: // %bb.0:
367 ; CHECK-SD-NEXT: bic v0.2s, #16, lsl #24
368 ; CHECK-SD-NEXT: ret
369 ;
370 ; CHECK-GI-LABEL: bicimm2s_lsl124:
371 ; CHECK-GI: // %bb.0:
372 ; CHECK-GI-NEXT: mvni v1.2s, #16, lsl #24
373 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
374 ; CHECK-GI-NEXT: ret
375 %tmp1 = and <2 x i32> %a, < i32 4026531839, i32 4026531839>
376 ret <2 x i32> %tmp1
377 }
379 define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) {
380 ; CHECK-SD-LABEL: bicimm4s_lsl0:
381 ; CHECK-SD: // %bb.0:
382 ; CHECK-SD-NEXT: bic v0.4s, #16
383 ; CHECK-SD-NEXT: ret
384 ;
385 ; CHECK-GI-LABEL: bicimm4s_lsl0:
386 ; CHECK-GI: // %bb.0:
387 ; CHECK-GI-NEXT: mvni v1.4s, #16
388 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
389 ; CHECK-GI-NEXT: ret
390 %tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
391 ret <4 x i32> %tmp1
392 }
394 define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) {
395 ; CHECK-SD-LABEL: bicimm4s_lsl8:
396 ; CHECK-SD: // %bb.0:
397 ; CHECK-SD-NEXT: bic v0.4s, #16, lsl #8
398 ; CHECK-SD-NEXT: ret
399 ;
400 ; CHECK-GI-LABEL: bicimm4s_lsl8:
401 ; CHECK-GI: // %bb.0:
402 ; CHECK-GI-NEXT: mvni v1.4s, #16, lsl #8
403 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
404 ; CHECK-GI-NEXT: ret
405 %tmp1 = and <4 x i32> %a, < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
406 ret <4 x i32> %tmp1
407 }
409 define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) {
410 ; CHECK-SD-LABEL: bicimm4s_lsl16:
411 ; CHECK-SD: // %bb.0:
412 ; CHECK-SD-NEXT: bic v0.4s, #16, lsl #16
413 ; CHECK-SD-NEXT: ret
414 ;
415 ; CHECK-GI-LABEL: bicimm4s_lsl16:
416 ; CHECK-GI: // %bb.0:
417 ; CHECK-GI-NEXT: mvni v1.4s, #16, lsl #16
418 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
419 ; CHECK-GI-NEXT: ret
420 %tmp1 = and <4 x i32> %a, < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
421 ret <4 x i32> %tmp1
422 }
424 define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) {
425 ; CHECK-SD-LABEL: bicimm4s_lsl124:
426 ; CHECK-SD: // %bb.0:
427 ; CHECK-SD-NEXT: bic v0.4s, #16, lsl #24
428 ; CHECK-SD-NEXT: ret
429 ;
430 ; CHECK-GI-LABEL: bicimm4s_lsl124:
431 ; CHECK-GI: // %bb.0:
432 ; CHECK-GI-NEXT: mvni v1.4s, #16, lsl #24
433 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
434 ; CHECK-GI-NEXT: ret
435 %tmp1 = and <4 x i32> %a, < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839>
436 ret <4 x i32> %tmp1
437 }
439 define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) {
440 ; CHECK-SD-LABEL: bicimm4h_lsl0_a:
441 ; CHECK-SD: // %bb.0:
442 ; CHECK-SD-NEXT: bic v0.4h, #16
443 ; CHECK-SD-NEXT: ret
444 ;
445 ; CHECK-GI-LABEL: bicimm4h_lsl0_a:
446 ; CHECK-GI: // %bb.0:
447 ; CHECK-GI-NEXT: mvni v1.4h, #16
448 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
449 ; CHECK-GI-NEXT: ret
450 %tmp1 = and <4 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
451 ret <4 x i16> %tmp1
452 }
454 define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) {
455 ; CHECK-SD-LABEL: bicimm4h_lsl0_b:
456 ; CHECK-SD: // %bb.0:
457 ; CHECK-SD-NEXT: bic v0.4h, #255
458 ; CHECK-SD-NEXT: ret
459 ;
460 ; CHECK-GI-LABEL: bicimm4h_lsl0_b:
461 ; CHECK-GI: // %bb.0:
462 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff00
463 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
464 ; CHECK-GI-NEXT: ret
465 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
466 ret <4 x i16> %tmp1
467 }
469 define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) {
470 ; CHECK-SD-LABEL: bicimm4h_lsl8_a:
471 ; CHECK-SD: // %bb.0:
472 ; CHECK-SD-NEXT: bic v0.4h, #16, lsl #8
473 ; CHECK-SD-NEXT: ret
474 ;
475 ; CHECK-GI-LABEL: bicimm4h_lsl8_a:
476 ; CHECK-GI: // %bb.0:
477 ; CHECK-GI-NEXT: mvni v1.4h, #16, lsl #8
478 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
479 ; CHECK-GI-NEXT: ret
480 %tmp1 = and <4 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
481 ret <4 x i16> %tmp1
482 }
484 define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) {
485 ; CHECK-SD-LABEL: bicimm4h_lsl8_b:
486 ; CHECK-SD: // %bb.0:
487 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
488 ; CHECK-SD-NEXT: ret
489 ;
490 ; CHECK-GI-LABEL: bicimm4h_lsl8_b:
491 ; CHECK-GI: // %bb.0:
492 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
493 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
494 ; CHECK-GI-NEXT: ret
495 %tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255>
496 ret <4 x i16> %tmp1
497 }
499 define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) {
500 ; CHECK-SD-LABEL: bicimm8h_lsl0_a:
501 ; CHECK-SD: // %bb.0:
502 ; CHECK-SD-NEXT: bic v0.8h, #16
503 ; CHECK-SD-NEXT: ret
504 ;
505 ; CHECK-GI-LABEL: bicimm8h_lsl0_a:
506 ; CHECK-GI: // %bb.0:
507 ; CHECK-GI-NEXT: mvni v1.8h, #16
508 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
509 ; CHECK-GI-NEXT: ret
510 %tmp1 = and <8 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279,
511 i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
512 ret <8 x i16> %tmp1
513 }
515 define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) {
516 ; CHECK-SD-LABEL: bicimm8h_lsl0_b:
517 ; CHECK-SD: // %bb.0:
518 ; CHECK-SD-NEXT: bic v0.8h, #255
519 ; CHECK-SD-NEXT: ret
520 ;
521 ; CHECK-GI-LABEL: bicimm8h_lsl0_b:
522 ; CHECK-GI: // %bb.0:
523 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
524 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
525 ; CHECK-GI-NEXT: ret
526 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
527 ret <8 x i16> %tmp1
528 }
530 define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) {
531 ; CHECK-SD-LABEL: bicimm8h_lsl8_a:
532 ; CHECK-SD: // %bb.0:
533 ; CHECK-SD-NEXT: bic v0.8h, #16, lsl #8
534 ; CHECK-SD-NEXT: ret
535 ;
536 ; CHECK-GI-LABEL: bicimm8h_lsl8_a:
537 ; CHECK-GI: // %bb.0:
538 ; CHECK-GI-NEXT: mvni v1.8h, #16, lsl #8
539 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
540 ; CHECK-GI-NEXT: ret
541 %tmp1 = and <8 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199,
542 i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
543 ret <8 x i16> %tmp1
544 }
546 define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) {
547 ; CHECK-SD-LABEL: bicimm8h_lsl8_b:
548 ; CHECK-SD: // %bb.0:
549 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
550 ; CHECK-SD-NEXT: ret
551 ;
552 ; CHECK-GI-LABEL: bicimm8h_lsl8_b:
553 ; CHECK-GI: // %bb.0:
554 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
555 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
556 ; CHECK-GI-NEXT: ret
557 %tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
558 ret <8 x i16> %tmp1
559 }
561 define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) {
562 ; CHECK-LABEL: and2xi32:
563 ; CHECK: // %bb.0:
564 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
565 ; CHECK-NEXT: ret
566 %tmp1 = and <2 x i32> %a, %b;
567 ret <2 x i32> %tmp1
568 }
570 define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) {
571 ; CHECK-LABEL: and4xi16:
572 ; CHECK: // %bb.0:
573 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
574 ; CHECK-NEXT: ret
575 %tmp1 = and <4 x i16> %a, %b;
576 ret <4 x i16> %tmp1
577 }
579 define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) {
580 ; CHECK-SD-LABEL: and1xi64:
581 ; CHECK-SD: // %bb.0:
582 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
583 ; CHECK-SD-NEXT: ret
584 ;
585 ; CHECK-GI-LABEL: and1xi64:
586 ; CHECK-GI: // %bb.0:
587 ; CHECK-GI-NEXT: fmov x8, d0
588 ; CHECK-GI-NEXT: fmov x9, d1
589 ; CHECK-GI-NEXT: and x8, x8, x9
590 ; CHECK-GI-NEXT: fmov d0, x8
591 ; CHECK-GI-NEXT: ret
592 %tmp1 = and <1 x i64> %a, %b;
593 ret <1 x i64> %tmp1
594 }
596 define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) {
597 ; CHECK-LABEL: and4xi32:
598 ; CHECK: // %bb.0:
599 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
600 ; CHECK-NEXT: ret
601 %tmp1 = and <4 x i32> %a, %b;
602 ret <4 x i32> %tmp1
603 }
605 define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) {
606 ; CHECK-LABEL: and8xi16:
607 ; CHECK: // %bb.0:
608 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
609 ; CHECK-NEXT: ret
610 %tmp1 = and <8 x i16> %a, %b;
611 ret <8 x i16> %tmp1
612 }
614 define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) {
615 ; CHECK-LABEL: and2xi64:
616 ; CHECK: // %bb.0:
617 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
618 ; CHECK-NEXT: ret
619 %tmp1 = and <2 x i64> %a, %b;
620 ret <2 x i64> %tmp1
621 }
623 define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) {
624 ; CHECK-LABEL: orr2xi32:
625 ; CHECK: // %bb.0:
626 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
627 ; CHECK-NEXT: ret
628 %tmp1 = or <2 x i32> %a, %b;
629 ret <2 x i32> %tmp1
630 }
632 define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) {
633 ; CHECK-LABEL: orr4xi16:
634 ; CHECK: // %bb.0:
635 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
636 ; CHECK-NEXT: ret
637 %tmp1 = or <4 x i16> %a, %b;
638 ret <4 x i16> %tmp1
639 }
641 define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) {
642 ; CHECK-SD-LABEL: orr1xi64:
643 ; CHECK-SD: // %bb.0:
644 ; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
645 ; CHECK-SD-NEXT: ret
646 ;
647 ; CHECK-GI-LABEL: orr1xi64:
648 ; CHECK-GI: // %bb.0:
649 ; CHECK-GI-NEXT: fmov x8, d0
650 ; CHECK-GI-NEXT: fmov x9, d1
651 ; CHECK-GI-NEXT: orr x8, x8, x9
652 ; CHECK-GI-NEXT: fmov d0, x8
653 ; CHECK-GI-NEXT: ret
654 %tmp1 = or <1 x i64> %a, %b;
655 ret <1 x i64> %tmp1
656 }
658 define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) {
659 ; CHECK-LABEL: orr4xi32:
660 ; CHECK: // %bb.0:
661 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
662 ; CHECK-NEXT: ret
663 %tmp1 = or <4 x i32> %a, %b;
664 ret <4 x i32> %tmp1
665 }
667 define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) {
668 ; CHECK-LABEL: orr8xi16:
669 ; CHECK: // %bb.0:
670 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
671 ; CHECK-NEXT: ret
672 %tmp1 = or <8 x i16> %a, %b;
673 ret <8 x i16> %tmp1
674 }
676 define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) {
677 ; CHECK-LABEL: orr2xi64:
678 ; CHECK: // %bb.0:
679 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
680 ; CHECK-NEXT: ret
681 %tmp1 = or <2 x i64> %a, %b;
682 ret <2 x i64> %tmp1
683 }
685 define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) {
686 ; CHECK-LABEL: eor2xi32:
687 ; CHECK: // %bb.0:
688 ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
689 ; CHECK-NEXT: ret
690 %tmp1 = xor <2 x i32> %a, %b;
691 ret <2 x i32> %tmp1
692 }
694 define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) {
695 ; CHECK-LABEL: eor4xi16:
696 ; CHECK: // %bb.0:
697 ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
698 ; CHECK-NEXT: ret
699 %tmp1 = xor <4 x i16> %a, %b;
700 ret <4 x i16> %tmp1
701 }
703 define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) {
704 ; CHECK-SD-LABEL: eor1xi64:
705 ; CHECK-SD: // %bb.0:
706 ; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
707 ; CHECK-SD-NEXT: ret
708 ;
709 ; CHECK-GI-LABEL: eor1xi64:
710 ; CHECK-GI: // %bb.0:
711 ; CHECK-GI-NEXT: fmov x8, d0
712 ; CHECK-GI-NEXT: fmov x9, d1
713 ; CHECK-GI-NEXT: eor x8, x8, x9
714 ; CHECK-GI-NEXT: fmov d0, x8
715 ; CHECK-GI-NEXT: ret
716 %tmp1 = xor <1 x i64> %a, %b;
717 ret <1 x i64> %tmp1
718 }
720 define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) {
721 ; CHECK-LABEL: eor4xi32:
722 ; CHECK: // %bb.0:
723 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
724 ; CHECK-NEXT: ret
725 %tmp1 = xor <4 x i32> %a, %b;
726 ret <4 x i32> %tmp1
727 }
729 define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) {
730 ; CHECK-LABEL: eor8xi16:
731 ; CHECK: // %bb.0:
732 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
733 ; CHECK-NEXT: ret
734 %tmp1 = xor <8 x i16> %a, %b;
735 ret <8 x i16> %tmp1
736 }
738 define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) {
739 ; CHECK-LABEL: eor2xi64:
740 ; CHECK: // %bb.0:
741 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
742 ; CHECK-NEXT: ret
743 %tmp1 = xor <2 x i64> %a, %b;
744 ret <2 x i64> %tmp1
745 }
748 define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) {
749 ; CHECK-LABEL: bic2xi32:
750 ; CHECK: // %bb.0:
751 ; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
752 ; CHECK-NEXT: ret
753 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
754 %tmp2 = and <2 x i32> %a, %tmp1
755 ret <2 x i32> %tmp2
756 }
758 define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) {
759 ; CHECK-LABEL: bic4xi16:
760 ; CHECK: // %bb.0:
761 ; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
762 ; CHECK-NEXT: ret
763 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
764 %tmp2 = and <4 x i16> %a, %tmp1
765 ret <4 x i16> %tmp2
766 }
768 define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) {
769 ; CHECK-SD-LABEL: bic1xi64:
770 ; CHECK-SD: // %bb.0:
771 ; CHECK-SD-NEXT: bic v0.8b, v0.8b, v1.8b
772 ; CHECK-SD-NEXT: ret
773 ;
774 ; CHECK-GI-LABEL: bic1xi64:
775 ; CHECK-GI: // %bb.0:
776 ; CHECK-GI-NEXT: fmov x8, d1
777 ; CHECK-GI-NEXT: fmov x9, d0
778 ; CHECK-GI-NEXT: bic x8, x9, x8
779 ; CHECK-GI-NEXT: fmov d0, x8
780 ; CHECK-GI-NEXT: ret
781 %tmp1 = xor <1 x i64> %b, < i64 -1>
782 %tmp2 = and <1 x i64> %a, %tmp1
783 ret <1 x i64> %tmp2
784 }
786 define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) {
787 ; CHECK-LABEL: bic4xi32:
788 ; CHECK: // %bb.0:
789 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
790 ; CHECK-NEXT: ret
791 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
792 %tmp2 = and <4 x i32> %a, %tmp1
793 ret <4 x i32> %tmp2
794 }
796 define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) {
797 ; CHECK-LABEL: bic8xi16:
798 ; CHECK: // %bb.0:
799 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
800 ; CHECK-NEXT: ret
801 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
802 %tmp2 = and <8 x i16> %a, %tmp1
803 ret <8 x i16> %tmp2
804 }
806 define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) {
807 ; CHECK-LABEL: bic2xi64:
808 ; CHECK: // %bb.0:
809 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
810 ; CHECK-NEXT: ret
811 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
812 %tmp2 = and <2 x i64> %a, %tmp1
813 ret <2 x i64> %tmp2
814 }
816 define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) {
817 ; CHECK-LABEL: orn2xi32:
818 ; CHECK: // %bb.0:
819 ; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
820 ; CHECK-NEXT: ret
821 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
822 %tmp2 = or <2 x i32> %a, %tmp1
823 ret <2 x i32> %tmp2
824 }
826 define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) {
827 ; CHECK-LABEL: orn4xi16:
828 ; CHECK: // %bb.0:
829 ; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
830 ; CHECK-NEXT: ret
831 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
832 %tmp2 = or <4 x i16> %a, %tmp1
833 ret <4 x i16> %tmp2
834 }
836 define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) {
837 ; CHECK-SD-LABEL: orn1xi64:
838 ; CHECK-SD: // %bb.0:
839 ; CHECK-SD-NEXT: orn v0.8b, v0.8b, v1.8b
840 ; CHECK-SD-NEXT: ret
841 ;
842 ; CHECK-GI-LABEL: orn1xi64:
843 ; CHECK-GI: // %bb.0:
844 ; CHECK-GI-NEXT: fmov x8, d1
845 ; CHECK-GI-NEXT: fmov x9, d0
846 ; CHECK-GI-NEXT: orn x8, x9, x8
847 ; CHECK-GI-NEXT: fmov d0, x8
848 ; CHECK-GI-NEXT: ret
849 %tmp1 = xor <1 x i64> %b, < i64 -1>
850 %tmp2 = or <1 x i64> %a, %tmp1
851 ret <1 x i64> %tmp2
852 }
854 define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) {
855 ; CHECK-LABEL: orn4xi32:
856 ; CHECK: // %bb.0:
857 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
858 ; CHECK-NEXT: ret
859 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
860 %tmp2 = or <4 x i32> %a, %tmp1
861 ret <4 x i32> %tmp2
862 }
864 define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) {
865 ; CHECK-LABEL: orn8xi16:
866 ; CHECK: // %bb.0:
867 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
868 ; CHECK-NEXT: ret
869 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
870 %tmp2 = or <8 x i16> %a, %tmp1
871 ret <8 x i16> %tmp2
872 }
874 define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) {
875 ; CHECK-LABEL: orn2xi64:
876 ; CHECK: // %bb.0:
877 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
878 ; CHECK-NEXT: ret
879 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
880 %tmp2 = or <2 x i64> %a, %tmp1
881 ret <2 x i64> %tmp2
882 }
884 define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) {
885 ; CHECK-SD-LABEL: bsl2xi32_const:
886 ; CHECK-SD: // %bb.0:
887 ; CHECK-SD-NEXT: movi d2, #0x000000ffffffff
888 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
889 ; CHECK-SD-NEXT: ret
890 ;
891 ; CHECK-GI-LABEL: bsl2xi32_const:
892 ; CHECK-GI: // %bb.0:
893 ; CHECK-GI-NEXT: adrp x8, .LCPI70_0
894 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI70_0]
895 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
896 ; CHECK-GI-NEXT: ret
897 %tmp1 = and <2 x i32> %a, < i32 -1, i32 0 >
898 %tmp2 = and <2 x i32> %b, < i32 0, i32 -1 >
899 %tmp3 = or <2 x i32> %tmp1, %tmp2
900 ret <2 x i32> %tmp3
901 }
904 define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) {
905 ; CHECK-SD-LABEL: bsl4xi16_const:
906 ; CHECK-SD: // %bb.0:
907 ; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
908 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
909 ; CHECK-SD-NEXT: ret
910 ;
911 ; CHECK-GI-LABEL: bsl4xi16_const:
912 ; CHECK-GI: // %bb.0:
913 ; CHECK-GI-NEXT: adrp x8, .LCPI71_0
914 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI71_0]
915 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
916 ; CHECK-GI-NEXT: ret
917 %tmp1 = and <4 x i16> %a, < i16 -1, i16 0, i16 -1,i16 0 >
918 %tmp2 = and <4 x i16> %b, < i16 0, i16 -1,i16 0, i16 -1 >
919 %tmp3 = or <4 x i16> %tmp1, %tmp2
920 ret <4 x i16> %tmp3
921 }
923 define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) {
924 ; CHECK-SD-LABEL: bsl1xi64_const:
925 ; CHECK-SD: // %bb.0:
926 ; CHECK-SD-NEXT: movi d2, #0xffffffffffffff00
927 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
928 ; CHECK-SD-NEXT: ret
929 ;
930 ; CHECK-GI-LABEL: bsl1xi64_const:
931 ; CHECK-GI: // %bb.0:
932 ; CHECK-GI-NEXT: fmov x8, d0
933 ; CHECK-GI-NEXT: fmov x9, d1
934 ; CHECK-GI-NEXT: and x8, x8, #0xffffffffffffff00
935 ; CHECK-GI-NEXT: and x9, x9, #0xff
936 ; CHECK-GI-NEXT: orr x8, x8, x9
937 ; CHECK-GI-NEXT: fmov d0, x8
938 ; CHECK-GI-NEXT: ret
939 %tmp1 = and <1 x i64> %a, < i64 -256 >
940 %tmp2 = and <1 x i64> %b, < i64 255 >
941 %tmp3 = or <1 x i64> %tmp1, %tmp2
942 ret <1 x i64> %tmp3
943 }
945 define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) {
946 ; CHECK-SD-LABEL: bsl4xi32_const:
947 ; CHECK-SD: // %bb.0:
948 ; CHECK-SD-NEXT: movi v2.2d, #0x000000ffffffff
949 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
950 ; CHECK-SD-NEXT: ret
951 ;
952 ; CHECK-GI-LABEL: bsl4xi32_const:
953 ; CHECK-GI: // %bb.0:
954 ; CHECK-GI-NEXT: adrp x8, .LCPI73_0
955 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI73_0]
956 ; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
957 ; CHECK-GI-NEXT: ret
958 %tmp1 = and <4 x i32> %a, < i32 -1, i32 0, i32 -1, i32 0 >
959 %tmp2 = and <4 x i32> %b, < i32 0, i32 -1, i32 0, i32 -1 >
960 %tmp3 = or <4 x i32> %tmp1, %tmp2
961 ret <4 x i32> %tmp3
962 }
964 define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) {
965 ; CHECK-SD-LABEL: bsl8xi16_const:
966 ; CHECK-SD: // %bb.0:
967 ; CHECK-SD-NEXT: movi v2.2d, #0x000000ffffffff
968 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
969 ; CHECK-SD-NEXT: ret
970 ;
971 ; CHECK-GI-LABEL: bsl8xi16_const:
972 ; CHECK-GI: // %bb.0:
973 ; CHECK-GI-NEXT: adrp x8, .LCPI74_0
974 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI74_0]
975 ; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
976 ; CHECK-GI-NEXT: ret
977 %tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 0,i16 0, i16 -1, i16 -1, i16 0,i16 0 >
978 %tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 -1, i16 -1 >
979 %tmp3 = or <8 x i16> %tmp1, %tmp2
980 ret <8 x i16> %tmp3
981 }
983 define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) {
984 ; CHECK-LABEL: bsl2xi64_const:
985 ; CHECK: // %bb.0:
986 ; CHECK-NEXT: adrp x8, .LCPI75_0
987 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI75_0]
988 ; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
989 ; CHECK-NEXT: ret
990 %tmp1 = and <2 x i64> %a, < i64 -1, i64 0 >
991 %tmp2 = and <2 x i64> %b, < i64 0, i64 -1 >
992 %tmp3 = or <2 x i64> %tmp1, %tmp2
993 ret <2 x i64> %tmp3
994 }
997 define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {
998 ; CHECK-LABEL: bsl8xi8:
999 ; CHECK: // %bb.0:
1000 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1001 ; CHECK-NEXT: ret
1002 %1 = and <8 x i8> %v1, %v2
1003 %2 = xor <8 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
1004 %3 = and <8 x i8> %2, %v3
1005 %4 = or <8 x i8> %1, %3
1006 ret <8 x i8> %4
1007 }
1009 define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) {
1010 ; CHECK-LABEL: bsl4xi16:
1011 ; CHECK: // %bb.0:
1012 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1013 ; CHECK-NEXT: ret
1014 %1 = and <4 x i16> %v1, %v2
1015 %2 = xor <4 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1>
1016 %3 = and <4 x i16> %2, %v3
1017 %4 = or <4 x i16> %1, %3
1018 ret <4 x i16> %4
1019 }
1021 define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {
1022 ; CHECK-LABEL: bsl2xi32:
1023 ; CHECK: // %bb.0:
1024 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1025 ; CHECK-NEXT: ret
1026 %1 = and <2 x i32> %v1, %v2
1027 %2 = xor <2 x i32> %v1, <i32 -1, i32 -1>
1028 %3 = and <2 x i32> %2, %v3
1029 %4 = or <2 x i32> %1, %3
1030 ret <2 x i32> %4
1031 }
1033 define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
1034 ; CHECK-SD-LABEL: bsl1xi64:
1035 ; CHECK-SD: // %bb.0:
1036 ; CHECK-SD-NEXT: bsl v0.8b, v1.8b, v2.8b
1037 ; CHECK-SD-NEXT: ret
1038 ;
1039 ; CHECK-GI-LABEL: bsl1xi64:
1040 ; CHECK-GI: // %bb.0:
1041 ; CHECK-GI-NEXT: fmov x8, d0
1042 ; CHECK-GI-NEXT: fmov x9, d1
1043 ; CHECK-GI-NEXT: fmov x10, d2
1044 ; CHECK-GI-NEXT: and x9, x8, x9
1045 ; CHECK-GI-NEXT: bic x8, x10, x8
1046 ; CHECK-GI-NEXT: orr x8, x9, x8
1047 ; CHECK-GI-NEXT: fmov d0, x8
1048 ; CHECK-GI-NEXT: ret
1049 %1 = and <1 x i64> %v1, %v2
1050 %2 = xor <1 x i64> %v1, <i64 -1>
1051 %3 = and <1 x i64> %2, %v3
1052 %4 = or <1 x i64> %1, %3
1053 ret <1 x i64> %4
1054 }
1056 define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {
1057 ; CHECK-LABEL: bsl16xi8:
1058 ; CHECK: // %bb.0:
1059 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1060 ; CHECK-NEXT: ret
1061 %1 = and <16 x i8> %v1, %v2
1062 %2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
1063 %3 = and <16 x i8> %2, %v3
1064 %4 = or <16 x i8> %1, %3
1065 ret <16 x i8> %4
1066 }
1068 define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
1069 ; CHECK-LABEL: bsl8xi16:
1070 ; CHECK: // %bb.0:
1071 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1072 ; CHECK-NEXT: ret
1073 %1 = and <8 x i16> %v1, %v2
1074 %2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
1075 %3 = and <8 x i16> %2, %v3
1076 %4 = or <8 x i16> %1, %3
1077 ret <8 x i16> %4
1078 }
1080 define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
1081 ; CHECK-LABEL: bsl4xi32:
1082 ; CHECK: // %bb.0:
1083 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1084 ; CHECK-NEXT: ret
1085 %1 = and <4 x i32> %v1, %v2
1086 %2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
1087 %3 = and <4 x i32> %2, %v3
1088 %4 = or <4 x i32> %1, %3
1089 ret <4 x i32> %4
1090 }
1092 define <8 x i8> @vselect_constant_cond_zero_v8i8(<8 x i8> %a) {
1093 ; CHECK-SD-LABEL: vselect_constant_cond_zero_v8i8:
1094 ; CHECK-SD: // %bb.0:
1095 ; CHECK-SD-NEXT: movi d1, #0x00000000ff00ff
1096 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
1097 ; CHECK-SD-NEXT: ret
1098 ;
1099 ; CHECK-GI-LABEL: vselect_constant_cond_zero_v8i8:
1100 ; CHECK-GI: // %bb.0:
1101 ; CHECK-GI-NEXT: adrp x8, .LCPI83_0
1102 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI83_0]
1103 ; CHECK-GI-NEXT: shl v1.8b, v1.8b, #7
1104 ; CHECK-GI-NEXT: sshr v1.8b, v1.8b, #7
1105 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1106 ; CHECK-GI-NEXT: ret
1107 %b = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> zeroinitializer
1108 ret <8 x i8> %b
1109 }
1111 define <4 x i16> @vselect_constant_cond_zero_v4i16(<4 x i16> %a) {
1112 ; CHECK-SD-LABEL: vselect_constant_cond_zero_v4i16:
1113 ; CHECK-SD: // %bb.0:
1114 ; CHECK-SD-NEXT: movi d1, #0xffff00000000ffff
1115 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
1116 ; CHECK-SD-NEXT: ret
1117 ;
1118 ; CHECK-GI-LABEL: vselect_constant_cond_zero_v4i16:
1119 ; CHECK-GI: // %bb.0:
1120 ; CHECK-GI-NEXT: mov w8, #1 // =0x1
1121 ; CHECK-GI-NEXT: mov w9, #0 // =0x0
1122 ; CHECK-GI-NEXT: fmov s1, w8
1123 ; CHECK-GI-NEXT: mov v1.h[1], w9
1124 ; CHECK-GI-NEXT: mov v1.h[2], w9
1125 ; CHECK-GI-NEXT: mov v1.h[3], w8
1126 ; CHECK-GI-NEXT: shl v1.4h, v1.4h, #15
1127 ; CHECK-GI-NEXT: sshr v1.4h, v1.4h, #15
1128 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1129 ; CHECK-GI-NEXT: ret
1130 %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i16> %a, <4 x i16> zeroinitializer
1131 ret <4 x i16> %b
1132 }
1134 define <4 x i32> @vselect_constant_cond_zero_v4i32(<4 x i32> %a) {
1135 ; CHECK-SD-LABEL: vselect_constant_cond_zero_v4i32:
1136 ; CHECK-SD: // %bb.0:
1137 ; CHECK-SD-NEXT: adrp x8, .LCPI85_0
1138 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI85_0]
1139 ; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
1140 ; CHECK-SD-NEXT: ret
1141 ;
1142 ; CHECK-GI-LABEL: vselect_constant_cond_zero_v4i32:
1143 ; CHECK-GI: // %bb.0:
1144 ; CHECK-GI-NEXT: mov w8, #1 // =0x1
1145 ; CHECK-GI-NEXT: mov w9, #0 // =0x0
1146 ; CHECK-GI-NEXT: mov v1.s[0], w8
1147 ; CHECK-GI-NEXT: mov v1.s[1], w9
1148 ; CHECK-GI-NEXT: mov v1.s[2], w9
1149 ; CHECK-GI-NEXT: mov v1.s[3], w8
1150 ; CHECK-GI-NEXT: shl v1.4s, v1.4s, #31
1151 ; CHECK-GI-NEXT: sshr v1.4s, v1.4s, #31
1152 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1153 ; CHECK-GI-NEXT: ret
1154 %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> %a, <4 x i32> zeroinitializer
1155 ret <4 x i32> %b
1156 }
1158 define <8 x i8> @vselect_constant_cond_v8i8(<8 x i8> %a, <8 x i8> %b) {
1159 ; CHECK-SD-LABEL: vselect_constant_cond_v8i8:
1160 ; CHECK-SD: // %bb.0:
1161 ; CHECK-SD-NEXT: movi d2, #0xffffffffff00ff00
1162 ; CHECK-SD-NEXT: movi d3, #0x00000000ff00ff
1163 ; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b
1164 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v3.8b
1165 ; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
1166 ; CHECK-SD-NEXT: ret
1167 ;
1168 ; CHECK-GI-LABEL: vselect_constant_cond_v8i8:
1169 ; CHECK-GI: // %bb.0:
1170 ; CHECK-GI-NEXT: adrp x8, .LCPI86_0
1171 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI86_0]
1172 ; CHECK-GI-NEXT: shl v2.8b, v2.8b, #7
1173 ; CHECK-GI-NEXT: sshr v2.8b, v2.8b, #7
1174 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
1175 ; CHECK-GI-NEXT: ret
1176 %c = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> %b
1177 ret <8 x i8> %c
1178 }
1180 define <4 x i16> @vselect_constant_cond_v4i16(<4 x i16> %a, <4 x i16> %b) {
1181 ; CHECK-SD-LABEL: vselect_constant_cond_v4i16:
1182 ; CHECK-SD: // %bb.0:
1183 ; CHECK-SD-NEXT: movi d2, #0x00ffffffff0000
1184 ; CHECK-SD-NEXT: movi d3, #0xffff00000000ffff
1185 ; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b
1186 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v3.8b
1187 ; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
1188 ; CHECK-SD-NEXT: ret
1189 ;
1190 ; CHECK-GI-LABEL: vselect_constant_cond_v4i16:
1191 ; CHECK-GI: // %bb.0:
1192 ; CHECK-GI-NEXT: mov w8, #1 // =0x1
1193 ; CHECK-GI-NEXT: mov w9, #0 // =0x0
1194 ; CHECK-GI-NEXT: fmov s2, w8
1195 ; CHECK-GI-NEXT: mov v2.h[1], w9
1196 ; CHECK-GI-NEXT: mov v2.h[2], w9
1197 ; CHECK-GI-NEXT: mov v2.h[3], w8
1198 ; CHECK-GI-NEXT: shl v2.4h, v2.4h, #15
1199 ; CHECK-GI-NEXT: sshr v2.4h, v2.4h, #15
1200 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
1201 ; CHECK-GI-NEXT: ret
1202 %c = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i16> %a, <4 x i16> %b
1203 ret <4 x i16> %c
1204 }
1206 define <4 x i32> @vselect_constant_cond_v4i32(<4 x i32> %a, <4 x i32> %b) {
1207 ; CHECK-SD-LABEL: vselect_constant_cond_v4i32:
1208 ; CHECK-SD: // %bb.0:
1209 ; CHECK-SD-NEXT: adrp x8, .LCPI88_0
1210 ; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI88_0]
1211 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
1212 ; CHECK-SD-NEXT: ret
1213 ;
1214 ; CHECK-GI-LABEL: vselect_constant_cond_v4i32:
1215 ; CHECK-GI: // %bb.0:
1216 ; CHECK-GI-NEXT: mov w8, #1 // =0x1
1217 ; CHECK-GI-NEXT: mov w9, #0 // =0x0
1218 ; CHECK-GI-NEXT: mov v2.s[0], w8
1219 ; CHECK-GI-NEXT: mov v2.s[1], w9
1220 ; CHECK-GI-NEXT: mov v2.s[2], w9
1221 ; CHECK-GI-NEXT: mov v2.s[3], w8
1222 ; CHECK-GI-NEXT: shl v2.4s, v2.4s, #31
1223 ; CHECK-GI-NEXT: sshr v2.4s, v2.4s, #31
1224 ; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
1225 ; CHECK-GI-NEXT: ret
1226 %c = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> %a, <4 x i32> %b
1227 ret <4 x i32> %c
1228 }
1230 ; CHECK-SD: .byte 0
1231 ; CHECK-SD: .byte 8
1232 ; CHECK-SD: .byte 2
1233 ; CHECK-SD: .byte 9
1234 ; CHECK-SD: .byte 4
1235 ; CHECK-SD: .byte 5
1236 ; CHECK-SD: .byte 6
1237 ; CHECK-SD: .byte 7
1238 define <8 x i8> @vselect_equivalent_shuffle_v8i8(<8 x i8> %a, <8 x i8> %b) {
1239 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i8:
1240 ; CHECK-SD: // %bb.0:
1241 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
1242 ; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
1243 ; CHECK-SD-NEXT: adrp x8, .LCPI89_0
1244 ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
1245 ; CHECK-SD-NEXT: ldr d1, [x8, :lo12:.LCPI89_0]
1246 ; CHECK-SD-NEXT: tbl v0.8b, { v0.16b }, v1.8b
1247 ; CHECK-SD-NEXT: ret
1248 ;
1249 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i8:
1250 ; CHECK-GI: // %bb.0:
1251 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1252 ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
1253 ; CHECK-GI-NEXT: adrp x8, .LCPI89_0
1254 ; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
1255 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI89_0]
1256 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1257 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1258 ; CHECK-GI-NEXT: ret
1259 %c = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1260 ret <8 x i8> %c
1261 }
1263 define <8 x i8> @vselect_equivalent_shuffle_v8i8_zero(<8 x i8> %a) {
1264 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i8_zero:
1265 ; CHECK-SD: // %bb.0:
1266 ; CHECK-SD-NEXT: movi d1, #0xffffffff00ff00ff
1267 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
1268 ; CHECK-SD-NEXT: ret
1269 ;
1270 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i8_zero:
1271 ; CHECK-GI: // %bb.0:
1272 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1273 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1274 ; CHECK-GI-NEXT: adrp x8, .LCPI90_0
1275 ; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
1276 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI90_0]
1277 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1278 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1279 ; CHECK-GI-NEXT: ret
1280 %c = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1281 ret <8 x i8> %c
1282 }
1284 ; CHECK-SD-LABEL: .LCPI91_0:
1285 ; CHECK-SD-NEXT: .byte 0
1286 ; CHECK-SD-NEXT: .byte 255
1287 ; CHECK-SD-NEXT: .byte 2
1288 ; CHECK-SD-NEXT: .byte 255
1289 ; CHECK-SD-NEXT: .byte 4
1290 ; CHECK-SD-NEXT: .byte 5
1291 ; CHECK-SD-NEXT: .byte 6
1292 ; CHECK-SD-NEXT: .byte 7
1293 define <8 x i8> @vselect_equivalent_shuffle_v8i8_zeroswap(<8 x i8> %a) {
1294 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i8_zeroswap:
1295 ; CHECK-SD: // %bb.0:
1296 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
1297 ; CHECK-SD-NEXT: adrp x8, .LCPI91_0
1298 ; CHECK-SD-NEXT: mov v0.d[1], v0.d[0]
1299 ; CHECK-SD-NEXT: ldr d1, [x8, :lo12:.LCPI91_0]
1300 ; CHECK-SD-NEXT: tbl v0.8b, { v0.16b }, v1.8b
1301 ; CHECK-SD-NEXT: ret
1302 ;
1303 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i8_zeroswap:
1304 ; CHECK-GI: // %bb.0:
1305 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1306 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1307 ; CHECK-GI-NEXT: adrp x8, .LCPI91_0
1308 ; CHECK-GI-NEXT: mov v1.d[1], v0.d[0]
1309 ; CHECK-GI-NEXT: ldr d0, [x8, :lo12:.LCPI91_0]
1310 ; CHECK-GI-NEXT: tbl v0.16b, { v1.16b }, v0.16b
1311 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1312 ; CHECK-GI-NEXT: ret
1313 %c = shufflevector <8 x i8> zeroinitializer, <8 x i8> %a, <8 x i32> <i32 8, i32 0, i32 10, i32 1, i32 12, i32 13, i32 14, i32 15>
1314 ret <8 x i8> %c
1315 }
1317 ; CHECK-SD-LABEL: .LCPI92_0:
1318 ; CHECK-SD-NEXT: .byte 0
1319 ; CHECK-SD-NEXT: .byte 1
1320 ; CHECK-SD-NEXT: .byte 16
1321 ; CHECK-SD-NEXT: .byte 17
1322 ; CHECK-SD-NEXT: .byte 4
1323 ; CHECK-SD-NEXT: .byte 5
1324 ; CHECK-SD-NEXT: .byte 18
1325 ; CHECK-SD-NEXT: .byte 19
1326 ; CHECK-SD-NEXT: .byte 8
1327 ; CHECK-SD-NEXT: .byte 9
1328 ; CHECK-SD-NEXT: .byte 10
1329 ; CHECK-SD-NEXT: .byte 11
1330 ; CHECK-SD-NEXT: .byte 12
1331 ; CHECK-SD-NEXT: .byte 13
1332 ; CHECK-SD-NEXT: .byte 14
1333 ; CHECK-SD-NEXT: .byte 15
1334 define <8 x i16> @vselect_equivalent_shuffle_v8i16(<8 x i16> %a, <8 x i16> %b) {
1335 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i16:
1336 ; CHECK-SD: // %bb.0:
1337 ; CHECK-SD-NEXT: adrp x8, .LCPI92_0
1338 ; CHECK-SD-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
1339 ; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI92_0]
1340 ; CHECK-SD-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
1341 ; CHECK-SD-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1342 ; CHECK-SD-NEXT: ret
1343 ;
1344 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i16:
1345 ; CHECK-GI: // %bb.0:
1346 ; CHECK-GI-NEXT: adrp x8, .LCPI92_0
1347 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
1348 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI92_0]
1349 ; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
1350 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1351 ; CHECK-GI-NEXT: ret
1352 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1353 ret <8 x i16> %c
1354 }
1356 ; CHECK-SD-LABEL: .LCPI93_0:
1357 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1358 ; CHECK-SD-NEXT: .hword 0 // 0x0
1359 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1360 ; CHECK-SD-NEXT: .hword 0 // 0x0
1361 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1362 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1363 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1364 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1365 define <8 x i16> @vselect_equivalent_shuffle_v8i16_zero(<8 x i16> %a) {
1366 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i16_zero:
1367 ; CHECK-SD: // %bb.0:
1368 ; CHECK-SD-NEXT: adrp x8, .LCPI93_0
1369 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI93_0]
1370 ; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
1371 ; CHECK-SD-NEXT: ret
1372 ;
1373 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i16_zero:
1374 ; CHECK-GI: // %bb.0:
1375 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1
1376 ; CHECK-GI-NEXT: adrp x8, .LCPI93_0
1377 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1378 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI93_0]
1379 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1380 ; CHECK-GI-NEXT: ret
1381 %c = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1382 ret <8 x i16> %c
1383 }
1385 ; CHECK-SD: .byte 0
1386 ; CHECK-SD: .byte 1
1387 ; CHECK-SD: .byte 255
1388 ; CHECK-SD: .byte 255
1389 ; CHECK-SD: .byte 4
1390 ; CHECK-SD: .byte 5
1391 ; CHECK-SD: .byte 255
1392 ; CHECK-SD: .byte 255
1393 ; CHECK-SD: .byte 8
1394 ; CHECK-SD: .byte 9
1395 ; CHECK-SD: .byte 10
1396 ; CHECK-SD: .byte 11
1397 ; CHECK-SD: .byte 12
1398 ; CHECK-SD: .byte 13
1399 ; CHECK-SD: .byte 14
1400 ; CHECK-SD: .byte 15
1401 define <8 x i16> @vselect_equivalent_shuffle_v8i16_zeroswap(<8 x i16> %a) {
1402 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i16_zeroswap:
1403 ; CHECK-SD: // %bb.0:
1404 ; CHECK-SD-NEXT: adrp x8, .LCPI94_0
1405 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI94_0]
1406 ; CHECK-SD-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1407 ; CHECK-SD-NEXT: ret
1408 ;
1409 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i16_zeroswap:
1410 ; CHECK-GI: // %bb.0:
1411 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q31_q0
1412 ; CHECK-GI-NEXT: adrp x8, .LCPI94_0
1413 ; CHECK-GI-NEXT: movi v31.2d, #0000000000000000
1414 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI94_0]
1415 ; CHECK-GI-NEXT: tbl v0.16b, { v31.16b, v0.16b }, v1.16b
1416 ; CHECK-GI-NEXT: ret
1417 %c = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 0, i32 10, i32 1, i32 12, i32 13, i32 14, i32 15>
1418 ret <8 x i16> %c
1419 }
1421 define <4 x i16> @vselect_equivalent_shuffle_v4i16(<4 x i16> %a, <4 x i16> %b) {
1422 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v4i16:
1423 ; CHECK-SD: // %bb.0:
1424 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
1425 ; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
1426 ; CHECK-SD-NEXT: mov v0.h[1], v1.h[0]
1427 ; CHECK-SD-NEXT: mov v0.h[2], v1.h[1]
1428 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
1429 ; CHECK-SD-NEXT: ret
1430 ;
1431 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v4i16:
1432 ; CHECK-GI: // %bb.0:
1433 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1434 ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
1435 ; CHECK-GI-NEXT: adrp x8, .LCPI95_0
1436 ; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
1437 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI95_0]
1438 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1439 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1440 ; CHECK-GI-NEXT: ret
1441 %c = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 3>
1442 ret <4 x i16> %c
1443 }
1445 define <4 x i32> @vselect_equivalent_shuffle_v4i32(<4 x i32> %a, <4 x i32> %b) {
1446 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v4i32:
1447 ; CHECK-SD: // %bb.0:
1448 ; CHECK-SD-NEXT: mov v0.s[1], v1.s[0]
1449 ; CHECK-SD-NEXT: mov v0.s[2], v1.s[1]
1450 ; CHECK-SD-NEXT: ret
1451 ;
1452 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v4i32:
1453 ; CHECK-GI: // %bb.0:
1454 ; CHECK-GI-NEXT: adrp x8, .LCPI96_0
1455 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
1456 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI96_0]
1457 ; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
1458 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1459 ; CHECK-GI-NEXT: ret
1460 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 3>
1461 ret <4 x i32> %c
1462 }
1464 define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1465 ; CHECK-SD-LABEL: vselect_cmp_ne:
1466 ; CHECK-SD: // %bb.0:
1467 ; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, v1.8b
1468 ; CHECK-SD-NEXT: bsl v0.8b, v2.8b, v1.8b
1469 ; CHECK-SD-NEXT: ret
1470 ;
1471 ; CHECK-GI-LABEL: vselect_cmp_ne:
1472 ; CHECK-GI: // %bb.0:
1473 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
1474 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1475 ; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
1476 ; CHECK-GI-NEXT: ret
1477 %cmp = icmp ne <8 x i8> %a, %b
1478 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1479 ret <8 x i8> %d
1480 }
1482 define <8 x i8> @vselect_cmp_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1483 ; CHECK-LABEL: vselect_cmp_eq:
1484 ; CHECK: // %bb.0:
1485 ; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b
1486 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1487 ; CHECK-NEXT: ret
1488 %cmp = icmp eq <8 x i8> %a, %b
1489 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1490 ret <8 x i8> %d
1491 }
1493 define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1494 ; CHECK-SD-LABEL: vselect_cmpz_ne:
1495 ; CHECK-SD: // %bb.0:
1496 ; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
1497 ; CHECK-SD-NEXT: bsl v0.8b, v2.8b, v1.8b
1498 ; CHECK-SD-NEXT: ret
1499 ;
1500 ; CHECK-GI-LABEL: vselect_cmpz_ne:
1501 ; CHECK-GI: // %bb.0:
1502 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, #0
1503 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1504 ; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
1505 ; CHECK-GI-NEXT: ret
1506 %cmp = icmp ne <8 x i8> %a, zeroinitializer
1507 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1508 ret <8 x i8> %d
1509 }
1511 define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1512 ; CHECK-LABEL: vselect_cmpz_eq:
1513 ; CHECK: // %bb.0:
1514 ; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
1515 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1516 ; CHECK-NEXT: ret
1517 %cmp = icmp eq <8 x i8> %a, zeroinitializer
1518 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1519 ret <8 x i8> %d
1520 }
1522 define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1523 ; CHECK-LABEL: vselect_tst:
1524 ; CHECK: // %bb.0:
1525 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
1526 ; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
1527 ; CHECK-NEXT: bsl v0.8b, v2.8b, v1.8b
1528 ; CHECK-NEXT: ret
1529 %tmp3 = and <8 x i8> %a, %b
1530 %tmp4 = icmp eq <8 x i8> %tmp3, zeroinitializer
1531 %d = select <8 x i1> %tmp4, <8 x i8> %c, <8 x i8> %b
1532 ret <8 x i8> %d
1533 }
1535 define <8 x i8> @sext_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1536 ; CHECK-SD-LABEL: sext_tst:
1537 ; CHECK-SD: // %bb.0:
1538 ; CHECK-SD-NEXT: cmtst v0.8b, v0.8b, v1.8b
1539 ; CHECK-SD-NEXT: ret
1540 ;
1541 ; CHECK-GI-LABEL: sext_tst:
1542 ; CHECK-GI: // %bb.0:
1543 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1544 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, #0
1545 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1546 ; CHECK-GI-NEXT: ret
1547 %tmp3 = and <8 x i8> %a, %b
1548 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
1549 %d = sext <8 x i1> %tmp4 to <8 x i8>
1550 ret <8 x i8> %d
1551 }
1553 define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) {
1554 ; CHECK-LABEL: bsl2xi64:
1555 ; CHECK: // %bb.0:
1556 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1557 ; CHECK-NEXT: ret
1558 %1 = and <2 x i64> %v1, %v2
1559 %2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
1560 %3 = and <2 x i64> %2, %v3
1561 %4 = or <2 x i64> %1, %3
1562 ret <2 x i64> %4
1563 }
1565 define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) {
1566 ; CHECK-SD-LABEL: orrimm8b_as_orrimm4h_lsl0:
1567 ; CHECK-SD: // %bb.0:
1568 ; CHECK-SD-NEXT: orr v0.4h, #255
1569 ; CHECK-SD-NEXT: ret
1570 ;
1571 ; CHECK-GI-LABEL: orrimm8b_as_orrimm4h_lsl0:
1572 ; CHECK-GI: // %bb.0:
1573 ; CHECK-GI-NEXT: adrp x8, .LCPI104_0
1574 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI104_0]
1575 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
1576 ; CHECK-GI-NEXT: ret
1577 %val = or <8 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
1578 ret <8 x i8> %val
1579 }
1581 define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) {
1582 ; CHECK-SD-LABEL: orrimm8b_as_orimm4h_lsl8:
1583 ; CHECK-SD: // %bb.0:
1584 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
1585 ; CHECK-SD-NEXT: ret
1586 ;
1587 ; CHECK-GI-LABEL: orrimm8b_as_orimm4h_lsl8:
1588 ; CHECK-GI: // %bb.0:
1589 ; CHECK-GI-NEXT: adrp x8, .LCPI105_0
1590 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI105_0]
1591 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
1592 ; CHECK-GI-NEXT: ret
1593 %val = or <8 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
1594 ret <8 x i8> %val
1595 }
1597 define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) {
1598 ; CHECK-SD-LABEL: orimm16b_as_orrimm8h_lsl0:
1599 ; CHECK-SD: // %bb.0:
1600 ; CHECK-SD-NEXT: orr v0.8h, #255
1601 ; CHECK-SD-NEXT: ret
1602 ;
1603 ; CHECK-GI-LABEL: orimm16b_as_orrimm8h_lsl0:
1604 ; CHECK-GI: // %bb.0:
1605 ; CHECK-GI-NEXT: adrp x8, .LCPI106_0
1606 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI106_0]
1607 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
1608 ; CHECK-GI-NEXT: ret
1609 %val = or <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
1610 ret <16 x i8> %val
1611 }
1613 define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) {
1614 ; CHECK-SD-LABEL: orimm16b_as_orrimm8h_lsl8:
1615 ; CHECK-SD: // %bb.0:
1616 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
1617 ; CHECK-SD-NEXT: ret
1618 ;
1619 ; CHECK-GI-LABEL: orimm16b_as_orrimm8h_lsl8:
1620 ; CHECK-GI: // %bb.0:
1621 ; CHECK-GI-NEXT: adrp x8, .LCPI107_0
1622 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI107_0]
1623 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
1624 ; CHECK-GI-NEXT: ret
1625 %val = or <16 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
1626 ret <16 x i8> %val
1627 }
1629 define <8 x i8> @and8imm2s_lsl0(<8 x i8> %a) {
1630 ; CHECK-SD-LABEL: and8imm2s_lsl0:
1631 ; CHECK-SD: // %bb.0:
1632 ; CHECK-SD-NEXT: bic v0.2s, #255
1633 ; CHECK-SD-NEXT: ret
1634 ;
1635 ; CHECK-GI-LABEL: and8imm2s_lsl0:
1636 ; CHECK-GI: // %bb.0:
1637 ; CHECK-GI-NEXT: adrp x8, .LCPI108_0
1638 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI108_0]
1639 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1640 ; CHECK-GI-NEXT: ret
1641 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
1642 ret <8 x i8> %tmp1
1643 }
1645 define <8 x i8> @and8imm2s_lsl8(<8 x i8> %a) {
1646 ; CHECK-SD-LABEL: and8imm2s_lsl8:
1647 ; CHECK-SD: // %bb.0:
1648 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #8
1649 ; CHECK-SD-NEXT: ret
1650 ;
1651 ; CHECK-GI-LABEL: and8imm2s_lsl8:
1652 ; CHECK-GI: // %bb.0:
1653 ; CHECK-GI-NEXT: adrp x8, .LCPI109_0
1654 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI109_0]
1655 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1656 ; CHECK-GI-NEXT: ret
1657 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
1658 ret <8 x i8> %tmp1
1659 }
1661 define <8 x i8> @and8imm2s_lsl16(<8 x i8> %a) {
1662 ; CHECK-SD-LABEL: and8imm2s_lsl16:
1663 ; CHECK-SD: // %bb.0:
1664 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #16
1665 ; CHECK-SD-NEXT: ret
1666 ;
1667 ; CHECK-GI-LABEL: and8imm2s_lsl16:
1668 ; CHECK-GI: // %bb.0:
1669 ; CHECK-GI-NEXT: adrp x8, .LCPI110_0
1670 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI110_0]
1671 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1672 ; CHECK-GI-NEXT: ret
1673 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
1674 ret <8 x i8> %tmp1
1675 }
1677 define <8 x i8> @and8imm2s_lsl24(<8 x i8> %a) {
1678 ; CHECK-SD-LABEL: and8imm2s_lsl24:
1679 ; CHECK-SD: // %bb.0:
1680 ; CHECK-SD-NEXT: bic v0.2s, #254, lsl #24
1681 ; CHECK-SD-NEXT: ret
1682 ;
1683 ; CHECK-GI-LABEL: and8imm2s_lsl24:
1684 ; CHECK-GI: // %bb.0:
1685 ; CHECK-GI-NEXT: adrp x8, .LCPI111_0
1686 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI111_0]
1687 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1688 ; CHECK-GI-NEXT: ret
1689 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
1690 ret <8 x i8> %tmp1
1691 }
1693 define <4 x i16> @and16imm2s_lsl0(<4 x i16> %a) {
1694 ; CHECK-SD-LABEL: and16imm2s_lsl0:
1695 ; CHECK-SD: // %bb.0:
1696 ; CHECK-SD-NEXT: bic v0.2s, #255
1697 ; CHECK-SD-NEXT: ret
1698 ;
1699 ; CHECK-GI-LABEL: and16imm2s_lsl0:
1700 ; CHECK-GI: // %bb.0:
1701 ; CHECK-GI-NEXT: adrp x8, .LCPI112_0
1702 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI112_0]
1703 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1704 ; CHECK-GI-NEXT: ret
1705 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535>
1706 ret <4 x i16> %tmp1
1707 }
1709 define <4 x i16> @and16imm2s_lsl8(<4 x i16> %a) {
1710 ; CHECK-SD-LABEL: and16imm2s_lsl8:
1711 ; CHECK-SD: // %bb.0:
1712 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #8
1713 ; CHECK-SD-NEXT: ret
1714 ;
1715 ; CHECK-GI-LABEL: and16imm2s_lsl8:
1716 ; CHECK-GI: // %bb.0:
1717 ; CHECK-GI-NEXT: adrp x8, .LCPI113_0
1718 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI113_0]
1719 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1720 ; CHECK-GI-NEXT: ret
1721 %tmp1 = and <4 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535>
1722 ret <4 x i16> %tmp1
1723 }
1725 define <4 x i16> @and16imm2s_lsl16(<4 x i16> %a) {
1726 ; CHECK-SD-LABEL: and16imm2s_lsl16:
1727 ; CHECK-SD: // %bb.0:
1728 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #16
1729 ; CHECK-SD-NEXT: ret
1730 ;
1731 ; CHECK-GI-LABEL: and16imm2s_lsl16:
1732 ; CHECK-GI: // %bb.0:
1733 ; CHECK-GI-NEXT: adrp x8, .LCPI114_0
1734 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI114_0]
1735 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1736 ; CHECK-GI-NEXT: ret
1737 %tmp1 = and <4 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280>
1738 ret <4 x i16> %tmp1
1739 }
1741 define <4 x i16> @and16imm2s_lsl24(<4 x i16> %a) {
1742 ; CHECK-SD-LABEL: and16imm2s_lsl24:
1743 ; CHECK-SD: // %bb.0:
1744 ; CHECK-SD-NEXT: bic v0.2s, #254, lsl #24
1745 ; CHECK-SD-NEXT: ret
1746 ;
1747 ; CHECK-GI-LABEL: and16imm2s_lsl24:
1748 ; CHECK-GI: // %bb.0:
1749 ; CHECK-GI-NEXT: adrp x8, .LCPI115_0
1750 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI115_0]
1751 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1752 ; CHECK-GI-NEXT: ret
1753 %tmp1 = and <4 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511>
1754 ret <4 x i16> %tmp1
1755 }
1758 define <1 x i64> @and64imm2s_lsl0(<1 x i64> %a) {
1759 ; CHECK-SD-LABEL: and64imm2s_lsl0:
1760 ; CHECK-SD: // %bb.0:
1761 ; CHECK-SD-NEXT: bic v0.2s, #255
1762 ; CHECK-SD-NEXT: ret
1763 ;
1764 ; CHECK-GI-LABEL: and64imm2s_lsl0:
1765 ; CHECK-GI: // %bb.0:
1766 ; CHECK-GI-NEXT: fmov x8, d0
1767 ; CHECK-GI-NEXT: and x8, x8, #0xffffff00ffffff00
1768 ; CHECK-GI-NEXT: fmov d0, x8
1769 ; CHECK-GI-NEXT: ret
1770 %tmp1 = and <1 x i64> %a, < i64 -1095216660736>
1771 ret <1 x i64> %tmp1
1772 }
1774 define <1 x i64> @and64imm2s_lsl8(<1 x i64> %a) {
1775 ; CHECK-SD-LABEL: and64imm2s_lsl8:
1776 ; CHECK-SD: // %bb.0:
1777 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #8
1778 ; CHECK-SD-NEXT: ret
1779 ;
1780 ; CHECK-GI-LABEL: and64imm2s_lsl8:
1781 ; CHECK-GI: // %bb.0:
1782 ; CHECK-GI-NEXT: fmov x8, d0
1783 ; CHECK-GI-NEXT: and x8, x8, #0xffff00ffffff00ff
1784 ; CHECK-GI-NEXT: fmov d0, x8
1785 ; CHECK-GI-NEXT: ret
1786 %tmp1 = and <1 x i64> %a, < i64 -280375465148161>
1787 ret <1 x i64> %tmp1
1788 }
1790 define <1 x i64> @and64imm2s_lsl16(<1 x i64> %a) {
1791 ; CHECK-SD-LABEL: and64imm2s_lsl16:
1792 ; CHECK-SD: // %bb.0:
1793 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #16
1794 ; CHECK-SD-NEXT: ret
1795 ;
1796 ; CHECK-GI-LABEL: and64imm2s_lsl16:
1797 ; CHECK-GI: // %bb.0:
1798 ; CHECK-GI-NEXT: fmov x8, d0
1799 ; CHECK-GI-NEXT: and x8, x8, #0xff00ffffff00ffff
1800 ; CHECK-GI-NEXT: fmov d0, x8
1801 ; CHECK-GI-NEXT: ret
1802 %tmp1 = and <1 x i64> %a, < i64 -71776119077928961>
1803 ret <1 x i64> %tmp1
1804 }
1806 define <1 x i64> @and64imm2s_lsl24(<1 x i64> %a) {
1807 ; CHECK-SD-LABEL: and64imm2s_lsl24:
1808 ; CHECK-SD: // %bb.0:
1809 ; CHECK-SD-NEXT: bic v0.2s, #254, lsl #24
1810 ; CHECK-SD-NEXT: ret
1811 ;
1812 ; CHECK-GI-LABEL: and64imm2s_lsl24:
1813 ; CHECK-GI: // %bb.0:
1814 ; CHECK-GI-NEXT: fmov x8, d0
1815 ; CHECK-GI-NEXT: and x8, x8, #0x1ffffff01ffffff
1816 ; CHECK-GI-NEXT: fmov d0, x8
1817 ; CHECK-GI-NEXT: ret
1818 %tmp1 = and <1 x i64> %a, < i64 144115183814443007>
1819 ret <1 x i64> %tmp1
1820 }
1822 define <16 x i8> @and8imm4s_lsl0(<16 x i8> %a) {
1823 ; CHECK-SD-LABEL: and8imm4s_lsl0:
1824 ; CHECK-SD: // %bb.0:
1825 ; CHECK-SD-NEXT: bic v0.4s, #255
1826 ; CHECK-SD-NEXT: ret
1827 ;
1828 ; CHECK-GI-LABEL: and8imm4s_lsl0:
1829 ; CHECK-GI: // %bb.0:
1830 ; CHECK-GI-NEXT: adrp x8, .LCPI120_0
1831 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI120_0]
1832 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1833 ; CHECK-GI-NEXT: ret
1834 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
1835 ret <16 x i8> %tmp1
1836 }
1838 define <16 x i8> @and8imm4s_lsl8(<16 x i8> %a) {
1839 ; CHECK-SD-LABEL: and8imm4s_lsl8:
1840 ; CHECK-SD: // %bb.0:
1841 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
1842 ; CHECK-SD-NEXT: ret
1843 ;
1844 ; CHECK-GI-LABEL: and8imm4s_lsl8:
1845 ; CHECK-GI: // %bb.0:
1846 ; CHECK-GI-NEXT: adrp x8, .LCPI121_0
1847 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI121_0]
1848 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1849 ; CHECK-GI-NEXT: ret
1850 %tmp1 = and <16 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
1851 ret <16 x i8> %tmp1
1852 }
1854 define <16 x i8> @and8imm4s_lsl16(<16 x i8> %a) {
1855 ; CHECK-SD-LABEL: and8imm4s_lsl16:
1856 ; CHECK-SD: // %bb.0:
1857 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #16
1858 ; CHECK-SD-NEXT: ret
1859 ;
1860 ; CHECK-GI-LABEL: and8imm4s_lsl16:
1861 ; CHECK-GI: // %bb.0:
1862 ; CHECK-GI-NEXT: adrp x8, .LCPI122_0
1863 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI122_0]
1864 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1865 ; CHECK-GI-NEXT: ret
1866 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
1867 ret <16 x i8> %tmp1
1868 }
1870 define <16 x i8> @and8imm4s_lsl24(<16 x i8> %a) {
1871 ; CHECK-SD-LABEL: and8imm4s_lsl24:
1872 ; CHECK-SD: // %bb.0:
1873 ; CHECK-SD-NEXT: bic v0.4s, #254, lsl #24
1874 ; CHECK-SD-NEXT: ret
1875 ;
1876 ; CHECK-GI-LABEL: and8imm4s_lsl24:
1877 ; CHECK-GI: // %bb.0:
1878 ; CHECK-GI-NEXT: adrp x8, .LCPI123_0
1879 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI123_0]
1880 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1881 ; CHECK-GI-NEXT: ret
1882 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
1883 ret <16 x i8> %tmp1
1884 }
1886 define <8 x i16> @and16imm4s_lsl0(<8 x i16> %a) {
1887 ; CHECK-SD-LABEL: and16imm4s_lsl0:
1888 ; CHECK-SD: // %bb.0:
1889 ; CHECK-SD-NEXT: bic v0.4s, #255
1890 ; CHECK-SD-NEXT: ret
1891 ;
1892 ; CHECK-GI-LABEL: and16imm4s_lsl0:
1893 ; CHECK-GI: // %bb.0:
1894 ; CHECK-GI-NEXT: adrp x8, .LCPI124_0
1895 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI124_0]
1896 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1897 ; CHECK-GI-NEXT: ret
1898 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535>
1899 ret <8 x i16> %tmp1
1900 }
1902 define <8 x i16> @and16imm4s_lsl8(<8 x i16> %a) {
1903 ; CHECK-SD-LABEL: and16imm4s_lsl8:
1904 ; CHECK-SD: // %bb.0:
1905 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
1906 ; CHECK-SD-NEXT: ret
1907 ;
1908 ; CHECK-GI-LABEL: and16imm4s_lsl8:
1909 ; CHECK-GI: // %bb.0:
1910 ; CHECK-GI-NEXT: adrp x8, .LCPI125_0
1911 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI125_0]
1912 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1913 ; CHECK-GI-NEXT: ret
1914 %tmp1 = and <8 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535>
1915 ret <8 x i16> %tmp1
1916 }
1918 define <8 x i16> @and16imm4s_lsl16(<8 x i16> %a) {
1919 ; CHECK-SD-LABEL: and16imm4s_lsl16:
1920 ; CHECK-SD: // %bb.0:
1921 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #16
1922 ; CHECK-SD-NEXT: ret
1923 ;
1924 ; CHECK-GI-LABEL: and16imm4s_lsl16:
1925 ; CHECK-GI: // %bb.0:
1926 ; CHECK-GI-NEXT: adrp x8, .LCPI126_0
1927 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI126_0]
1928 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1929 ; CHECK-GI-NEXT: ret
1930 %tmp1 = and <8 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280>
1931 ret <8 x i16> %tmp1
1932 }
1934 define <8 x i16> @and16imm4s_lsl24(<8 x i16> %a) {
1935 ; CHECK-SD-LABEL: and16imm4s_lsl24:
1936 ; CHECK-SD: // %bb.0:
1937 ; CHECK-SD-NEXT: bic v0.4s, #254, lsl #24
1938 ; CHECK-SD-NEXT: ret
1939 ;
1940 ; CHECK-GI-LABEL: and16imm4s_lsl24:
1941 ; CHECK-GI: // %bb.0:
1942 ; CHECK-GI-NEXT: adrp x8, .LCPI127_0
1943 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI127_0]
1944 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1945 ; CHECK-GI-NEXT: ret
1946 %tmp1 = and <8 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511>
1947 ret <8 x i16> %tmp1
1948 }
1950 define <2 x i64> @and64imm4s_lsl0(<2 x i64> %a) {
1951 ; CHECK-SD-LABEL: and64imm4s_lsl0:
1952 ; CHECK-SD: // %bb.0:
1953 ; CHECK-SD-NEXT: bic v0.4s, #255
1954 ; CHECK-SD-NEXT: ret
1955 ;
1956 ; CHECK-GI-LABEL: and64imm4s_lsl0:
1957 ; CHECK-GI: // %bb.0:
1958 ; CHECK-GI-NEXT: movi v1.2d, #0xffffff00ffffff00
1959 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1960 ; CHECK-GI-NEXT: ret
1961 %tmp1 = and <2 x i64> %a, < i64 -1095216660736, i64 -1095216660736>
1962 ret <2 x i64> %tmp1
1963 }
1965 define <2 x i64> @and64imm4s_lsl8(<2 x i64> %a) {
1966 ; CHECK-SD-LABEL: and64imm4s_lsl8:
1967 ; CHECK-SD: // %bb.0:
1968 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
1969 ; CHECK-SD-NEXT: ret
1970 ;
1971 ; CHECK-GI-LABEL: and64imm4s_lsl8:
1972 ; CHECK-GI: // %bb.0:
1973 ; CHECK-GI-NEXT: movi v1.2d, #0xffff00ffffff00ff
1974 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1975 ; CHECK-GI-NEXT: ret
1976 %tmp1 = and <2 x i64> %a, < i64 -280375465148161, i64 -280375465148161>
1977 ret <2 x i64> %tmp1
1978 }
1980 define <2 x i64> @and64imm4s_lsl16(<2 x i64> %a) {
1981 ; CHECK-SD-LABEL: and64imm4s_lsl16:
1982 ; CHECK-SD: // %bb.0:
1983 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #16
1984 ; CHECK-SD-NEXT: ret
1985 ;
1986 ; CHECK-GI-LABEL: and64imm4s_lsl16:
1987 ; CHECK-GI: // %bb.0:
1988 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ffffff00ffff
1989 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1990 ; CHECK-GI-NEXT: ret
1991 %tmp1 = and <2 x i64> %a, < i64 -71776119077928961, i64 -71776119077928961>
1992 ret <2 x i64> %tmp1
1993 }
1995 define <2 x i64> @and64imm4s_lsl24(<2 x i64> %a) {
1996 ; CHECK-SD-LABEL: and64imm4s_lsl24:
1997 ; CHECK-SD: // %bb.0:
1998 ; CHECK-SD-NEXT: bic v0.4s, #254, lsl #24
1999 ; CHECK-SD-NEXT: ret
2000 ;
2001 ; CHECK-GI-LABEL: and64imm4s_lsl24:
2002 ; CHECK-GI: // %bb.0:
2003 ; CHECK-GI-NEXT: mvni v1.4s, #254, lsl #24
2004 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2005 ; CHECK-GI-NEXT: ret
2006 %tmp1 = and <2 x i64> %a, < i64 144115183814443007, i64 144115183814443007>
2007 ret <2 x i64> %tmp1
2008 }
2010 define <8 x i8> @and8imm4h_lsl0(<8 x i8> %a) {
2011 ; CHECK-SD-LABEL: and8imm4h_lsl0:
2012 ; CHECK-SD: // %bb.0:
2013 ; CHECK-SD-NEXT: bic v0.4h, #255
2014 ; CHECK-SD-NEXT: ret
2015 ;
2016 ; CHECK-GI-LABEL: and8imm4h_lsl0:
2017 ; CHECK-GI: // %bb.0:
2018 ; CHECK-GI-NEXT: adrp x8, .LCPI132_0
2019 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI132_0]
2020 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2021 ; CHECK-GI-NEXT: ret
2022 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
2023 ret <8 x i8> %tmp1
2024 }
2026 define <8 x i8> @and8imm4h_lsl8(<8 x i8> %a) {
2027 ; CHECK-SD-LABEL: and8imm4h_lsl8:
2028 ; CHECK-SD: // %bb.0:
2029 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
2030 ; CHECK-SD-NEXT: ret
2031 ;
2032 ; CHECK-GI-LABEL: and8imm4h_lsl8:
2033 ; CHECK-GI: // %bb.0:
2034 ; CHECK-GI-NEXT: adrp x8, .LCPI133_0
2035 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI133_0]
2036 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2037 ; CHECK-GI-NEXT: ret
2038 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
2039 ret <8 x i8> %tmp1
2040 }
2042 define <2 x i32> @and16imm4h_lsl0(<2 x i32> %a) {
2043 ; CHECK-SD-LABEL: and16imm4h_lsl0:
2044 ; CHECK-SD: // %bb.0:
2045 ; CHECK-SD-NEXT: bic v0.4h, #255
2046 ; CHECK-SD-NEXT: ret
2047 ;
2048 ; CHECK-GI-LABEL: and16imm4h_lsl0:
2049 ; CHECK-GI: // %bb.0:
2050 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff00
2051 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2052 ; CHECK-GI-NEXT: ret
2053 %tmp1 = and <2 x i32> %a, < i32 4278255360, i32 4278255360>
2054 ret <2 x i32> %tmp1
2055 }
2057 define <2 x i32> @and16imm4h_lsl8(<2 x i32> %a) {
2058 ; CHECK-SD-LABEL: and16imm4h_lsl8:
2059 ; CHECK-SD: // %bb.0:
2060 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
2061 ; CHECK-SD-NEXT: ret
2062 ;
2063 ; CHECK-GI-LABEL: and16imm4h_lsl8:
2064 ; CHECK-GI: // %bb.0:
2065 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
2066 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2067 ; CHECK-GI-NEXT: ret
2068 %tmp1 = and <2 x i32> %a, < i32 16711935, i32 16711935>
2069 ret <2 x i32> %tmp1
2070 }
2072 define <1 x i64> @and64imm4h_lsl0(<1 x i64> %a) {
2073 ; CHECK-SD-LABEL: and64imm4h_lsl0:
2074 ; CHECK-SD: // %bb.0:
2075 ; CHECK-SD-NEXT: bic v0.4h, #255
2076 ; CHECK-SD-NEXT: ret
2077 ;
2078 ; CHECK-GI-LABEL: and64imm4h_lsl0:
2079 ; CHECK-GI: // %bb.0:
2080 ; CHECK-GI-NEXT: fmov x8, d0
2081 ; CHECK-GI-NEXT: and x8, x8, #0xff00ff00ff00ff00
2082 ; CHECK-GI-NEXT: fmov d0, x8
2083 ; CHECK-GI-NEXT: ret
2084 %tmp1 = and <1 x i64> %a, < i64 -71777214294589696>
2085 ret <1 x i64> %tmp1
2086 }
2088 define <1 x i64> @and64imm4h_lsl8(<1 x i64> %a) {
2089 ; CHECK-SD-LABEL: and64imm4h_lsl8:
2090 ; CHECK-SD: // %bb.0:
2091 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
2092 ; CHECK-SD-NEXT: ret
2093 ;
2094 ; CHECK-GI-LABEL: and64imm4h_lsl8:
2095 ; CHECK-GI: // %bb.0:
2096 ; CHECK-GI-NEXT: fmov x8, d0
2097 ; CHECK-GI-NEXT: and x8, x8, #0xff00ff00ff00ff
2098 ; CHECK-GI-NEXT: fmov d0, x8
2099 ; CHECK-GI-NEXT: ret
2100 %tmp1 = and <1 x i64> %a, < i64 71777214294589695>
2101 ret <1 x i64> %tmp1
2102 }
2104 define <16 x i8> @and8imm8h_lsl0(<16 x i8> %a) {
2105 ; CHECK-SD-LABEL: and8imm8h_lsl0:
2106 ; CHECK-SD: // %bb.0:
2107 ; CHECK-SD-NEXT: bic v0.8h, #255
2108 ; CHECK-SD-NEXT: ret
2109 ;
2110 ; CHECK-GI-LABEL: and8imm8h_lsl0:
2111 ; CHECK-GI: // %bb.0:
2112 ; CHECK-GI-NEXT: adrp x8, .LCPI138_0
2113 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI138_0]
2114 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2115 ; CHECK-GI-NEXT: ret
2116 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255 >
2117 ret <16 x i8> %tmp1
2118 }
2120 define <16 x i8> @and8imm8h_lsl8(<16 x i8> %a) {
2121 ; CHECK-SD-LABEL: and8imm8h_lsl8:
2122 ; CHECK-SD: // %bb.0:
2123 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2124 ; CHECK-SD-NEXT: ret
2125 ;
2126 ; CHECK-GI-LABEL: and8imm8h_lsl8:
2127 ; CHECK-GI: // %bb.0:
2128 ; CHECK-GI-NEXT: adrp x8, .LCPI139_0
2129 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI139_0]
2130 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2131 ; CHECK-GI-NEXT: ret
2132 %tmp1 = and <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0 >
2133 ret <16 x i8> %tmp1
2134 }
2136 define <4 x i32> @and16imm8h_lsl0(<4 x i32> %a) {
2137 ; CHECK-SD-LABEL: and16imm8h_lsl0:
2138 ; CHECK-SD: // %bb.0:
2139 ; CHECK-SD-NEXT: bic v0.8h, #255
2140 ; CHECK-SD-NEXT: ret
2141 ;
2142 ; CHECK-GI-LABEL: and16imm8h_lsl0:
2143 ; CHECK-GI: // %bb.0:
2144 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
2145 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2146 ; CHECK-GI-NEXT: ret
2147 %tmp1 = and <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
2148 ret <4 x i32> %tmp1
2149 }
2151 define <4 x i32> @and16imm8h_lsl8(<4 x i32> %a) {
2152 ; CHECK-SD-LABEL: and16imm8h_lsl8:
2153 ; CHECK-SD: // %bb.0:
2154 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2155 ; CHECK-SD-NEXT: ret
2156 ;
2157 ; CHECK-GI-LABEL: and16imm8h_lsl8:
2158 ; CHECK-GI: // %bb.0:
2159 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
2160 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2161 ; CHECK-GI-NEXT: ret
2162 %tmp1 = and <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
2163 ret <4 x i32> %tmp1
2164 }
2166 define <2 x i64> @and64imm8h_lsl0(<2 x i64> %a) {
2167 ; CHECK-SD-LABEL: and64imm8h_lsl0:
2168 ; CHECK-SD: // %bb.0:
2169 ; CHECK-SD-NEXT: bic v0.8h, #255
2170 ; CHECK-SD-NEXT: ret
2171 ;
2172 ; CHECK-GI-LABEL: and64imm8h_lsl0:
2173 ; CHECK-GI: // %bb.0:
2174 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
2175 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2176 ; CHECK-GI-NEXT: ret
2177 %tmp1 = and <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>
2178 ret <2 x i64> %tmp1
2179 }
2181 define <2 x i64> @and64imm8h_lsl8(<2 x i64> %a) {
2182 ; CHECK-SD-LABEL: and64imm8h_lsl8:
2183 ; CHECK-SD: // %bb.0:
2184 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2185 ; CHECK-SD-NEXT: ret
2186 ;
2187 ; CHECK-GI-LABEL: and64imm8h_lsl8:
2188 ; CHECK-GI: // %bb.0:
2189 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
2190 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2191 ; CHECK-GI-NEXT: ret
2192 %tmp1 = and <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
2193 ret <2 x i64> %tmp1
2194 }
2196 define <8 x i16> @bic_shifted_knownbits(<8 x i16> %v) {
2197 ; CHECK-SD-LABEL: bic_shifted_knownbits:
2198 ; CHECK-SD: // %bb.0: // %entry
2199 ; CHECK-SD-NEXT: ushr v0.8h, v0.8h, #9
2200 ; CHECK-SD-NEXT: bic v0.8h, #126
2201 ; CHECK-SD-NEXT: ret
2202 ;
2203 ; CHECK-GI-LABEL: bic_shifted_knownbits:
2204 ; CHECK-GI: // %bb.0: // %entry
2205 ; CHECK-GI-NEXT: movi v1.8h, #1
2206 ; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #9
2207 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2208 ; CHECK-GI-NEXT: ret
2209 entry:
2210 %vshr_n = lshr <8 x i16> %v, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
2211 %and.i = and <8 x i16> %vshr_n, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
2212 ret <8 x i16> %and.i
2213 }
2215 define <8 x i32> @bic_shifted_knownbits2(<8 x i16> %v) {
2216 ; CHECK-SD-LABEL: bic_shifted_knownbits2:
2217 ; CHECK-SD: // %bb.0: // %entry
2218 ; CHECK-SD-NEXT: ushll v2.4s, v0.4h, #0
2219 ; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0
2220 ; CHECK-SD-NEXT: bic v2.4s, #255, lsl #8
2221 ; CHECK-SD-NEXT: bic v1.4s, #255, lsl #8
2222 ; CHECK-SD-NEXT: mov v0.16b, v2.16b
2223 ; CHECK-SD-NEXT: ret
2224 ;
2225 ; CHECK-GI-LABEL: bic_shifted_knownbits2:
2226 ; CHECK-GI: // %bb.0: // %entry
2227 ; CHECK-GI-NEXT: adrp x8, .LCPI145_0
2228 ; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0
2229 ; CHECK-GI-NEXT: ushll2 v2.4s, v0.8h, #0
2230 ; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI145_0]
2231 ; CHECK-GI-NEXT: and v0.16b, v1.16b, v3.16b
2232 ; CHECK-GI-NEXT: and v1.16b, v2.16b, v3.16b
2233 ; CHECK-GI-NEXT: ret
2234 entry:
2235 %vshr_n = zext <8 x i16> %v to <8 x i32>
2236 %and.i = and <8 x i32> %vshr_n, <i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975>
2237 ret <8 x i32> %and.i
2238 }
2240 define <8 x i32> @bic_shifted_knownbits3(<8 x i16> %v) {
2241 ; CHECK-SD-LABEL: bic_shifted_knownbits3:
2242 ; CHECK-SD: // %bb.0:
2243 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2244 ; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0
2245 ; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
2246 ; CHECK-SD-NEXT: ret
2247 ;
2248 ; CHECK-GI-LABEL: bic_shifted_knownbits3:
2249 ; CHECK-GI: // %bb.0:
2250 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
2251 ; CHECK-GI-NEXT: and v1.16b, v0.16b, v1.16b
2252 ; CHECK-GI-NEXT: ushll v0.4s, v1.4h, #0
2253 ; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0
2254 ; CHECK-GI-NEXT: ret
2255 %a = and <8 x i16> %v, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
2256 %and.i = zext <8 x i16> %a to <8 x i32>
2257 ret <8 x i32> %and.i
2258 }
2261 define <8 x i32> @bic_shifted_knownbits4(<8 x i32> %v) {
2262 ; CHECK-SD-LABEL: bic_shifted_knownbits4:
2263 ; CHECK-SD: // %bb.0: // %entry
2264 ; CHECK-SD-NEXT: shl v1.4s, v1.4s, #8
2265 ; CHECK-SD-NEXT: shl v0.4s, v0.4s, #8
2266 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
2267 ; CHECK-SD-NEXT: bic v1.4s, #255, lsl #8
2268 ; CHECK-SD-NEXT: ret
2269 ;
2270 ; CHECK-GI-LABEL: bic_shifted_knownbits4:
2271 ; CHECK-GI: // %bb.0: // %entry
2272 ; CHECK-GI-NEXT: movi v2.2d, #0xffff0000ffff0000
2273 ; CHECK-GI-NEXT: shl v0.4s, v0.4s, #8
2274 ; CHECK-GI-NEXT: shl v1.4s, v1.4s, #8
2275 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
2276 ; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
2277 ; CHECK-GI-NEXT: ret
2278 entry:
2279 %vshr_n = shl <8 x i32> %v, <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
2280 %and.i = and <8 x i32> %vshr_n, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
2281 ret <8 x i32> %and.i
2282 }
2284 define <8 x i8> @orr8imm2s_lsl0(<8 x i8> %a) {
2285 ; CHECK-SD-LABEL: orr8imm2s_lsl0:
2286 ; CHECK-SD: // %bb.0:
2287 ; CHECK-SD-NEXT: orr v0.2s, #255
2288 ; CHECK-SD-NEXT: ret
2289 ;
2290 ; CHECK-GI-LABEL: orr8imm2s_lsl0:
2291 ; CHECK-GI: // %bb.0:
2292 ; CHECK-GI-NEXT: adrp x8, .LCPI148_0
2293 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI148_0]
2294 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2295 ; CHECK-GI-NEXT: ret
2296 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
2297 ret <8 x i8> %tmp1
2298 }
2300 define <8 x i8> @orr8imm2s_lsl8(<8 x i8> %a) {
2301 ; CHECK-SD-LABEL: orr8imm2s_lsl8:
2302 ; CHECK-SD: // %bb.0:
2303 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
2304 ; CHECK-SD-NEXT: ret
2305 ;
2306 ; CHECK-GI-LABEL: orr8imm2s_lsl8:
2307 ; CHECK-GI: // %bb.0:
2308 ; CHECK-GI-NEXT: adrp x8, .LCPI149_0
2309 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI149_0]
2310 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2311 ; CHECK-GI-NEXT: ret
2312 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
2313 ret <8 x i8> %tmp1
2314 }
2316 define <8 x i8> @orr8imm2s_lsl16(<8 x i8> %a) {
2317 ; CHECK-SD-LABEL: orr8imm2s_lsl16:
2318 ; CHECK-SD: // %bb.0:
2319 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
2320 ; CHECK-SD-NEXT: ret
2321 ;
2322 ; CHECK-GI-LABEL: orr8imm2s_lsl16:
2323 ; CHECK-GI: // %bb.0:
2324 ; CHECK-GI-NEXT: adrp x8, .LCPI150_0
2325 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI150_0]
2326 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2327 ; CHECK-GI-NEXT: ret
2328 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
2329 ret <8 x i8> %tmp1
2330 }
2332 define <8 x i8> @orr8imm2s_lsl24(<8 x i8> %a) {
2333 ; CHECK-SD-LABEL: orr8imm2s_lsl24:
2334 ; CHECK-SD: // %bb.0:
2335 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
2336 ; CHECK-SD-NEXT: ret
2337 ;
2338 ; CHECK-GI-LABEL: orr8imm2s_lsl24:
2339 ; CHECK-GI: // %bb.0:
2340 ; CHECK-GI-NEXT: adrp x8, .LCPI151_0
2341 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI151_0]
2342 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2343 ; CHECK-GI-NEXT: ret
2344 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
2345 ret <8 x i8> %tmp1
2346 }
2348 define <4 x i16> @orr16imm2s_lsl0(<4 x i16> %a) {
2349 ; CHECK-SD-LABEL: orr16imm2s_lsl0:
2350 ; CHECK-SD: // %bb.0:
2351 ; CHECK-SD-NEXT: orr v0.2s, #255
2352 ; CHECK-SD-NEXT: ret
2353 ;
2354 ; CHECK-GI-LABEL: orr16imm2s_lsl0:
2355 ; CHECK-GI: // %bb.0:
2356 ; CHECK-GI-NEXT: adrp x8, .LCPI152_0
2357 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI152_0]
2358 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2359 ; CHECK-GI-NEXT: ret
2360 %tmp1 = or <4 x i16> %a, < i16 255, i16 0, i16 255, i16 0>
2361 ret <4 x i16> %tmp1
2362 }
2364 define <4 x i16> @orr16imm2s_lsl8(<4 x i16> %a) {
2365 ; CHECK-SD-LABEL: orr16imm2s_lsl8:
2366 ; CHECK-SD: // %bb.0:
2367 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
2368 ; CHECK-SD-NEXT: ret
2369 ;
2370 ; CHECK-GI-LABEL: orr16imm2s_lsl8:
2371 ; CHECK-GI: // %bb.0:
2372 ; CHECK-GI-NEXT: adrp x8, .LCPI153_0
2373 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI153_0]
2374 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2375 ; CHECK-GI-NEXT: ret
2376 %tmp1 = or <4 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0>
2377 ret <4 x i16> %tmp1
2378 }
2380 define <4 x i16> @orr16imm2s_lsl16(<4 x i16> %a) {
2381 ; CHECK-SD-LABEL: orr16imm2s_lsl16:
2382 ; CHECK-SD: // %bb.0:
2383 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
2384 ; CHECK-SD-NEXT: ret
2385 ;
2386 ; CHECK-GI-LABEL: orr16imm2s_lsl16:
2387 ; CHECK-GI: // %bb.0:
2388 ; CHECK-GI-NEXT: adrp x8, .LCPI154_0
2389 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI154_0]
2390 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2391 ; CHECK-GI-NEXT: ret
2392 %tmp1 = or <4 x i16> %a, < i16 0, i16 255, i16 0, i16 255>
2393 ret <4 x i16> %tmp1
2394 }
2396 define <4 x i16> @orr16imm2s_lsl24(<4 x i16> %a) {
2397 ; CHECK-SD-LABEL: orr16imm2s_lsl24:
2398 ; CHECK-SD: // %bb.0:
2399 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
2400 ; CHECK-SD-NEXT: ret
2401 ;
2402 ; CHECK-GI-LABEL: orr16imm2s_lsl24:
2403 ; CHECK-GI: // %bb.0:
2404 ; CHECK-GI-NEXT: adrp x8, .LCPI155_0
2405 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI155_0]
2406 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2407 ; CHECK-GI-NEXT: ret
2408 %tmp1 = or <4 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280>
2409 ret <4 x i16> %tmp1
2410 }
2412 define <1 x i64> @orr64imm2s_lsl0(<1 x i64> %a) {
2413 ; CHECK-SD-LABEL: orr64imm2s_lsl0:
2414 ; CHECK-SD: // %bb.0:
2415 ; CHECK-SD-NEXT: orr v0.2s, #255
2416 ; CHECK-SD-NEXT: ret
2417 ;
2418 ; CHECK-GI-LABEL: orr64imm2s_lsl0:
2419 ; CHECK-GI: // %bb.0:
2420 ; CHECK-GI-NEXT: fmov x8, d0
2421 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff
2422 ; CHECK-GI-NEXT: fmov d0, x8
2423 ; CHECK-GI-NEXT: ret
2424 %tmp1 = or <1 x i64> %a, < i64 1095216660735>
2425 ret <1 x i64> %tmp1
2426 }
2428 define <1 x i64> @orr64imm2s_lsl8(<1 x i64> %a) {
2429 ; CHECK-SD-LABEL: orr64imm2s_lsl8:
2430 ; CHECK-SD: // %bb.0:
2431 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
2432 ; CHECK-SD-NEXT: ret
2433 ;
2434 ; CHECK-GI-LABEL: orr64imm2s_lsl8:
2435 ; CHECK-GI: // %bb.0:
2436 ; CHECK-GI-NEXT: fmov x8, d0
2437 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff00
2438 ; CHECK-GI-NEXT: fmov d0, x8
2439 ; CHECK-GI-NEXT: ret
2440 %tmp1 = or <1 x i64> %a, < i64 280375465148160>
2441 ret <1 x i64> %tmp1
2442 }
2444 define <1 x i64> @orr64imm2s_lsl16(<1 x i64> %a) {
2445 ; CHECK-SD-LABEL: orr64imm2s_lsl16:
2446 ; CHECK-SD: // %bb.0:
2447 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
2448 ; CHECK-SD-NEXT: ret
2449 ;
2450 ; CHECK-GI-LABEL: orr64imm2s_lsl16:
2451 ; CHECK-GI: // %bb.0:
2452 ; CHECK-GI-NEXT: fmov x8, d0
2453 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff0000
2454 ; CHECK-GI-NEXT: fmov d0, x8
2455 ; CHECK-GI-NEXT: ret
2456 %tmp1 = or <1 x i64> %a, < i64 71776119077928960>
2457 ret <1 x i64> %tmp1
2458 }
2460 define <1 x i64> @orr64imm2s_lsl24(<1 x i64> %a) {
2461 ; CHECK-SD-LABEL: orr64imm2s_lsl24:
2462 ; CHECK-SD: // %bb.0:
2463 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
2464 ; CHECK-SD-NEXT: ret
2465 ;
2466 ; CHECK-GI-LABEL: orr64imm2s_lsl24:
2467 ; CHECK-GI: // %bb.0:
2468 ; CHECK-GI-NEXT: fmov x8, d0
2469 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff000000
2470 ; CHECK-GI-NEXT: fmov d0, x8
2471 ; CHECK-GI-NEXT: ret
2472 %tmp1 = or <1 x i64> %a, < i64 -72057589759737856>
2473 ret <1 x i64> %tmp1
2474 }
2476 define <16 x i8> @orr8imm4s_lsl0(<16 x i8> %a) {
2477 ; CHECK-SD-LABEL: orr8imm4s_lsl0:
2478 ; CHECK-SD: // %bb.0:
2479 ; CHECK-SD-NEXT: orr v0.4s, #255
2480 ; CHECK-SD-NEXT: ret
2481 ;
2482 ; CHECK-GI-LABEL: orr8imm4s_lsl0:
2483 ; CHECK-GI: // %bb.0:
2484 ; CHECK-GI-NEXT: adrp x8, .LCPI160_0
2485 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI160_0]
2486 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2487 ; CHECK-GI-NEXT: ret
2488 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
2489 ret <16 x i8> %tmp1
2490 }
2492 define <16 x i8> @orr8imm4s_lsl8(<16 x i8> %a) {
2493 ; CHECK-SD-LABEL: orr8imm4s_lsl8:
2494 ; CHECK-SD: // %bb.0:
2495 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
2496 ; CHECK-SD-NEXT: ret
2497 ;
2498 ; CHECK-GI-LABEL: orr8imm4s_lsl8:
2499 ; CHECK-GI: // %bb.0:
2500 ; CHECK-GI-NEXT: adrp x8, .LCPI161_0
2501 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI161_0]
2502 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2503 ; CHECK-GI-NEXT: ret
2504 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
2505 ret <16 x i8> %tmp1
2506 }
2508 define <16 x i8> @orr8imm4s_lsl16(<16 x i8> %a) {
2509 ; CHECK-SD-LABEL: orr8imm4s_lsl16:
2510 ; CHECK-SD: // %bb.0:
2511 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
2512 ; CHECK-SD-NEXT: ret
2513 ;
2514 ; CHECK-GI-LABEL: orr8imm4s_lsl16:
2515 ; CHECK-GI: // %bb.0:
2516 ; CHECK-GI-NEXT: adrp x8, .LCPI162_0
2517 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI162_0]
2518 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2519 ; CHECK-GI-NEXT: ret
2520 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
2521 ret <16 x i8> %tmp1
2522 }
2524 define <16 x i8> @orr8imm4s_lsl24(<16 x i8> %a) {
2525 ; CHECK-SD-LABEL: orr8imm4s_lsl24:
2526 ; CHECK-SD: // %bb.0:
2527 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
2528 ; CHECK-SD-NEXT: ret
2529 ;
2530 ; CHECK-GI-LABEL: orr8imm4s_lsl24:
2531 ; CHECK-GI: // %bb.0:
2532 ; CHECK-GI-NEXT: adrp x8, .LCPI163_0
2533 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI163_0]
2534 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2535 ; CHECK-GI-NEXT: ret
2536 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
2537 ret <16 x i8> %tmp1
2538 }
2540 define <8 x i16> @orr16imm4s_lsl0(<8 x i16> %a) {
2541 ; CHECK-SD-LABEL: orr16imm4s_lsl0:
2542 ; CHECK-SD: // %bb.0:
2543 ; CHECK-SD-NEXT: orr v0.4s, #255
2544 ; CHECK-SD-NEXT: ret
2545 ;
2546 ; CHECK-GI-LABEL: orr16imm4s_lsl0:
2547 ; CHECK-GI: // %bb.0:
2548 ; CHECK-GI-NEXT: adrp x8, .LCPI164_0
2549 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI164_0]
2550 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2551 ; CHECK-GI-NEXT: ret
2552 %tmp1 = or <8 x i16> %a, < i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0>
2553 ret <8 x i16> %tmp1
2554 }
2556 define <8 x i16> @orr16imm4s_lsl8(<8 x i16> %a) {
2557 ; CHECK-SD-LABEL: orr16imm4s_lsl8:
2558 ; CHECK-SD: // %bb.0:
2559 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
2560 ; CHECK-SD-NEXT: ret
2561 ;
2562 ; CHECK-GI-LABEL: orr16imm4s_lsl8:
2563 ; CHECK-GI: // %bb.0:
2564 ; CHECK-GI-NEXT: adrp x8, .LCPI165_0
2565 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI165_0]
2566 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2567 ; CHECK-GI-NEXT: ret
2568 %tmp1 = or <8 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0>
2569 ret <8 x i16> %tmp1
2570 }
2572 define <8 x i16> @orr16imm4s_lsl16(<8 x i16> %a) {
2573 ; CHECK-SD-LABEL: orr16imm4s_lsl16:
2574 ; CHECK-SD: // %bb.0:
2575 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
2576 ; CHECK-SD-NEXT: ret
2577 ;
2578 ; CHECK-GI-LABEL: orr16imm4s_lsl16:
2579 ; CHECK-GI: // %bb.0:
2580 ; CHECK-GI-NEXT: adrp x8, .LCPI166_0
2581 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI166_0]
2582 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2583 ; CHECK-GI-NEXT: ret
2584 %tmp1 = or <8 x i16> %a, < i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255>
2585 ret <8 x i16> %tmp1
2586 }
2588 define <8 x i16> @orr16imm4s_lsl24(<8 x i16> %a) {
2589 ; CHECK-SD-LABEL: orr16imm4s_lsl24:
2590 ; CHECK-SD: // %bb.0:
2591 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
2592 ; CHECK-SD-NEXT: ret
2593 ;
2594 ; CHECK-GI-LABEL: orr16imm4s_lsl24:
2595 ; CHECK-GI: // %bb.0:
2596 ; CHECK-GI-NEXT: adrp x8, .LCPI167_0
2597 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI167_0]
2598 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2599 ; CHECK-GI-NEXT: ret
2600 %tmp1 = or <8 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280>
2601 ret <8 x i16> %tmp1
2602 }
2604 define <2 x i64> @orr64imm4s_lsl0(<2 x i64> %a) {
2605 ; CHECK-SD-LABEL: orr64imm4s_lsl0:
2606 ; CHECK-SD: // %bb.0:
2607 ; CHECK-SD-NEXT: orr v0.4s, #255
2608 ; CHECK-SD-NEXT: ret
2609 ;
2610 ; CHECK-GI-LABEL: orr64imm4s_lsl0:
2611 ; CHECK-GI: // %bb.0:
2612 ; CHECK-GI-NEXT: movi v1.2d, #0x0000ff000000ff
2613 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2614 ; CHECK-GI-NEXT: ret
2615 %tmp1 = or <2 x i64> %a, < i64 1095216660735, i64 1095216660735>
2616 ret <2 x i64> %tmp1
2617 }
2619 define <2 x i64> @orr64imm4s_lsl8(<2 x i64> %a) {
2620 ; CHECK-SD-LABEL: orr64imm4s_lsl8:
2621 ; CHECK-SD: // %bb.0:
2622 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
2623 ; CHECK-SD-NEXT: ret
2624 ;
2625 ; CHECK-GI-LABEL: orr64imm4s_lsl8:
2626 ; CHECK-GI: // %bb.0:
2627 ; CHECK-GI-NEXT: movi v1.2d, #0x00ff000000ff00
2628 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2629 ; CHECK-GI-NEXT: ret
2630 %tmp1 = or <2 x i64> %a, < i64 280375465148160, i64 280375465148160>
2631 ret <2 x i64> %tmp1
2632 }
2634 define <2 x i64> @orr64imm4s_lsl16(<2 x i64> %a) {
2635 ; CHECK-SD-LABEL: orr64imm4s_lsl16:
2636 ; CHECK-SD: // %bb.0:
2637 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
2638 ; CHECK-SD-NEXT: ret
2639 ;
2640 ; CHECK-GI-LABEL: orr64imm4s_lsl16:
2641 ; CHECK-GI: // %bb.0:
2642 ; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff0000
2643 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2644 ; CHECK-GI-NEXT: ret
2645 %tmp1 = or <2 x i64> %a, < i64 71776119077928960, i64 71776119077928960>
2646 ret <2 x i64> %tmp1
2647 }
2649 define <2 x i64> @orr64imm4s_lsl24(<2 x i64> %a) {
2650 ; CHECK-SD-LABEL: orr64imm4s_lsl24:
2651 ; CHECK-SD: // %bb.0:
2652 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
2653 ; CHECK-SD-NEXT: ret
2654 ;
2655 ; CHECK-GI-LABEL: orr64imm4s_lsl24:
2656 ; CHECK-GI: // %bb.0:
2657 ; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff000000
2658 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2659 ; CHECK-GI-NEXT: ret
2660 %tmp1 = or <2 x i64> %a, < i64 -72057589759737856, i64 -72057589759737856>
2661 ret <2 x i64> %tmp1
2662 }
2664 define <8 x i8> @orr8imm4h_lsl0(<8 x i8> %a) {
2665 ; CHECK-SD-LABEL: orr8imm4h_lsl0:
2666 ; CHECK-SD: // %bb.0:
2667 ; CHECK-SD-NEXT: orr v0.4h, #255
2668 ; CHECK-SD-NEXT: ret
2669 ;
2670 ; CHECK-GI-LABEL: orr8imm4h_lsl0:
2671 ; CHECK-GI: // %bb.0:
2672 ; CHECK-GI-NEXT: adrp x8, .LCPI172_0
2673 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI172_0]
2674 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2675 ; CHECK-GI-NEXT: ret
2676 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
2677 ret <8 x i8> %tmp1
2678 }
2680 define <8 x i8> @orr8imm4h_lsl8(<8 x i8> %a) {
2681 ; CHECK-SD-LABEL: orr8imm4h_lsl8:
2682 ; CHECK-SD: // %bb.0:
2683 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
2684 ; CHECK-SD-NEXT: ret
2685 ;
2686 ; CHECK-GI-LABEL: orr8imm4h_lsl8:
2687 ; CHECK-GI: // %bb.0:
2688 ; CHECK-GI-NEXT: adrp x8, .LCPI173_0
2689 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI173_0]
2690 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2691 ; CHECK-GI-NEXT: ret
2692 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
2693 ret <8 x i8> %tmp1
2694 }
2696 define <2 x i32> @orr16imm4h_lsl0(<2 x i32> %a) {
2697 ; CHECK-SD-LABEL: orr16imm4h_lsl0:
2698 ; CHECK-SD: // %bb.0:
2699 ; CHECK-SD-NEXT: orr v0.4h, #255
2700 ; CHECK-SD-NEXT: ret
2701 ;
2702 ; CHECK-GI-LABEL: orr16imm4h_lsl0:
2703 ; CHECK-GI: // %bb.0:
2704 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
2705 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2706 ; CHECK-GI-NEXT: ret
2707 %tmp1 = or <2 x i32> %a, < i32 16711935, i32 16711935>
2708 ret <2 x i32> %tmp1
2709 }
2711 define <2 x i32> @orr16imm4h_lsl8(<2 x i32> %a) {
2712 ; CHECK-SD-LABEL: orr16imm4h_lsl8:
2713 ; CHECK-SD: // %bb.0:
2714 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
2715 ; CHECK-SD-NEXT: ret
2716 ;
2717 ; CHECK-GI-LABEL: orr16imm4h_lsl8:
2718 ; CHECK-GI: // %bb.0:
2719 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff00
2720 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2721 ; CHECK-GI-NEXT: ret
2722 %tmp1 = or <2 x i32> %a, < i32 4278255360, i32 4278255360>
2723 ret <2 x i32> %tmp1
2724 }
2726 define <1 x i64> @orr64imm4h_lsl0(<1 x i64> %a) {
2727 ; CHECK-SD-LABEL: orr64imm4h_lsl0:
2728 ; CHECK-SD: // %bb.0:
2729 ; CHECK-SD-NEXT: orr v0.4h, #255
2730 ; CHECK-SD-NEXT: ret
2731 ;
2732 ; CHECK-GI-LABEL: orr64imm4h_lsl0:
2733 ; CHECK-GI: // %bb.0:
2734 ; CHECK-GI-NEXT: fmov x8, d0
2735 ; CHECK-GI-NEXT: orr x8, x8, #0xff00ff00ff00ff
2736 ; CHECK-GI-NEXT: fmov d0, x8
2737 ; CHECK-GI-NEXT: ret
2738 %tmp1 = or <1 x i64> %a, < i64 71777214294589695>
2739 ret <1 x i64> %tmp1
2740 }
2742 define <1 x i64> @orr64imm4h_lsl8(<1 x i64> %a) {
2743 ; CHECK-SD-LABEL: orr64imm4h_lsl8:
2744 ; CHECK-SD: // %bb.0:
2745 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
2746 ; CHECK-SD-NEXT: ret
2747 ;
2748 ; CHECK-GI-LABEL: orr64imm4h_lsl8:
2749 ; CHECK-GI: // %bb.0:
2750 ; CHECK-GI-NEXT: fmov x8, d0
2751 ; CHECK-GI-NEXT: orr x8, x8, #0xff00ff00ff00ff00
2752 ; CHECK-GI-NEXT: fmov d0, x8
2753 ; CHECK-GI-NEXT: ret
2754 %tmp1 = or <1 x i64> %a, < i64 -71777214294589696>
2755 ret <1 x i64> %tmp1
2756 }
2758 define <16 x i8> @orr8imm8h_lsl0(<16 x i8> %a) {
2759 ; CHECK-SD-LABEL: orr8imm8h_lsl0:
2760 ; CHECK-SD: // %bb.0:
2761 ; CHECK-SD-NEXT: orr v0.8h, #255
2762 ; CHECK-SD-NEXT: ret
2763 ;
2764 ; CHECK-GI-LABEL: orr8imm8h_lsl0:
2765 ; CHECK-GI: // %bb.0:
2766 ; CHECK-GI-NEXT: adrp x8, .LCPI178_0
2767 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI178_0]
2768 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2769 ; CHECK-GI-NEXT: ret
2770 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
2771 ret <16 x i8> %tmp1
2772 }
2774 define <16 x i8> @orr8imm8h_lsl8(<16 x i8> %a) {
2775 ; CHECK-SD-LABEL: orr8imm8h_lsl8:
2776 ; CHECK-SD: // %bb.0:
2777 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
2778 ; CHECK-SD-NEXT: ret
2779 ;
2780 ; CHECK-GI-LABEL: orr8imm8h_lsl8:
2781 ; CHECK-GI: // %bb.0:
2782 ; CHECK-GI-NEXT: adrp x8, .LCPI179_0
2783 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI179_0]
2784 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2785 ; CHECK-GI-NEXT: ret
2786 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
2787 ret <16 x i8> %tmp1
2788 }
2790 define <4 x i32> @orr16imm8h_lsl0(<4 x i32> %a) {
2791 ; CHECK-SD-LABEL: orr16imm8h_lsl0:
2792 ; CHECK-SD: // %bb.0:
2793 ; CHECK-SD-NEXT: orr v0.8h, #255
2794 ; CHECK-SD-NEXT: ret
2795 ;
2796 ; CHECK-GI-LABEL: orr16imm8h_lsl0:
2797 ; CHECK-GI: // %bb.0:
2798 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
2799 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2800 ; CHECK-GI-NEXT: ret
2801 %tmp1 = or <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
2802 ret <4 x i32> %tmp1
2803 }
2805 define <4 x i32> @orr16imm8h_lsl8(<4 x i32> %a) {
2806 ; CHECK-SD-LABEL: orr16imm8h_lsl8:
2807 ; CHECK-SD: // %bb.0:
2808 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
2809 ; CHECK-SD-NEXT: ret
2810 ;
2811 ; CHECK-GI-LABEL: orr16imm8h_lsl8:
2812 ; CHECK-GI: // %bb.0:
2813 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
2814 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2815 ; CHECK-GI-NEXT: ret
2816 %tmp1 = or <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
2817 ret <4 x i32> %tmp1
2818 }
2820 define <2 x i64> @orr64imm8h_lsl0(<2 x i64> %a) {
2821 ; CHECK-SD-LABEL: orr64imm8h_lsl0:
2822 ; CHECK-SD: // %bb.0:
2823 ; CHECK-SD-NEXT: orr v0.8h, #255
2824 ; CHECK-SD-NEXT: ret
2825 ;
2826 ; CHECK-GI-LABEL: orr64imm8h_lsl0:
2827 ; CHECK-GI: // %bb.0:
2828 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
2829 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2830 ; CHECK-GI-NEXT: ret
2831 %tmp1 = or <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
2832 ret <2 x i64> %tmp1
2833 }
2835 define <2 x i64> @orr64imm8h_lsl8(<2 x i64> %a) {
2836 ; CHECK-SD-LABEL: orr64imm8h_lsl8:
2837 ; CHECK-SD: // %bb.0:
2838 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
2839 ; CHECK-SD-NEXT: ret
2840 ;
2841 ; CHECK-GI-LABEL: orr64imm8h_lsl8:
2842 ; CHECK-GI: // %bb.0:
2843 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
2844 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2845 ; CHECK-GI-NEXT: ret
2846 %tmp1 = or <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>
2847 ret <2 x i64> %tmp1
2848 }