| blob | f83ac8ed642cc124610e3b838ccc9a9b64061709 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple aarch64 -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3 ; RUN: llc < %s -mtriple aarch64 -o - -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
5 define <8 x i32> @extmuls_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1) {
6 ; CHECK-SD-LABEL: extmuls_v8i8_i32:
7 ; CHECK-SD: // %bb.0: // %entry
8 ; CHECK-SD-NEXT: smull v0.8h, v0.8b, v1.8b
9 ; CHECK-SD-NEXT: sshll2 v1.4s, v0.8h, #0
10 ; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
11 ; CHECK-SD-NEXT: ret
12 ;
13 ; CHECK-GI-LABEL: extmuls_v8i8_i32:
14 ; CHECK-GI: // %bb.0: // %entry
15 ; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0
16 ; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
17 ; CHECK-GI-NEXT: smull v0.4s, v2.4h, v1.4h
18 ; CHECK-GI-NEXT: smull2 v1.4s, v2.8h, v1.8h
19 ; CHECK-GI-NEXT: ret
20 entry:
21 %s0s = sext <8 x i8> %s0 to <8 x i32>
22 %s1s = sext <8 x i8> %s1 to <8 x i32>
23 %m = mul <8 x i32> %s0s, %s1s
24 ret <8 x i32> %m
25 }
27 define <8 x i32> @extmulu_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1) {
28 ; CHECK-SD-LABEL: extmulu_v8i8_i32:
29 ; CHECK-SD: // %bb.0: // %entry
30 ; CHECK-SD-NEXT: umull v0.8h, v0.8b, v1.8b
31 ; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0
32 ; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
33 ; CHECK-SD-NEXT: ret
34 ;
35 ; CHECK-GI-LABEL: extmulu_v8i8_i32:
36 ; CHECK-GI: // %bb.0: // %entry
37 ; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
38 ; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
39 ; CHECK-GI-NEXT: umull v0.4s, v2.4h, v1.4h
40 ; CHECK-GI-NEXT: umull2 v1.4s, v2.8h, v1.8h
41 ; CHECK-GI-NEXT: ret
42 entry:
43 %s0s = zext <8 x i8> %s0 to <8 x i32>
44 %s1s = zext <8 x i8> %s1 to <8 x i32>
45 %m = mul <8 x i32> %s0s, %s1s
46 ret <8 x i32> %m
47 }
49 define <8 x i32> @extmulsu_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1) {
50 ; CHECK-SD-LABEL: extmulsu_v8i8_i32:
51 ; CHECK-SD: // %bb.0: // %entry
52 ; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
53 ; CHECK-SD-NEXT: ushll v2.8h, v1.8b, #0
54 ; CHECK-SD-NEXT: smull2 v1.4s, v0.8h, v2.8h
55 ; CHECK-SD-NEXT: smull v0.4s, v0.4h, v2.4h
56 ; CHECK-SD-NEXT: ret
57 ;
58 ; CHECK-GI-LABEL: extmulsu_v8i8_i32:
59 ; CHECK-GI: // %bb.0: // %entry
60 ; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
61 ; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
62 ; CHECK-GI-NEXT: sshll v2.4s, v0.4h, #0
63 ; CHECK-GI-NEXT: sshll2 v3.4s, v0.8h, #0
64 ; CHECK-GI-NEXT: ushll v0.4s, v1.4h, #0
65 ; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0
66 ; CHECK-GI-NEXT: mul v0.4s, v2.4s, v0.4s
67 ; CHECK-GI-NEXT: mul v1.4s, v3.4s, v1.4s
68 ; CHECK-GI-NEXT: ret
69 entry:
70 %s0s = sext <8 x i8> %s0 to <8 x i32>
71 %s1s = zext <8 x i8> %s1 to <8 x i32>
72 %m = mul <8 x i32> %s0s, %s1s
73 ret <8 x i32> %m
74 }
76 define <8 x i32> @extmuladds_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1, <8 x i32> %b) {
77 ; CHECK-SD-LABEL: extmuladds_v8i8_i32:
78 ; CHECK-SD: // %bb.0: // %entry
79 ; CHECK-SD-NEXT: smull v0.8h, v0.8b, v1.8b
80 ; CHECK-SD-NEXT: saddw2 v1.4s, v3.4s, v0.8h
81 ; CHECK-SD-NEXT: saddw v0.4s, v2.4s, v0.4h
82 ; CHECK-SD-NEXT: ret
83 ;
84 ; CHECK-GI-LABEL: extmuladds_v8i8_i32:
85 ; CHECK-GI: // %bb.0: // %entry
86 ; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
87 ; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
88 ; CHECK-GI-NEXT: smlal v2.4s, v0.4h, v1.4h
89 ; CHECK-GI-NEXT: smlal2 v3.4s, v0.8h, v1.8h
90 ; CHECK-GI-NEXT: mov v0.16b, v2.16b
91 ; CHECK-GI-NEXT: mov v1.16b, v3.16b
92 ; CHECK-GI-NEXT: ret
93 entry:
94 %s0s = sext <8 x i8> %s0 to <8 x i32>
95 %s1s = sext <8 x i8> %s1 to <8 x i32>
96 %m = mul <8 x i32> %s0s, %s1s
97 %a = add <8 x i32> %m, %b
98 ret <8 x i32> %a
99 }
101 define <8 x i32> @extmuladdu_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1, <8 x i32> %b) {
102 ; CHECK-SD-LABEL: extmuladdu_v8i8_i32:
103 ; CHECK-SD: // %bb.0: // %entry
104 ; CHECK-SD-NEXT: umull v0.8h, v0.8b, v1.8b
105 ; CHECK-SD-NEXT: uaddw2 v1.4s, v3.4s, v0.8h
106 ; CHECK-SD-NEXT: uaddw v0.4s, v2.4s, v0.4h
107 ; CHECK-SD-NEXT: ret
108 ;
109 ; CHECK-GI-LABEL: extmuladdu_v8i8_i32:
110 ; CHECK-GI: // %bb.0: // %entry
111 ; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
112 ; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
113 ; CHECK-GI-NEXT: umlal v2.4s, v0.4h, v1.4h
114 ; CHECK-GI-NEXT: umlal2 v3.4s, v0.8h, v1.8h
115 ; CHECK-GI-NEXT: mov v0.16b, v2.16b
116 ; CHECK-GI-NEXT: mov v1.16b, v3.16b
117 ; CHECK-GI-NEXT: ret
118 entry:
119 %s0s = zext <8 x i8> %s0 to <8 x i32>
120 %s1s = zext <8 x i8> %s1 to <8 x i32>
121 %m = mul <8 x i32> %s0s, %s1s
122 %a = add <8 x i32> %m, %b
123 ret <8 x i32> %a
124 }
126 define <8 x i32> @extmuladdsu_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1, <8 x i32> %b) {
127 ; CHECK-SD-LABEL: extmuladdsu_v8i8_i32:
128 ; CHECK-SD: // %bb.0: // %entry
129 ; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0
130 ; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
131 ; CHECK-SD-NEXT: smlal2 v3.4s, v0.8h, v1.8h
132 ; CHECK-SD-NEXT: smlal v2.4s, v0.4h, v1.4h
133 ; CHECK-SD-NEXT: mov v0.16b, v2.16b
134 ; CHECK-SD-NEXT: mov v1.16b, v3.16b
135 ; CHECK-SD-NEXT: ret
136 ;
137 ; CHECK-GI-LABEL: extmuladdsu_v8i8_i32:
138 ; CHECK-GI: // %bb.0: // %entry
139 ; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
140 ; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
141 ; CHECK-GI-NEXT: sshll v4.4s, v0.4h, #0
142 ; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
143 ; CHECK-GI-NEXT: ushll v5.4s, v1.4h, #0
144 ; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0
145 ; CHECK-GI-NEXT: mla v2.4s, v4.4s, v5.4s
146 ; CHECK-GI-NEXT: mla v3.4s, v0.4s, v1.4s
147 ; CHECK-GI-NEXT: mov v0.16b, v2.16b
148 ; CHECK-GI-NEXT: mov v1.16b, v3.16b
149 ; CHECK-GI-NEXT: ret
150 entry:
151 %s0s = sext <8 x i8> %s0 to <8 x i32>
152 %s1s = zext <8 x i8> %s1 to <8 x i32>
153 %m = mul <8 x i32> %s0s, %s1s
154 %a = add <8 x i32> %m, %b
155 ret <8 x i32> %a
156 }
160 define <8 x i64> @extmuls_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1) {
161 ; CHECK-SD-LABEL: extmuls_v8i8_i64:
162 ; CHECK-SD: // %bb.0: // %entry
163 ; CHECK-SD-NEXT: smull v0.8h, v0.8b, v1.8b
164 ; CHECK-SD-NEXT: sshll v1.4s, v0.4h, #0
165 ; CHECK-SD-NEXT: sshll2 v2.4s, v0.8h, #0
166 ; CHECK-SD-NEXT: sshll v0.2d, v1.2s, #0
167 ; CHECK-SD-NEXT: sshll2 v3.2d, v2.4s, #0
168 ; CHECK-SD-NEXT: sshll2 v1.2d, v1.4s, #0
169 ; CHECK-SD-NEXT: sshll v2.2d, v2.2s, #0
170 ; CHECK-SD-NEXT: ret
171 ;
172 ; CHECK-GI-LABEL: extmuls_v8i8_i64:
173 ; CHECK-GI: // %bb.0: // %entry
174 ; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
175 ; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
176 ; CHECK-GI-NEXT: sshll v2.4s, v0.4h, #0
177 ; CHECK-GI-NEXT: sshll v3.4s, v1.4h, #0
178 ; CHECK-GI-NEXT: sshll2 v4.4s, v0.8h, #0
179 ; CHECK-GI-NEXT: sshll2 v5.4s, v1.8h, #0
180 ; CHECK-GI-NEXT: smull v0.2d, v2.2s, v3.2s
181 ; CHECK-GI-NEXT: smull2 v1.2d, v2.4s, v3.4s
182 ; CHECK-GI-NEXT: smull v2.2d, v4.2s, v5.2s
183 ; CHECK-GI-NEXT: smull2 v3.2d, v4.4s, v5.4s
184 ; CHECK-GI-NEXT: ret
185 entry:
186 %s0s = sext <8 x i8> %s0 to <8 x i64>
187 %s1s = sext <8 x i8> %s1 to <8 x i64>
188 %m = mul <8 x i64> %s0s, %s1s
189 ret <8 x i64> %m
190 }
192 define <8 x i64> @extmulu_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1) {
193 ; CHECK-SD-LABEL: extmulu_v8i8_i64:
194 ; CHECK-SD: // %bb.0: // %entry
195 ; CHECK-SD-NEXT: umull v0.8h, v0.8b, v1.8b
196 ; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0
197 ; CHECK-SD-NEXT: ushll2 v2.4s, v0.8h, #0
198 ; CHECK-SD-NEXT: ushll v0.2d, v1.2s, #0
199 ; CHECK-SD-NEXT: ushll2 v3.2d, v2.4s, #0
200 ; CHECK-SD-NEXT: ushll2 v1.2d, v1.4s, #0
201 ; CHECK-SD-NEXT: ushll v2.2d, v2.2s, #0
202 ; CHECK-SD-NEXT: ret
203 ;
204 ; CHECK-GI-LABEL: extmulu_v8i8_i64:
205 ; CHECK-GI: // %bb.0: // %entry
206 ; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
207 ; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
208 ; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0
209 ; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0
210 ; CHECK-GI-NEXT: ushll2 v4.4s, v0.8h, #0
211 ; CHECK-GI-NEXT: ushll2 v5.4s, v1.8h, #0
212 ; CHECK-GI-NEXT: umull v0.2d, v2.2s, v3.2s
213 ; CHECK-GI-NEXT: umull2 v1.2d, v2.4s, v3.4s
214 ; CHECK-GI-NEXT: umull v2.2d, v4.2s, v5.2s
215 ; CHECK-GI-NEXT: umull2 v3.2d, v4.4s, v5.4s
216 ; CHECK-GI-NEXT: ret
217 entry:
218 %s0s = zext <8 x i8> %s0 to <8 x i64>
219 %s1s = zext <8 x i8> %s1 to <8 x i64>
220 %m = mul <8 x i64> %s0s, %s1s
221 ret <8 x i64> %m
222 }
224 define <8 x i64> @extaddsu_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1) {
225 ; CHECK-SD-LABEL: extaddsu_v8i8_i64:
226 ; CHECK-SD: // %bb.0: // %entry
227 ; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
228 ; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0
229 ; CHECK-SD-NEXT: sshll v2.4s, v0.4h, #0
230 ; CHECK-SD-NEXT: ushll v4.4s, v1.4h, #0
231 ; CHECK-SD-NEXT: sshll2 v5.4s, v0.8h, #0
232 ; CHECK-SD-NEXT: ushll2 v6.4s, v1.8h, #0
233 ; CHECK-SD-NEXT: smull v0.2d, v2.2s, v4.2s
234 ; CHECK-SD-NEXT: smull2 v1.2d, v2.4s, v4.4s
235 ; CHECK-SD-NEXT: smull2 v3.2d, v5.4s, v6.4s
236 ; CHECK-SD-NEXT: smull v2.2d, v5.2s, v6.2s
237 ; CHECK-SD-NEXT: ret
238 ;
239 ; CHECK-GI-LABEL: extaddsu_v8i8_i64:
240 ; CHECK-GI: // %bb.0: // %entry
241 ; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
242 ; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
243 ; CHECK-GI-NEXT: sshll v2.4s, v0.4h, #0
244 ; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0
245 ; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
246 ; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0
247 ; CHECK-GI-NEXT: sshll v4.2d, v2.2s, #0
248 ; CHECK-GI-NEXT: ushll v5.2d, v3.2s, #0
249 ; CHECK-GI-NEXT: sshll2 v2.2d, v2.4s, #0
250 ; CHECK-GI-NEXT: ushll2 v3.2d, v3.4s, #0
251 ; CHECK-GI-NEXT: sshll v6.2d, v0.2s, #0
252 ; CHECK-GI-NEXT: ushll v7.2d, v1.2s, #0
253 ; CHECK-GI-NEXT: sshll2 v0.2d, v0.4s, #0
254 ; CHECK-GI-NEXT: ushll2 v1.2d, v1.4s, #0
255 ; CHECK-GI-NEXT: fmov x8, d4
256 ; CHECK-GI-NEXT: fmov x9, d5
257 ; CHECK-GI-NEXT: mov x12, v4.d[1]
258 ; CHECK-GI-NEXT: fmov x10, d3
259 ; CHECK-GI-NEXT: fmov x11, d7
260 ; CHECK-GI-NEXT: mov x13, v5.d[1]
261 ; CHECK-GI-NEXT: fmov x14, d1
262 ; CHECK-GI-NEXT: mov x15, v2.d[1]
263 ; CHECK-GI-NEXT: mov x16, v3.d[1]
264 ; CHECK-GI-NEXT: mul x8, x8, x9
265 ; CHECK-GI-NEXT: fmov x9, d2
266 ; CHECK-GI-NEXT: mov x17, v7.d[1]
267 ; CHECK-GI-NEXT: mov x18, v1.d[1]
268 ; CHECK-GI-NEXT: mul x12, x12, x13
269 ; CHECK-GI-NEXT: mov x13, v0.d[1]
270 ; CHECK-GI-NEXT: mul x9, x9, x10
271 ; CHECK-GI-NEXT: fmov x10, d6
272 ; CHECK-GI-NEXT: mul x15, x15, x16
273 ; CHECK-GI-NEXT: mul x10, x10, x11
274 ; CHECK-GI-NEXT: fmov x11, d0
275 ; CHECK-GI-NEXT: mov v0.d[0], x8
276 ; CHECK-GI-NEXT: mov v1.d[0], x9
277 ; CHECK-GI-NEXT: mul x13, x13, x18
278 ; CHECK-GI-NEXT: mul x11, x11, x14
279 ; CHECK-GI-NEXT: mov x14, v6.d[1]
280 ; CHECK-GI-NEXT: mov v0.d[1], x12
281 ; CHECK-GI-NEXT: mov v2.d[0], x10
282 ; CHECK-GI-NEXT: mov v1.d[1], x15
283 ; CHECK-GI-NEXT: mul x14, x14, x17
284 ; CHECK-GI-NEXT: mov v3.d[0], x11
285 ; CHECK-GI-NEXT: mov v2.d[1], x14
286 ; CHECK-GI-NEXT: mov v3.d[1], x13
287 ; CHECK-GI-NEXT: ret
288 entry:
289 %s0s = sext <8 x i8> %s0 to <8 x i64>
290 %s1s = zext <8 x i8> %s1 to <8 x i64>
291 %m = mul <8 x i64> %s0s, %s1s
292 ret <8 x i64> %m
293 }
295 define <8 x i64> @extmuladds_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1, <8 x i64> %b) {
296 ; CHECK-SD-LABEL: extmuladds_v8i8_i64:
297 ; CHECK-SD: // %bb.0: // %entry
298 ; CHECK-SD-NEXT: smull v0.8h, v0.8b, v1.8b
299 ; CHECK-SD-NEXT: sshll2 v6.4s, v0.8h, #0
300 ; CHECK-SD-NEXT: sshll v1.4s, v0.4h, #0
301 ; CHECK-SD-NEXT: saddw2 v5.2d, v5.2d, v6.4s
302 ; CHECK-SD-NEXT: saddw v0.2d, v2.2d, v1.2s
303 ; CHECK-SD-NEXT: saddw2 v1.2d, v3.2d, v1.4s
304 ; CHECK-SD-NEXT: saddw v2.2d, v4.2d, v6.2s
305 ; CHECK-SD-NEXT: mov v3.16b, v5.16b
306 ; CHECK-SD-NEXT: ret
307 ;
308 ; CHECK-GI-LABEL: extmuladds_v8i8_i64:
309 ; CHECK-GI: // %bb.0: // %entry
310 ; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
311 ; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
312 ; CHECK-GI-NEXT: sshll v6.4s, v0.4h, #0
313 ; CHECK-GI-NEXT: sshll v7.4s, v1.4h, #0
314 ; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
315 ; CHECK-GI-NEXT: sshll2 v1.4s, v1.8h, #0
316 ; CHECK-GI-NEXT: smlal v2.2d, v6.2s, v7.2s
317 ; CHECK-GI-NEXT: smlal2 v3.2d, v6.4s, v7.4s
318 ; CHECK-GI-NEXT: smlal v4.2d, v0.2s, v1.2s
319 ; CHECK-GI-NEXT: smlal2 v5.2d, v0.4s, v1.4s
320 ; CHECK-GI-NEXT: mov v0.16b, v2.16b
321 ; CHECK-GI-NEXT: mov v1.16b, v3.16b
322 ; CHECK-GI-NEXT: mov v2.16b, v4.16b
323 ; CHECK-GI-NEXT: mov v3.16b, v5.16b
324 ; CHECK-GI-NEXT: ret
325 entry:
326 %s0s = sext <8 x i8> %s0 to <8 x i64>
327 %s1s = sext <8 x i8> %s1 to <8 x i64>
328 %m = mul <8 x i64> %s0s, %s1s
329 %a = add <8 x i64> %m, %b
330 ret <8 x i64> %a
331 }
333 define <8 x i64> @extmuladdu_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1, <8 x i64> %b) {
334 ; CHECK-SD-LABEL: extmuladdu_v8i8_i64:
335 ; CHECK-SD: // %bb.0: // %entry
336 ; CHECK-SD-NEXT: umull v0.8h, v0.8b, v1.8b
337 ; CHECK-SD-NEXT: ushll2 v6.4s, v0.8h, #0
338 ; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0
339 ; CHECK-SD-NEXT: uaddw2 v5.2d, v5.2d, v6.4s
340 ; CHECK-SD-NEXT: uaddw v0.2d, v2.2d, v1.2s
341 ; CHECK-SD-NEXT: uaddw2 v1.2d, v3.2d, v1.4s
342 ; CHECK-SD-NEXT: uaddw v2.2d, v4.2d, v6.2s
343 ; CHECK-SD-NEXT: mov v3.16b, v5.16b
344 ; CHECK-SD-NEXT: ret
345 ;
346 ; CHECK-GI-LABEL: extmuladdu_v8i8_i64:
347 ; CHECK-GI: // %bb.0: // %entry
348 ; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
349 ; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
350 ; CHECK-GI-NEXT: ushll v6.4s, v0.4h, #0
351 ; CHECK-GI-NEXT: ushll v7.4s, v1.4h, #0
352 ; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
353 ; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0
354 ; CHECK-GI-NEXT: umlal v2.2d, v6.2s, v7.2s
355 ; CHECK-GI-NEXT: umlal2 v3.2d, v6.4s, v7.4s
356 ; CHECK-GI-NEXT: umlal v4.2d, v0.2s, v1.2s
357 ; CHECK-GI-NEXT: umlal2 v5.2d, v0.4s, v1.4s
358 ; CHECK-GI-NEXT: mov v0.16b, v2.16b
359 ; CHECK-GI-NEXT: mov v1.16b, v3.16b
360 ; CHECK-GI-NEXT: mov v2.16b, v4.16b
361 ; CHECK-GI-NEXT: mov v3.16b, v5.16b
362 ; CHECK-GI-NEXT: ret
363 entry:
364 %s0s = zext <8 x i8> %s0 to <8 x i64>
365 %s1s = zext <8 x i8> %s1 to <8 x i64>
366 %m = mul <8 x i64> %s0s, %s1s
367 %a = add <8 x i64> %m, %b
368 ret <8 x i64> %a
369 }
371 define <8 x i64> @extmuladdsu_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1, <8 x i64> %b) {
372 ; CHECK-SD-LABEL: extmuladdsu_v8i8_i64:
373 ; CHECK-SD: // %bb.0: // %entry
374 ; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
375 ; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0
376 ; CHECK-SD-NEXT: sshll v6.4s, v0.4h, #0
377 ; CHECK-SD-NEXT: ushll v7.4s, v1.4h, #0
378 ; CHECK-SD-NEXT: sshll2 v0.4s, v0.8h, #0
379 ; CHECK-SD-NEXT: ushll2 v1.4s, v1.8h, #0
380 ; CHECK-SD-NEXT: smlal v2.2d, v6.2s, v7.2s
381 ; CHECK-SD-NEXT: smlal2 v3.2d, v6.4s, v7.4s
382 ; CHECK-SD-NEXT: smlal2 v5.2d, v0.4s, v1.4s
383 ; CHECK-SD-NEXT: smlal v4.2d, v0.2s, v1.2s
384 ; CHECK-SD-NEXT: mov v0.16b, v2.16b
385 ; CHECK-SD-NEXT: mov v1.16b, v3.16b
386 ; CHECK-SD-NEXT: mov v2.16b, v4.16b
387 ; CHECK-SD-NEXT: mov v3.16b, v5.16b
388 ; CHECK-SD-NEXT: ret
389 ;
390 ; CHECK-GI-LABEL: extmuladdsu_v8i8_i64:
391 ; CHECK-GI: // %bb.0: // %entry
392 ; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
393 ; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
394 ; CHECK-GI-NEXT: sshll v6.4s, v0.4h, #0
395 ; CHECK-GI-NEXT: ushll v7.4s, v1.4h, #0
396 ; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
397 ; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0
398 ; CHECK-GI-NEXT: sshll v16.2d, v6.2s, #0
399 ; CHECK-GI-NEXT: ushll v17.2d, v7.2s, #0
400 ; CHECK-GI-NEXT: sshll2 v6.2d, v6.4s, #0
401 ; CHECK-GI-NEXT: ushll2 v7.2d, v7.4s, #0
402 ; CHECK-GI-NEXT: sshll v18.2d, v0.2s, #0
403 ; CHECK-GI-NEXT: ushll v19.2d, v1.2s, #0
404 ; CHECK-GI-NEXT: sshll2 v0.2d, v0.4s, #0
405 ; CHECK-GI-NEXT: ushll2 v1.2d, v1.4s, #0
406 ; CHECK-GI-NEXT: fmov x8, d16
407 ; CHECK-GI-NEXT: fmov x9, d17
408 ; CHECK-GI-NEXT: mov x12, v16.d[1]
409 ; CHECK-GI-NEXT: fmov x10, d7
410 ; CHECK-GI-NEXT: fmov x11, d19
411 ; CHECK-GI-NEXT: mov x13, v17.d[1]
412 ; CHECK-GI-NEXT: fmov x14, d1
413 ; CHECK-GI-NEXT: mov x15, v6.d[1]
414 ; CHECK-GI-NEXT: mov x16, v7.d[1]
415 ; CHECK-GI-NEXT: mul x8, x8, x9
416 ; CHECK-GI-NEXT: fmov x9, d6
417 ; CHECK-GI-NEXT: mov x17, v19.d[1]
418 ; CHECK-GI-NEXT: mov x18, v1.d[1]
419 ; CHECK-GI-NEXT: mul x12, x12, x13
420 ; CHECK-GI-NEXT: mov x13, v0.d[1]
421 ; CHECK-GI-NEXT: mul x9, x9, x10
422 ; CHECK-GI-NEXT: fmov x10, d18
423 ; CHECK-GI-NEXT: mul x15, x15, x16
424 ; CHECK-GI-NEXT: mul x10, x10, x11
425 ; CHECK-GI-NEXT: fmov x11, d0
426 ; CHECK-GI-NEXT: mov v0.d[0], x8
427 ; CHECK-GI-NEXT: mov v1.d[0], x9
428 ; CHECK-GI-NEXT: mul x13, x13, x18
429 ; CHECK-GI-NEXT: mul x11, x11, x14
430 ; CHECK-GI-NEXT: mov x14, v18.d[1]
431 ; CHECK-GI-NEXT: mov v0.d[1], x12
432 ; CHECK-GI-NEXT: mov v6.d[0], x10
433 ; CHECK-GI-NEXT: mov v1.d[1], x15
434 ; CHECK-GI-NEXT: mul x14, x14, x17
435 ; CHECK-GI-NEXT: add v0.2d, v0.2d, v2.2d
436 ; CHECK-GI-NEXT: mov v7.d[0], x11
437 ; CHECK-GI-NEXT: add v1.2d, v1.2d, v3.2d
438 ; CHECK-GI-NEXT: mov v6.d[1], x14
439 ; CHECK-GI-NEXT: mov v7.d[1], x13
440 ; CHECK-GI-NEXT: add v2.2d, v6.2d, v4.2d
441 ; CHECK-GI-NEXT: add v3.2d, v7.2d, v5.2d
442 ; CHECK-GI-NEXT: ret
443 entry:
444 %s0s = sext <8 x i8> %s0 to <8 x i64>
445 %s1s = zext <8 x i8> %s1 to <8 x i64>
446 %m = mul <8 x i64> %s0s, %s1s
447 %a = add <8 x i64> %m, %b
448 ret <8 x i64> %a
449 }
450 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
451 ; CHECK: {{.*}}