| blob | 752c2cd34bfe488f0c3b942d42aea4555a478e77 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
3 ; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
4 ; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
6 target triple = "aarch64-unknown-linux-gnu"
8 ;
9 ; UADDV
10 ;
12 ; Don't use SVE for 64-bit vectors.
13 define i8 @uaddv_v8i8(<8 x i8> %a) vscale_range(2,0) #0 {
14 ; CHECK-LABEL: uaddv_v8i8:
15 ; CHECK: // %bb.0:
16 ; CHECK-NEXT: addv b0, v0.8b
17 ; CHECK-NEXT: fmov w0, s0
18 ; CHECK-NEXT: ret
19 %res = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %a)
20 ret i8 %res
21 }
23 ; Don't use SVE for 128-bit vectors.
24 define i8 @uaddv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 {
25 ; CHECK-LABEL: uaddv_v16i8:
26 ; CHECK: // %bb.0:
27 ; CHECK-NEXT: addv b0, v0.16b
28 ; CHECK-NEXT: fmov w0, s0
29 ; CHECK-NEXT: ret
30 %res = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %a)
31 ret i8 %res
32 }
34 define i8 @uaddv_v32i8(ptr %a) vscale_range(2,0) #0 {
35 ; CHECK-LABEL: uaddv_v32i8:
36 ; CHECK: // %bb.0:
37 ; CHECK-NEXT: ptrue p0.b, vl32
38 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
39 ; CHECK-NEXT: uaddv d0, p0, z0.b
40 ; CHECK-NEXT: fmov x0, d0
41 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
42 ; CHECK-NEXT: ret
43 %op = load <32 x i8>, ptr %a
44 %res = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %op)
45 ret i8 %res
46 }
48 define i8 @uaddv_v64i8(ptr %a) #0 {
49 ; VBITS_GE_256-LABEL: uaddv_v64i8:
50 ; VBITS_GE_256: // %bb.0:
51 ; VBITS_GE_256-NEXT: ptrue p0.b, vl32
52 ; VBITS_GE_256-NEXT: mov w8, #32 // =0x20
53 ; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
54 ; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x0]
55 ; VBITS_GE_256-NEXT: add z0.b, z1.b, z0.b
56 ; VBITS_GE_256-NEXT: uaddv d0, p0, z0.b
57 ; VBITS_GE_256-NEXT: fmov x0, d0
58 ; VBITS_GE_256-NEXT: // kill: def $w0 killed $w0 killed $x0
59 ; VBITS_GE_256-NEXT: ret
60 ;
61 ; VBITS_GE_512-LABEL: uaddv_v64i8:
62 ; VBITS_GE_512: // %bb.0:
63 ; VBITS_GE_512-NEXT: ptrue p0.b, vl64
64 ; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]
65 ; VBITS_GE_512-NEXT: uaddv d0, p0, z0.b
66 ; VBITS_GE_512-NEXT: fmov x0, d0
67 ; VBITS_GE_512-NEXT: // kill: def $w0 killed $w0 killed $x0
68 ; VBITS_GE_512-NEXT: ret
69 %op = load <64 x i8>, ptr %a
70 %res = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> %op)
71 ret i8 %res
72 }
74 define i8 @uaddv_v128i8(ptr %a) vscale_range(8,0) #0 {
75 ; CHECK-LABEL: uaddv_v128i8:
76 ; CHECK: // %bb.0:
77 ; CHECK-NEXT: ptrue p0.b, vl128
78 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
79 ; CHECK-NEXT: uaddv d0, p0, z0.b
80 ; CHECK-NEXT: fmov x0, d0
81 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
82 ; CHECK-NEXT: ret
83 %op = load <128 x i8>, ptr %a
84 %res = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %op)
85 ret i8 %res
86 }
88 define i8 @uaddv_v256i8(ptr %a) vscale_range(16,0) #0 {
89 ; CHECK-LABEL: uaddv_v256i8:
90 ; CHECK: // %bb.0:
91 ; CHECK-NEXT: ptrue p0.b, vl256
92 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
93 ; CHECK-NEXT: uaddv d0, p0, z0.b
94 ; CHECK-NEXT: fmov x0, d0
95 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
96 ; CHECK-NEXT: ret
97 %op = load <256 x i8>, ptr %a
98 %res = call i8 @llvm.vector.reduce.add.v256i8(<256 x i8> %op)
99 ret i8 %res
100 }
102 ; Don't use SVE for 64-bit vectors.
103 define i16 @uaddv_v4i16(<4 x i16> %a) vscale_range(2,0) #0 {
104 ; CHECK-LABEL: uaddv_v4i16:
105 ; CHECK: // %bb.0:
106 ; CHECK-NEXT: addv h0, v0.4h
107 ; CHECK-NEXT: fmov w0, s0
108 ; CHECK-NEXT: ret
109 %res = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %a)
110 ret i16 %res
111 }
113 ; Don't use SVE for 128-bit vectors.
114 define i16 @uaddv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 {
115 ; CHECK-LABEL: uaddv_v8i16:
116 ; CHECK: // %bb.0:
117 ; CHECK-NEXT: addv h0, v0.8h
118 ; CHECK-NEXT: fmov w0, s0
119 ; CHECK-NEXT: ret
120 %res = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %a)
121 ret i16 %res
122 }
124 define i16 @uaddv_v16i16(ptr %a) vscale_range(2,0) #0 {
125 ; CHECK-LABEL: uaddv_v16i16:
126 ; CHECK: // %bb.0:
127 ; CHECK-NEXT: ptrue p0.h, vl16
128 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
129 ; CHECK-NEXT: uaddv d0, p0, z0.h
130 ; CHECK-NEXT: fmov x0, d0
131 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
132 ; CHECK-NEXT: ret
133 %op = load <16 x i16>, ptr %a
134 %res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %op)
135 ret i16 %res
136 }
138 define i16 @uaddv_v32i16(ptr %a) #0 {
139 ; VBITS_GE_256-LABEL: uaddv_v32i16:
140 ; VBITS_GE_256: // %bb.0:
141 ; VBITS_GE_256-NEXT: ptrue p0.h, vl16
142 ; VBITS_GE_256-NEXT: mov x8, #16 // =0x10
143 ; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
144 ; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]
145 ; VBITS_GE_256-NEXT: add z0.h, z1.h, z0.h
146 ; VBITS_GE_256-NEXT: uaddv d0, p0, z0.h
147 ; VBITS_GE_256-NEXT: fmov x0, d0
148 ; VBITS_GE_256-NEXT: // kill: def $w0 killed $w0 killed $x0
149 ; VBITS_GE_256-NEXT: ret
150 ;
151 ; VBITS_GE_512-LABEL: uaddv_v32i16:
152 ; VBITS_GE_512: // %bb.0:
153 ; VBITS_GE_512-NEXT: ptrue p0.h, vl32
154 ; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
155 ; VBITS_GE_512-NEXT: uaddv d0, p0, z0.h
156 ; VBITS_GE_512-NEXT: fmov x0, d0
157 ; VBITS_GE_512-NEXT: // kill: def $w0 killed $w0 killed $x0
158 ; VBITS_GE_512-NEXT: ret
159 %op = load <32 x i16>, ptr %a
160 %res = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> %op)
161 ret i16 %res
162 }
164 define i16 @uaddv_v64i16(ptr %a) vscale_range(8,0) #0 {
165 ; CHECK-LABEL: uaddv_v64i16:
166 ; CHECK: // %bb.0:
167 ; CHECK-NEXT: ptrue p0.h, vl64
168 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
169 ; CHECK-NEXT: uaddv d0, p0, z0.h
170 ; CHECK-NEXT: fmov x0, d0
171 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
172 ; CHECK-NEXT: ret
173 %op = load <64 x i16>, ptr %a
174 %res = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> %op)
175 ret i16 %res
176 }
178 define i16 @uaddv_v128i16(ptr %a) vscale_range(16,0) #0 {
179 ; CHECK-LABEL: uaddv_v128i16:
180 ; CHECK: // %bb.0:
181 ; CHECK-NEXT: ptrue p0.h, vl128
182 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
183 ; CHECK-NEXT: uaddv d0, p0, z0.h
184 ; CHECK-NEXT: fmov x0, d0
185 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
186 ; CHECK-NEXT: ret
187 %op = load <128 x i16>, ptr %a
188 %res = call i16 @llvm.vector.reduce.add.v128i16(<128 x i16> %op)
189 ret i16 %res
190 }
192 ; Don't use SVE for 64-bit vectors.
193 define i32 @uaddv_v2i32(<2 x i32> %a) vscale_range(2,0) #0 {
194 ; CHECK-LABEL: uaddv_v2i32:
195 ; CHECK: // %bb.0:
196 ; CHECK-NEXT: addp v0.2s, v0.2s, v0.2s
197 ; CHECK-NEXT: fmov w0, s0
198 ; CHECK-NEXT: ret
199 %res = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %a)
200 ret i32 %res
201 }
203 ; Don't use SVE for 128-bit vectors.
204 define i32 @uaddv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 {
205 ; CHECK-LABEL: uaddv_v4i32:
206 ; CHECK: // %bb.0:
207 ; CHECK-NEXT: addv s0, v0.4s
208 ; CHECK-NEXT: fmov w0, s0
209 ; CHECK-NEXT: ret
210 %res = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)
211 ret i32 %res
212 }
214 define i32 @uaddv_v8i32(ptr %a) vscale_range(2,0) #0 {
215 ; CHECK-LABEL: uaddv_v8i32:
216 ; CHECK: // %bb.0:
217 ; CHECK-NEXT: ptrue p0.s, vl8
218 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
219 ; CHECK-NEXT: uaddv d0, p0, z0.s
220 ; CHECK-NEXT: fmov x0, d0
221 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
222 ; CHECK-NEXT: ret
223 %op = load <8 x i32>, ptr %a
224 %res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %op)
225 ret i32 %res
226 }
228 define i32 @uaddv_v16i32(ptr %a) #0 {
229 ; VBITS_GE_256-LABEL: uaddv_v16i32:
230 ; VBITS_GE_256: // %bb.0:
231 ; VBITS_GE_256-NEXT: ptrue p0.s, vl8
232 ; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
233 ; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
234 ; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]
235 ; VBITS_GE_256-NEXT: add z0.s, z1.s, z0.s
236 ; VBITS_GE_256-NEXT: uaddv d0, p0, z0.s
237 ; VBITS_GE_256-NEXT: fmov x0, d0
238 ; VBITS_GE_256-NEXT: // kill: def $w0 killed $w0 killed $x0
239 ; VBITS_GE_256-NEXT: ret
240 ;
241 ; VBITS_GE_512-LABEL: uaddv_v16i32:
242 ; VBITS_GE_512: // %bb.0:
243 ; VBITS_GE_512-NEXT: ptrue p0.s, vl16
244 ; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
245 ; VBITS_GE_512-NEXT: uaddv d0, p0, z0.s
246 ; VBITS_GE_512-NEXT: fmov x0, d0
247 ; VBITS_GE_512-NEXT: // kill: def $w0 killed $w0 killed $x0
248 ; VBITS_GE_512-NEXT: ret
249 %op = load <16 x i32>, ptr %a
250 %res = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %op)
251 ret i32 %res
252 }
254 define i32 @uaddv_v32i32(ptr %a) vscale_range(8,0) #0 {
255 ; CHECK-LABEL: uaddv_v32i32:
256 ; CHECK: // %bb.0:
257 ; CHECK-NEXT: ptrue p0.s, vl32
258 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
259 ; CHECK-NEXT: uaddv d0, p0, z0.s
260 ; CHECK-NEXT: fmov x0, d0
261 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
262 ; CHECK-NEXT: ret
263 %op = load <32 x i32>, ptr %a
264 %res = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %op)
265 ret i32 %res
266 }
268 define i32 @uaddv_v64i32(ptr %a) vscale_range(16,0) #0 {
269 ; CHECK-LABEL: uaddv_v64i32:
270 ; CHECK: // %bb.0:
271 ; CHECK-NEXT: ptrue p0.s, vl64
272 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
273 ; CHECK-NEXT: uaddv d0, p0, z0.s
274 ; CHECK-NEXT: fmov x0, d0
275 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
276 ; CHECK-NEXT: ret
277 %op = load <64 x i32>, ptr %a
278 %res = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %op)
279 ret i32 %res
280 }
282 ; Nothing to do for single element vectors.
283 define i64 @uaddv_v1i64(<1 x i64> %a) vscale_range(2,0) #0 {
284 ; CHECK-LABEL: uaddv_v1i64:
285 ; CHECK: // %bb.0:
286 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
287 ; CHECK-NEXT: fmov x0, d0
288 ; CHECK-NEXT: ret
289 %res = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %a)
290 ret i64 %res
291 }
293 ; Don't use SVE for 128-bit vectors.
294 define i64 @uaddv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 {
295 ; CHECK-LABEL: uaddv_v2i64:
296 ; CHECK: // %bb.0:
297 ; CHECK-NEXT: addp d0, v0.2d
298 ; CHECK-NEXT: fmov x0, d0
299 ; CHECK-NEXT: ret
300 %res = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %a)
301 ret i64 %res
302 }
304 define i64 @uaddv_v4i64(ptr %a) vscale_range(2,0) #0 {
305 ; CHECK-LABEL: uaddv_v4i64:
306 ; CHECK: // %bb.0:
307 ; CHECK-NEXT: ptrue p0.d, vl4
308 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
309 ; CHECK-NEXT: uaddv d0, p0, z0.d
310 ; CHECK-NEXT: fmov x0, d0
311 ; CHECK-NEXT: ret
312 %op = load <4 x i64>, ptr %a
313 %res = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %op)
314 ret i64 %res
315 }
317 define i64 @uaddv_v8i64(ptr %a) #0 {
318 ; VBITS_GE_256-LABEL: uaddv_v8i64:
319 ; VBITS_GE_256: // %bb.0:
320 ; VBITS_GE_256-NEXT: ptrue p0.d, vl4
321 ; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
322 ; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
323 ; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]
324 ; VBITS_GE_256-NEXT: add z0.d, z1.d, z0.d
325 ; VBITS_GE_256-NEXT: uaddv d0, p0, z0.d
326 ; VBITS_GE_256-NEXT: fmov x0, d0
327 ; VBITS_GE_256-NEXT: ret
328 ;
329 ; VBITS_GE_512-LABEL: uaddv_v8i64:
330 ; VBITS_GE_512: // %bb.0:
331 ; VBITS_GE_512-NEXT: ptrue p0.d, vl8
332 ; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
333 ; VBITS_GE_512-NEXT: uaddv d0, p0, z0.d
334 ; VBITS_GE_512-NEXT: fmov x0, d0
335 ; VBITS_GE_512-NEXT: ret
336 %op = load <8 x i64>, ptr %a
337 %res = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %op)
338 ret i64 %res
339 }
341 define i64 @uaddv_v16i64(ptr %a) vscale_range(8,0) #0 {
342 ; CHECK-LABEL: uaddv_v16i64:
343 ; CHECK: // %bb.0:
344 ; CHECK-NEXT: ptrue p0.d, vl16
345 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
346 ; CHECK-NEXT: uaddv d0, p0, z0.d
347 ; CHECK-NEXT: fmov x0, d0
348 ; CHECK-NEXT: ret
349 %op = load <16 x i64>, ptr %a
350 %res = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %op)
351 ret i64 %res
352 }
354 define i64 @uaddv_v32i64(ptr %a) vscale_range(16,0) #0 {
355 ; CHECK-LABEL: uaddv_v32i64:
356 ; CHECK: // %bb.0:
357 ; CHECK-NEXT: ptrue p0.d, vl32
358 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
359 ; CHECK-NEXT: uaddv d0, p0, z0.d
360 ; CHECK-NEXT: fmov x0, d0
361 ; CHECK-NEXT: ret
362 %op = load <32 x i64>, ptr %a
363 %res = call i64 @llvm.vector.reduce.add.v32i64(<32 x i64> %op)
364 ret i64 %res
365 }
367 ;
368 ; SMAXV
369 ;
371 ; Don't use SVE for 64-bit vectors.
372 define i8 @smaxv_v8i8(<8 x i8> %a) vscale_range(2,0) #0 {
373 ; CHECK-LABEL: smaxv_v8i8:
374 ; CHECK: // %bb.0:
375 ; CHECK-NEXT: smaxv b0, v0.8b
376 ; CHECK-NEXT: fmov w0, s0
377 ; CHECK-NEXT: ret
378 %res = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> %a)
379 ret i8 %res
380 }
382 ; Don't use SVE for 128-bit vectors.
383 define i8 @smaxv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 {
384 ; CHECK-LABEL: smaxv_v16i8:
385 ; CHECK: // %bb.0:
386 ; CHECK-NEXT: smaxv b0, v0.16b
387 ; CHECK-NEXT: fmov w0, s0
388 ; CHECK-NEXT: ret
389 %res = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %a)
390 ret i8 %res
391 }
393 define i8 @smaxv_v32i8(ptr %a) vscale_range(2,0) #0 {
394 ; CHECK-LABEL: smaxv_v32i8:
395 ; CHECK: // %bb.0:
396 ; CHECK-NEXT: ptrue p0.b, vl32
397 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
398 ; CHECK-NEXT: smaxv b0, p0, z0.b
399 ; CHECK-NEXT: fmov w0, s0
400 ; CHECK-NEXT: ret
401 %op = load <32 x i8>, ptr %a
402 %res = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> %op)
403 ret i8 %res
404 }
406 define i8 @smaxv_v64i8(ptr %a) #0 {
407 ; VBITS_GE_256-LABEL: smaxv_v64i8:
408 ; VBITS_GE_256: // %bb.0:
409 ; VBITS_GE_256-NEXT: ptrue p0.b, vl32
410 ; VBITS_GE_256-NEXT: mov w8, #32 // =0x20
411 ; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
412 ; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x0]
413 ; VBITS_GE_256-NEXT: smax z0.b, p0/m, z0.b, z1.b
414 ; VBITS_GE_256-NEXT: smaxv b0, p0, z0.b
415 ; VBITS_GE_256-NEXT: fmov w0, s0
416 ; VBITS_GE_256-NEXT: ret
417 ;
418 ; VBITS_GE_512-LABEL: smaxv_v64i8:
419 ; VBITS_GE_512: // %bb.0:
420 ; VBITS_GE_512-NEXT: ptrue p0.b, vl64
421 ; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]
422 ; VBITS_GE_512-NEXT: smaxv b0, p0, z0.b
423 ; VBITS_GE_512-NEXT: fmov w0, s0
424 ; VBITS_GE_512-NEXT: ret
425 %op = load <64 x i8>, ptr %a
426 %res = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> %op)
427 ret i8 %res
428 }
430 define i8 @smaxv_v128i8(ptr %a) vscale_range(8,0) #0 {
431 ; CHECK-LABEL: smaxv_v128i8:
432 ; CHECK: // %bb.0:
433 ; CHECK-NEXT: ptrue p0.b, vl128
434 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
435 ; CHECK-NEXT: smaxv b0, p0, z0.b
436 ; CHECK-NEXT: fmov w0, s0
437 ; CHECK-NEXT: ret
438 %op = load <128 x i8>, ptr %a
439 %res = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> %op)
440 ret i8 %res
441 }
443 define i8 @smaxv_v256i8(ptr %a) vscale_range(16,0) #0 {
444 ; CHECK-LABEL: smaxv_v256i8:
445 ; CHECK: // %bb.0:
446 ; CHECK-NEXT: ptrue p0.b, vl256
447 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
448 ; CHECK-NEXT: smaxv b0, p0, z0.b
449 ; CHECK-NEXT: fmov w0, s0
450 ; CHECK-NEXT: ret
451 %op = load <256 x i8>, ptr %a
452 %res = call i8 @llvm.vector.reduce.smax.v256i8(<256 x i8> %op)
453 ret i8 %res
454 }
456 ; Don't use SVE for 64-bit vectors.
457 define i16 @smaxv_v4i16(<4 x i16> %a) vscale_range(2,0) #0 {
458 ; CHECK-LABEL: smaxv_v4i16:
459 ; CHECK: // %bb.0:
460 ; CHECK-NEXT: smaxv h0, v0.4h
461 ; CHECK-NEXT: fmov w0, s0
462 ; CHECK-NEXT: ret
463 %res = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %a)
464 ret i16 %res
465 }
467 ; Don't use SVE for 128-bit vectors.
468 define i16 @smaxv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 {
469 ; CHECK-LABEL: smaxv_v8i16:
470 ; CHECK: // %bb.0:
471 ; CHECK-NEXT: smaxv h0, v0.8h
472 ; CHECK-NEXT: fmov w0, s0
473 ; CHECK-NEXT: ret
474 %res = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %a)
475 ret i16 %res
476 }
478 define i16 @smaxv_v16i16(ptr %a) vscale_range(2,0) #0 {
479 ; CHECK-LABEL: smaxv_v16i16:
480 ; CHECK: // %bb.0:
481 ; CHECK-NEXT: ptrue p0.h, vl16
482 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
483 ; CHECK-NEXT: smaxv h0, p0, z0.h
484 ; CHECK-NEXT: fmov w0, s0
485 ; CHECK-NEXT: ret
486 %op = load <16 x i16>, ptr %a
487 %res = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %op)
488 ret i16 %res
489 }
491 define i16 @smaxv_v32i16(ptr %a) #0 {
492 ; VBITS_GE_256-LABEL: smaxv_v32i16:
493 ; VBITS_GE_256: // %bb.0:
494 ; VBITS_GE_256-NEXT: ptrue p0.h, vl16
495 ; VBITS_GE_256-NEXT: mov x8, #16 // =0x10
496 ; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
497 ; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]
498 ; VBITS_GE_256-NEXT: smax z0.h, p0/m, z0.h, z1.h
499 ; VBITS_GE_256-NEXT: smaxv h0, p0, z0.h
500 ; VBITS_GE_256-NEXT: fmov w0, s0
501 ; VBITS_GE_256-NEXT: ret
502 ;
503 ; VBITS_GE_512-LABEL: smaxv_v32i16:
504 ; VBITS_GE_512: // %bb.0:
505 ; VBITS_GE_512-NEXT: ptrue p0.h, vl32
506 ; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
507 ; VBITS_GE_512-NEXT: smaxv h0, p0, z0.h
508 ; VBITS_GE_512-NEXT: fmov w0, s0
509 ; VBITS_GE_512-NEXT: ret
510 %op = load <32 x i16>, ptr %a
511 %res = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> %op)
512 ret i16 %res
513 }
515 define i16 @smaxv_v64i16(ptr %a) vscale_range(8,0) #0 {
516 ; CHECK-LABEL: smaxv_v64i16:
517 ; CHECK: // %bb.0:
518 ; CHECK-NEXT: ptrue p0.h, vl64
519 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
520 ; CHECK-NEXT: smaxv h0, p0, z0.h
521 ; CHECK-NEXT: fmov w0, s0
522 ; CHECK-NEXT: ret
523 %op = load <64 x i16>, ptr %a
524 %res = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> %op)
525 ret i16 %res
526 }
528 define i16 @smaxv_v128i16(ptr %a) vscale_range(16,0) #0 {
529 ; CHECK-LABEL: smaxv_v128i16:
530 ; CHECK: // %bb.0:
531 ; CHECK-NEXT: ptrue p0.h, vl128
532 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
533 ; CHECK-NEXT: smaxv h0, p0, z0.h
534 ; CHECK-NEXT: fmov w0, s0
535 ; CHECK-NEXT: ret
536 %op = load <128 x i16>, ptr %a
537 %res = call i16 @llvm.vector.reduce.smax.v128i16(<128 x i16> %op)
538 ret i16 %res
539 }
541 ; Don't use SVE for 64-bit vectors.
542 define i32 @smaxv_v2i32(<2 x i32> %a) vscale_range(2,0) #0 {
543 ; CHECK-LABEL: smaxv_v2i32:
544 ; CHECK: // %bb.0:
545 ; CHECK-NEXT: smaxp v0.2s, v0.2s, v0.2s
546 ; CHECK-NEXT: fmov w0, s0
547 ; CHECK-NEXT: ret
548 %res = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> %a)
549 ret i32 %res
550 }
552 ; Don't use SVE for 128-bit vectors.
553 define i32 @smaxv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 {
554 ; CHECK-LABEL: smaxv_v4i32:
555 ; CHECK: // %bb.0:
556 ; CHECK-NEXT: smaxv s0, v0.4s
557 ; CHECK-NEXT: fmov w0, s0
558 ; CHECK-NEXT: ret
559 %res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %a)
560 ret i32 %res
561 }
563 define i32 @smaxv_v8i32(ptr %a) vscale_range(2,0) #0 {
564 ; CHECK-LABEL: smaxv_v8i32:
565 ; CHECK: // %bb.0:
566 ; CHECK-NEXT: ptrue p0.s, vl8
567 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
568 ; CHECK-NEXT: smaxv s0, p0, z0.s
569 ; CHECK-NEXT: fmov w0, s0
570 ; CHECK-NEXT: ret
571 %op = load <8 x i32>, ptr %a
572 %res = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %op)
573 ret i32 %res
574 }
576 define i32 @smaxv_v16i32(ptr %a) #0 {
577 ; VBITS_GE_256-LABEL: smaxv_v16i32:
578 ; VBITS_GE_256: // %bb.0:
579 ; VBITS_GE_256-NEXT: ptrue p0.s, vl8
580 ; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
581 ; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
582 ; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]
583 ; VBITS_GE_256-NEXT: smax z0.s, p0/m, z0.s, z1.s
584 ; VBITS_GE_256-NEXT: smaxv s0, p0, z0.s
585 ; VBITS_GE_256-NEXT: fmov w0, s0
586 ; VBITS_GE_256-NEXT: ret
587 ;
588 ; VBITS_GE_512-LABEL: smaxv_v16i32:
589 ; VBITS_GE_512: // %bb.0:
590 ; VBITS_GE_512-NEXT: ptrue p0.s, vl16
591 ; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
592 ; VBITS_GE_512-NEXT: smaxv s0, p0, z0.s
593 ; VBITS_GE_512-NEXT: fmov w0, s0
594 ; VBITS_GE_512-NEXT: ret
595 %op = load <16 x i32>, ptr %a
596 %res = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %op)
597 ret i32 %res
598 }
600 define i32 @smaxv_v32i32(ptr %a) vscale_range(8,0) #0 {
601 ; CHECK-LABEL: smaxv_v32i32:
602 ; CHECK: // %bb.0:
603 ; CHECK-NEXT: ptrue p0.s, vl32
604 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
605 ; CHECK-NEXT: smaxv s0, p0, z0.s
606 ; CHECK-NEXT: fmov w0, s0
607 ; CHECK-NEXT: ret
608 %op = load <32 x i32>, ptr %a
609 %res = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> %op)
610 ret i32 %res
611 }
613 define i32 @smaxv_v64i32(ptr %a) vscale_range(16,0) #0 {
614 ; CHECK-LABEL: smaxv_v64i32:
615 ; CHECK: // %bb.0:
616 ; CHECK-NEXT: ptrue p0.s, vl64
617 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
618 ; CHECK-NEXT: smaxv s0, p0, z0.s
619 ; CHECK-NEXT: fmov w0, s0
620 ; CHECK-NEXT: ret
621 %op = load <64 x i32>, ptr %a
622 %res = call i32 @llvm.vector.reduce.smax.v64i32(<64 x i32> %op)
623 ret i32 %res
624 }
626 ; Nothing to do for single element vectors.
627 define i64 @smaxv_v1i64(<1 x i64> %a) vscale_range(2,0) #0 {
628 ; CHECK-LABEL: smaxv_v1i64:
629 ; CHECK: // %bb.0:
630 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
631 ; CHECK-NEXT: fmov x0, d0
632 ; CHECK-NEXT: ret
633 %res = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> %a)
634 ret i64 %res
635 }
637 ; No NEON 64-bit vector SMAXV support. Use SVE.
638 define i64 @smaxv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 {
639 ; CHECK-LABEL: smaxv_v2i64:
640 ; CHECK: // %bb.0:
641 ; CHECK-NEXT: ptrue p0.d, vl2
642 ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
643 ; CHECK-NEXT: smaxv d0, p0, z0.d
644 ; CHECK-NEXT: fmov x0, d0
645 ; CHECK-NEXT: ret
646 %res = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %a)
647 ret i64 %res
648 }
650 define i64 @smaxv_v4i64(ptr %a) vscale_range(2,0) #0 {
651 ; CHECK-LABEL: smaxv_v4i64:
652 ; CHECK: // %bb.0:
653 ; CHECK-NEXT: ptrue p0.d, vl4
654 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
655 ; CHECK-NEXT: smaxv d0, p0, z0.d
656 ; CHECK-NEXT: fmov x0, d0
657 ; CHECK-NEXT: ret
658 %op = load <4 x i64>, ptr %a
659 %res = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %op)
660 ret i64 %res
661 }
663 define i64 @smaxv_v8i64(ptr %a) #0 {
664 ; VBITS_GE_256-LABEL: smaxv_v8i64:
665 ; VBITS_GE_256: // %bb.0:
666 ; VBITS_GE_256-NEXT: ptrue p0.d, vl4
667 ; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
668 ; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
669 ; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]
670 ; VBITS_GE_256-NEXT: smax z0.d, p0/m, z0.d, z1.d
671 ; VBITS_GE_256-NEXT: smaxv d0, p0, z0.d
672 ; VBITS_GE_256-NEXT: fmov x0, d0
673 ; VBITS_GE_256-NEXT: ret
674 ;
675 ; VBITS_GE_512-LABEL: smaxv_v8i64:
676 ; VBITS_GE_512: // %bb.0:
677 ; VBITS_GE_512-NEXT: ptrue p0.d, vl8
678 ; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
679 ; VBITS_GE_512-NEXT: smaxv d0, p0, z0.d
680 ; VBITS_GE_512-NEXT: fmov x0, d0
681 ; VBITS_GE_512-NEXT: ret
682 %op = load <8 x i64>, ptr %a
683 %res = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> %op)
684 ret i64 %res
685 }
687 define i64 @smaxv_v16i64(ptr %a) vscale_range(8,0) #0 {
688 ; CHECK-LABEL: smaxv_v16i64:
689 ; CHECK: // %bb.0:
690 ; CHECK-NEXT: ptrue p0.d, vl16
691 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
692 ; CHECK-NEXT: smaxv d0, p0, z0.d
693 ; CHECK-NEXT: fmov x0, d0
694 ; CHECK-NEXT: ret
695 %op = load <16 x i64>, ptr %a
696 %res = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> %op)
697 ret i64 %res
698 }
700 define i64 @smaxv_v32i64(ptr %a) vscale_range(16,0) #0 {
701 ; CHECK-LABEL: smaxv_v32i64:
702 ; CHECK: // %bb.0:
703 ; CHECK-NEXT: ptrue p0.d, vl32
704 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
705 ; CHECK-NEXT: smaxv d0, p0, z0.d
706 ; CHECK-NEXT: fmov x0, d0
707 ; CHECK-NEXT: ret
708 %op = load <32 x i64>, ptr %a
709 %res = call i64 @llvm.vector.reduce.smax.v32i64(<32 x i64> %op)
710 ret i64 %res
711 }
713 ;
714 ; SMINV
715 ;
717 ; Don't use SVE for 64-bit vectors.
718 define i8 @sminv_v8i8(<8 x i8> %a) vscale_range(2,0) #0 {
719 ; CHECK-LABEL: sminv_v8i8:
720 ; CHECK: // %bb.0:
721 ; CHECK-NEXT: sminv b0, v0.8b
722 ; CHECK-NEXT: fmov w0, s0
723 ; CHECK-NEXT: ret
724 %res = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> %a)
725 ret i8 %res
726 }
728 ; Don't use SVE for 128-bit vectors.
729 define i8 @sminv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 {
730 ; CHECK-LABEL: sminv_v16i8:
731 ; CHECK: // %bb.0:
732 ; CHECK-NEXT: sminv b0, v0.16b
733 ; CHECK-NEXT: fmov w0, s0
734 ; CHECK-NEXT: ret
735 %res = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %a)
736 ret i8 %res
737 }
739 define i8 @sminv_v32i8(ptr %a) vscale_range(2,0) #0 {
740 ; CHECK-LABEL: sminv_v32i8:
741 ; CHECK: // %bb.0:
742 ; CHECK-NEXT: ptrue p0.b, vl32
743 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
744 ; CHECK-NEXT: sminv b0, p0, z0.b
745 ; CHECK-NEXT: fmov w0, s0
746 ; CHECK-NEXT: ret
747 %op = load <32 x i8>, ptr %a
748 %res = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> %op)
749 ret i8 %res
750 }
752 define i8 @sminv_v64i8(ptr %a) #0 {
753 ; VBITS_GE_256-LABEL: sminv_v64i8:
754 ; VBITS_GE_256: // %bb.0:
755 ; VBITS_GE_256-NEXT: ptrue p0.b, vl32
756 ; VBITS_GE_256-NEXT: mov w8, #32 // =0x20
757 ; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
758 ; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x0]
759 ; VBITS_GE_256-NEXT: smin z0.b, p0/m, z0.b, z1.b
760 ; VBITS_GE_256-NEXT: sminv b0, p0, z0.b
761 ; VBITS_GE_256-NEXT: fmov w0, s0
762 ; VBITS_GE_256-NEXT: ret
763 ;
764 ; VBITS_GE_512-LABEL: sminv_v64i8:
765 ; VBITS_GE_512: // %bb.0:
766 ; VBITS_GE_512-NEXT: ptrue p0.b, vl64
767 ; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]
768 ; VBITS_GE_512-NEXT: sminv b0, p0, z0.b
769 ; VBITS_GE_512-NEXT: fmov w0, s0
770 ; VBITS_GE_512-NEXT: ret
771 %op = load <64 x i8>, ptr %a
772 %res = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> %op)
773 ret i8 %res
774 }
776 define i8 @sminv_v128i8(ptr %a) vscale_range(8,0) #0 {
777 ; CHECK-LABEL: sminv_v128i8:
778 ; CHECK: // %bb.0:
779 ; CHECK-NEXT: ptrue p0.b, vl128
780 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
781 ; CHECK-NEXT: sminv b0, p0, z0.b
782 ; CHECK-NEXT: fmov w0, s0
783 ; CHECK-NEXT: ret
784 %op = load <128 x i8>, ptr %a
785 %res = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> %op)
786 ret i8 %res
787 }
789 define i8 @sminv_v256i8(ptr %a) vscale_range(16,0) #0 {
790 ; CHECK-LABEL: sminv_v256i8:
791 ; CHECK: // %bb.0:
792 ; CHECK-NEXT: ptrue p0.b, vl256
793 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
794 ; CHECK-NEXT: sminv b0, p0, z0.b
795 ; CHECK-NEXT: fmov w0, s0
796 ; CHECK-NEXT: ret
797 %op = load <256 x i8>, ptr %a
798 %res = call i8 @llvm.vector.reduce.smin.v256i8(<256 x i8> %op)
799 ret i8 %res
800 }
802 ; Don't use SVE for 64-bit vectors.
803 define i16 @sminv_v4i16(<4 x i16> %a) vscale_range(2,0) #0 {
804 ; CHECK-LABEL: sminv_v4i16:
805 ; CHECK: // %bb.0:
806 ; CHECK-NEXT: sminv h0, v0.4h
807 ; CHECK-NEXT: fmov w0, s0
808 ; CHECK-NEXT: ret
809 %res = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %a)
810 ret i16 %res
811 }
813 ; Don't use SVE for 128-bit vectors.
814 define i16 @sminv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 {
815 ; CHECK-LABEL: sminv_v8i16:
816 ; CHECK: // %bb.0:
817 ; CHECK-NEXT: sminv h0, v0.8h
818 ; CHECK-NEXT: fmov w0, s0
819 ; CHECK-NEXT: ret
820 %res = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %a)
821 ret i16 %res
822 }
824 define i16 @sminv_v16i16(ptr %a) vscale_range(2,0) #0 {
825 ; CHECK-LABEL: sminv_v16i16:
826 ; CHECK: // %bb.0:
827 ; CHECK-NEXT: ptrue p0.h, vl16
828 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
829 ; CHECK-NEXT: sminv h0, p0, z0.h
830 ; CHECK-NEXT: fmov w0, s0
831 ; CHECK-NEXT: ret
832 %op = load <16 x i16>, ptr %a
833 %res = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %op)
834 ret i16 %res
835 }
837 define i16 @sminv_v32i16(ptr %a) #0 {
838 ; VBITS_GE_256-LABEL: sminv_v32i16:
839 ; VBITS_GE_256: // %bb.0:
840 ; VBITS_GE_256-NEXT: ptrue p0.h, vl16
841 ; VBITS_GE_256-NEXT: mov x8, #16 // =0x10
842 ; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
843 ; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]
844 ; VBITS_GE_256-NEXT: smin z0.h, p0/m, z0.h, z1.h
845 ; VBITS_GE_256-NEXT: sminv h0, p0, z0.h
846 ; VBITS_GE_256-NEXT: fmov w0, s0
847 ; VBITS_GE_256-NEXT: ret
848 ;
849 ; VBITS_GE_512-LABEL: sminv_v32i16:
850 ; VBITS_GE_512: // %bb.0:
851 ; VBITS_GE_512-NEXT: ptrue p0.h, vl32
852 ; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
853 ; VBITS_GE_512-NEXT: sminv h0, p0, z0.h
854 ; VBITS_GE_512-NEXT: fmov w0, s0
855 ; VBITS_GE_512-NEXT: ret
856 %op = load <32 x i16>, ptr %a
857 %res = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> %op)
858 ret i16 %res
859 }
861 define i16 @sminv_v64i16(ptr %a) vscale_range(8,0) #0 {
862 ; CHECK-LABEL: sminv_v64i16:
863 ; CHECK: // %bb.0:
864 ; CHECK-NEXT: ptrue p0.h, vl64
865 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
866 ; CHECK-NEXT: sminv h0, p0, z0.h
867 ; CHECK-NEXT: fmov w0, s0
868 ; CHECK-NEXT: ret
869 %op = load <64 x i16>, ptr %a
870 %res = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> %op)
871 ret i16 %res
872 }
874 define i16 @sminv_v128i16(ptr %a) vscale_range(16,0) #0 {
875 ; CHECK-LABEL: sminv_v128i16:
876 ; CHECK: // %bb.0:
877 ; CHECK-NEXT: ptrue p0.h, vl128
878 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
879 ; CHECK-NEXT: sminv h0, p0, z0.h
880 ; CHECK-NEXT: fmov w0, s0
881 ; CHECK-NEXT: ret
882 %op = load <128 x i16>, ptr %a
883 %res = call i16 @llvm.vector.reduce.smin.v128i16(<128 x i16> %op)
884 ret i16 %res
885 }
887 ; Don't use SVE for 64-bit vectors.
888 define i32 @sminv_v2i32(<2 x i32> %a) vscale_range(2,0) #0 {
889 ; CHECK-LABEL: sminv_v2i32:
890 ; CHECK: // %bb.0:
891 ; CHECK-NEXT: sminp v0.2s, v0.2s, v0.2s
892 ; CHECK-NEXT: fmov w0, s0
893 ; CHECK-NEXT: ret
894 %res = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> %a)
895 ret i32 %res
896 }
898 ; Don't use SVE for 128-bit vectors.
899 define i32 @sminv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 {
900 ; CHECK-LABEL: sminv_v4i32:
901 ; CHECK: // %bb.0:
902 ; CHECK-NEXT: sminv s0, v0.4s
903 ; CHECK-NEXT: fmov w0, s0
904 ; CHECK-NEXT: ret
905 %res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %a)
906 ret i32 %res
907 }
909 define i32 @sminv_v8i32(ptr %a) vscale_range(2,0) #0 {
910 ; CHECK-LABEL: sminv_v8i32:
911 ; CHECK: // %bb.0:
912 ; CHECK-NEXT: ptrue p0.s, vl8
913 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
914 ; CHECK-NEXT: sminv s0, p0, z0.s
915 ; CHECK-NEXT: fmov w0, s0
916 ; CHECK-NEXT: ret
917 %op = load <8 x i32>, ptr %a
918 %res = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %op)
919 ret i32 %res
920 }
922 define i32 @sminv_v16i32(ptr %a) #0 {
923 ; VBITS_GE_256-LABEL: sminv_v16i32:
924 ; VBITS_GE_256: // %bb.0:
925 ; VBITS_GE_256-NEXT: ptrue p0.s, vl8
926 ; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
927 ; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
928 ; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]
929 ; VBITS_GE_256-NEXT: smin z0.s, p0/m, z0.s, z1.s
930 ; VBITS_GE_256-NEXT: sminv s0, p0, z0.s
931 ; VBITS_GE_256-NEXT: fmov w0, s0
932 ; VBITS_GE_256-NEXT: ret
933 ;
934 ; VBITS_GE_512-LABEL: sminv_v16i32:
935 ; VBITS_GE_512: // %bb.0:
936 ; VBITS_GE_512-NEXT: ptrue p0.s, vl16
937 ; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
938 ; VBITS_GE_512-NEXT: sminv s0, p0, z0.s
939 ; VBITS_GE_512-NEXT: fmov w0, s0
940 ; VBITS_GE_512-NEXT: ret
941 %op = load <16 x i32>, ptr %a
942 %res = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> %op)
943 ret i32 %res
944 }
946 define i32 @sminv_v32i32(ptr %a) vscale_range(8,0) #0 {
947 ; CHECK-LABEL: sminv_v32i32:
948 ; CHECK: // %bb.0:
949 ; CHECK-NEXT: ptrue p0.s, vl32
950 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
951 ; CHECK-NEXT: sminv s0, p0, z0.s
952 ; CHECK-NEXT: fmov w0, s0
953 ; CHECK-NEXT: ret
954 %op = load <32 x i32>, ptr %a
955 %res = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> %op)
956 ret i32 %res
957 }
959 define i32 @sminv_v64i32(ptr %a) vscale_range(16,0) #0 {
960 ; CHECK-LABEL: sminv_v64i32:
961 ; CHECK: // %bb.0:
962 ; CHECK-NEXT: ptrue p0.s, vl64
963 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
964 ; CHECK-NEXT: sminv s0, p0, z0.s
965 ; CHECK-NEXT: fmov w0, s0
966 ; CHECK-NEXT: ret
967 %op = load <64 x i32>, ptr %a
968 %res = call i32 @llvm.vector.reduce.smin.v64i32(<64 x i32> %op)
969 ret i32 %res
970 }
972 ; Nothing to do for single element vectors.
973 define i64 @sminv_v1i64(<1 x i64> %a) vscale_range(2,0) #0 {
974 ; CHECK-LABEL: sminv_v1i64:
975 ; CHECK: // %bb.0:
976 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
977 ; CHECK-NEXT: fmov x0, d0
978 ; CHECK-NEXT: ret
979 %res = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> %a)
980 ret i64 %res
981 }
983 ; No NEON 64-bit vector SMINV support. Use SVE.
984 define i64 @sminv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 {
985 ; CHECK-LABEL: sminv_v2i64:
986 ; CHECK: // %bb.0:
987 ; CHECK-NEXT: ptrue p0.d, vl2
988 ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
989 ; CHECK-NEXT: sminv d0, p0, z0.d
990 ; CHECK-NEXT: fmov x0, d0
991 ; CHECK-NEXT: ret
992 %res = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %a)
993 ret i64 %res
994 }
996 define i64 @sminv_v4i64(ptr %a) vscale_range(2,0) #0 {
997 ; CHECK-LABEL: sminv_v4i64:
998 ; CHECK: // %bb.0:
999 ; CHECK-NEXT: ptrue p0.d, vl4
1000 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
1001 ; CHECK-NEXT: sminv d0, p0, z0.d
1002 ; CHECK-NEXT: fmov x0, d0
1003 ; CHECK-NEXT: ret
1004 %op = load <4 x i64>, ptr %a
1005 %res = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %op)
1006 ret i64 %res
1007 }
1009 define i64 @sminv_v8i64(ptr %a) #0 {
1010 ; VBITS_GE_256-LABEL: sminv_v8i64:
1011 ; VBITS_GE_256: // %bb.0:
1012 ; VBITS_GE_256-NEXT: ptrue p0.d, vl4
1013 ; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
1014 ; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
1015 ; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]
1016 ; VBITS_GE_256-NEXT: smin z0.d, p0/m, z0.d, z1.d
1017 ; VBITS_GE_256-NEXT: sminv d0, p0, z0.d
1018 ; VBITS_GE_256-NEXT: fmov x0, d0
1019 ; VBITS_GE_256-NEXT: ret
1020 ;
1021 ; VBITS_GE_512-LABEL: sminv_v8i64:
1022 ; VBITS_GE_512: // %bb.0:
1023 ; VBITS_GE_512-NEXT: ptrue p0.d, vl8
1024 ; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
1025 ; VBITS_GE_512-NEXT: sminv d0, p0, z0.d
1026 ; VBITS_GE_512-NEXT: fmov x0, d0
1027 ; VBITS_GE_512-NEXT: ret
1028 %op = load <8 x i64>, ptr %a
1029 %res = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> %op)
1030 ret i64 %res
1031 }
1033 define i64 @sminv_v16i64(ptr %a) vscale_range(8,0) #0 {
1034 ; CHECK-LABEL: sminv_v16i64:
1035 ; CHECK: // %bb.0:
1036 ; CHECK-NEXT: ptrue p0.d, vl16
1037 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
1038 ; CHECK-NEXT: sminv d0, p0, z0.d
1039 ; CHECK-NEXT: fmov x0, d0
1040 ; CHECK-NEXT: ret
1041 %op = load <16 x i64>, ptr %a
1042 %res = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> %op)
1043 ret i64 %res
1044 }
1046 define i64 @sminv_v32i64(ptr %a) vscale_range(16,0) #0 {
1047 ; CHECK-LABEL: sminv_v32i64:
1048 ; CHECK: // %bb.0:
1049 ; CHECK-NEXT: ptrue p0.d, vl32
1050 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
1051 ; CHECK-NEXT: sminv d0, p0, z0.d
1052 ; CHECK-NEXT: fmov x0, d0
1053 ; CHECK-NEXT: ret
1054 %op = load <32 x i64>, ptr %a
1055 %res = call i64 @llvm.vector.reduce.smin.v32i64(<32 x i64> %op)
1056 ret i64 %res
1057 }
1059 ;
1060 ; UMAXV
1061 ;
1063 ; Don't use SVE for 64-bit vectors.
1064 define i8 @umaxv_v8i8(<8 x i8> %a) vscale_range(2,0) #0 {
1065 ; CHECK-LABEL: umaxv_v8i8:
1066 ; CHECK: // %bb.0:
1067 ; CHECK-NEXT: umaxv b0, v0.8b
1068 ; CHECK-NEXT: fmov w0, s0
1069 ; CHECK-NEXT: ret
1070 %res = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> %a)
1071 ret i8 %res
1072 }
1074 ; Don't use SVE for 128-bit vectors.
1075 define i8 @umaxv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 {
1076 ; CHECK-LABEL: umaxv_v16i8:
1077 ; CHECK: // %bb.0:
1078 ; CHECK-NEXT: umaxv b0, v0.16b
1079 ; CHECK-NEXT: fmov w0, s0
1080 ; CHECK-NEXT: ret
1081 %res = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %a)
1082 ret i8 %res
1083 }
1085 define i8 @umaxv_v32i8(ptr %a) vscale_range(2,0) #0 {
1086 ; CHECK-LABEL: umaxv_v32i8:
1087 ; CHECK: // %bb.0:
1088 ; CHECK-NEXT: ptrue p0.b, vl32
1089 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
1090 ; CHECK-NEXT: umaxv b0, p0, z0.b
1091 ; CHECK-NEXT: fmov w0, s0
1092 ; CHECK-NEXT: ret
1093 %op = load <32 x i8>, ptr %a
1094 %res = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> %op)
1095 ret i8 %res
1096 }
1098 define i8 @umaxv_v64i8(ptr %a) #0 {
1099 ; VBITS_GE_256-LABEL: umaxv_v64i8:
1100 ; VBITS_GE_256: // %bb.0:
1101 ; VBITS_GE_256-NEXT: ptrue p0.b, vl32
1102 ; VBITS_GE_256-NEXT: mov w8, #32 // =0x20
1103 ; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
1104 ; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x0]
1105 ; VBITS_GE_256-NEXT: umax z0.b, p0/m, z0.b, z1.b
1106 ; VBITS_GE_256-NEXT: umaxv b0, p0, z0.b
1107 ; VBITS_GE_256-NEXT: fmov w0, s0
1108 ; VBITS_GE_256-NEXT: ret
1109 ;
1110 ; VBITS_GE_512-LABEL: umaxv_v64i8:
1111 ; VBITS_GE_512: // %bb.0:
1112 ; VBITS_GE_512-NEXT: ptrue p0.b, vl64
1113 ; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]
1114 ; VBITS_GE_512-NEXT: umaxv b0, p0, z0.b
1115 ; VBITS_GE_512-NEXT: fmov w0, s0
1116 ; VBITS_GE_512-NEXT: ret
1117 %op = load <64 x i8>, ptr %a
1118 %res = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> %op)
1119 ret i8 %res
1120 }
1122 define i8 @umaxv_v128i8(ptr %a) vscale_range(8,0) #0 {
1123 ; CHECK-LABEL: umaxv_v128i8:
1124 ; CHECK: // %bb.0:
1125 ; CHECK-NEXT: ptrue p0.b, vl128
1126 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
1127 ; CHECK-NEXT: umaxv b0, p0, z0.b
1128 ; CHECK-NEXT: fmov w0, s0
1129 ; CHECK-NEXT: ret
1130 %op = load <128 x i8>, ptr %a
1131 %res = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> %op)
1132 ret i8 %res
1133 }
1135 define i8 @umaxv_v256i8(ptr %a) vscale_range(16,0) #0 {
1136 ; CHECK-LABEL: umaxv_v256i8:
1137 ; CHECK: // %bb.0:
1138 ; CHECK-NEXT: ptrue p0.b, vl256
1139 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
1140 ; CHECK-NEXT: umaxv b0, p0, z0.b
1141 ; CHECK-NEXT: fmov w0, s0
1142 ; CHECK-NEXT: ret
1143 %op = load <256 x i8>, ptr %a
1144 %res = call i8 @llvm.vector.reduce.umax.v256i8(<256 x i8> %op)
1145 ret i8 %res
1146 }
1148 ; Don't use SVE for 64-bit vectors.
1149 define i16 @umaxv_v4i16(<4 x i16> %a) vscale_range(2,0) #0 {
1150 ; CHECK-LABEL: umaxv_v4i16:
1151 ; CHECK: // %bb.0:
1152 ; CHECK-NEXT: umaxv h0, v0.4h
1153 ; CHECK-NEXT: fmov w0, s0
1154 ; CHECK-NEXT: ret
1155 %res = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %a)
1156 ret i16 %res
1157 }
1159 ; Don't use SVE for 128-bit vectors.
1160 define i16 @umaxv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 {
1161 ; CHECK-LABEL: umaxv_v8i16:
1162 ; CHECK: // %bb.0:
1163 ; CHECK-NEXT: umaxv h0, v0.8h
1164 ; CHECK-NEXT: fmov w0, s0
1165 ; CHECK-NEXT: ret
1166 %res = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %a)
1167 ret i16 %res
1168 }
1170 define i16 @umaxv_v16i16(ptr %a) vscale_range(2,0) #0 {
1171 ; CHECK-LABEL: umaxv_v16i16:
1172 ; CHECK: // %bb.0:
1173 ; CHECK-NEXT: ptrue p0.h, vl16
1174 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
1175 ; CHECK-NEXT: umaxv h0, p0, z0.h
1176 ; CHECK-NEXT: fmov w0, s0
1177 ; CHECK-NEXT: ret
1178 %op = load <16 x i16>, ptr %a
1179 %res = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %op)
1180 ret i16 %res
1181 }
1183 define i16 @umaxv_v32i16(ptr %a) #0 {
1184 ; VBITS_GE_256-LABEL: umaxv_v32i16:
1185 ; VBITS_GE_256: // %bb.0:
1186 ; VBITS_GE_256-NEXT: ptrue p0.h, vl16
1187 ; VBITS_GE_256-NEXT: mov x8, #16 // =0x10
1188 ; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
1189 ; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]
1190 ; VBITS_GE_256-NEXT: umax z0.h, p0/m, z0.h, z1.h
1191 ; VBITS_GE_256-NEXT: umaxv h0, p0, z0.h
1192 ; VBITS_GE_256-NEXT: fmov w0, s0
1193 ; VBITS_GE_256-NEXT: ret
1194 ;
1195 ; VBITS_GE_512-LABEL: umaxv_v32i16:
1196 ; VBITS_GE_512: // %bb.0:
1197 ; VBITS_GE_512-NEXT: ptrue p0.h, vl32
1198 ; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
1199 ; VBITS_GE_512-NEXT: umaxv h0, p0, z0.h
1200 ; VBITS_GE_512-NEXT: fmov w0, s0
1201 ; VBITS_GE_512-NEXT: ret
1202 %op = load <32 x i16>, ptr %a
1203 %res = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> %op)
1204 ret i16 %res
1205 }
1207 define i16 @umaxv_v64i16(ptr %a) vscale_range(8,0) #0 {
1208 ; CHECK-LABEL: umaxv_v64i16:
1209 ; CHECK: // %bb.0:
1210 ; CHECK-NEXT: ptrue p0.h, vl64
1211 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
1212 ; CHECK-NEXT: umaxv h0, p0, z0.h
1213 ; CHECK-NEXT: fmov w0, s0
1214 ; CHECK-NEXT: ret
1215 %op = load <64 x i16>, ptr %a
1216 %res = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> %op)
1217 ret i16 %res
1218 }
1220 define i16 @umaxv_v128i16(ptr %a) vscale_range(16,0) #0 {
1221 ; CHECK-LABEL: umaxv_v128i16:
1222 ; CHECK: // %bb.0:
1223 ; CHECK-NEXT: ptrue p0.h, vl128
1224 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
1225 ; CHECK-NEXT: umaxv h0, p0, z0.h
1226 ; CHECK-NEXT: fmov w0, s0
1227 ; CHECK-NEXT: ret
1228 %op = load <128 x i16>, ptr %a
1229 %res = call i16 @llvm.vector.reduce.umax.v128i16(<128 x i16> %op)
1230 ret i16 %res
1231 }
1233 ; Don't use SVE for 64-bit vectors.
1234 define i32 @umaxv_v2i32(<2 x i32> %a) vscale_range(2,0) #0 {
1235 ; CHECK-LABEL: umaxv_v2i32:
1236 ; CHECK: // %bb.0:
1237 ; CHECK-NEXT: umaxp v0.2s, v0.2s, v0.2s
1238 ; CHECK-NEXT: fmov w0, s0
1239 ; CHECK-NEXT: ret
1240 %res = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %a)
1241 ret i32 %res
1242 }
1244 ; Don't use SVE for 128-bit vectors.
1245 define i32 @umaxv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 {
1246 ; CHECK-LABEL: umaxv_v4i32:
1247 ; CHECK: // %bb.0:
1248 ; CHECK-NEXT: umaxv s0, v0.4s
1249 ; CHECK-NEXT: fmov w0, s0
1250 ; CHECK-NEXT: ret
1251 %res = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %a)
1252 ret i32 %res
1253 }
1255 define i32 @umaxv_v8i32(ptr %a) vscale_range(2,0) #0 {
1256 ; CHECK-LABEL: umaxv_v8i32:
1257 ; CHECK: // %bb.0:
1258 ; CHECK-NEXT: ptrue p0.s, vl8
1259 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
1260 ; CHECK-NEXT: umaxv s0, p0, z0.s
1261 ; CHECK-NEXT: fmov w0, s0
1262 ; CHECK-NEXT: ret
1263 %op = load <8 x i32>, ptr %a
1264 %res = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %op)
1265 ret i32 %res
1266 }
1268 define i32 @umaxv_v16i32(ptr %a) #0 {
1269 ; VBITS_GE_256-LABEL: umaxv_v16i32:
1270 ; VBITS_GE_256: // %bb.0:
1271 ; VBITS_GE_256-NEXT: ptrue p0.s, vl8
1272 ; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
1273 ; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
1274 ; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]
1275 ; VBITS_GE_256-NEXT: umax z0.s, p0/m, z0.s, z1.s
1276 ; VBITS_GE_256-NEXT: umaxv s0, p0, z0.s
1277 ; VBITS_GE_256-NEXT: fmov w0, s0
1278 ; VBITS_GE_256-NEXT: ret
1279 ;
1280 ; VBITS_GE_512-LABEL: umaxv_v16i32:
1281 ; VBITS_GE_512: // %bb.0:
1282 ; VBITS_GE_512-NEXT: ptrue p0.s, vl16
1283 ; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
1284 ; VBITS_GE_512-NEXT: umaxv s0, p0, z0.s
1285 ; VBITS_GE_512-NEXT: fmov w0, s0
1286 ; VBITS_GE_512-NEXT: ret
1287 %op = load <16 x i32>, ptr %a
1288 %res = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %op)
1289 ret i32 %res
1290 }
1292 define i32 @umaxv_v32i32(ptr %a) vscale_range(8,0) #0 {
1293 ; CHECK-LABEL: umaxv_v32i32:
1294 ; CHECK: // %bb.0:
1295 ; CHECK-NEXT: ptrue p0.s, vl32
1296 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
1297 ; CHECK-NEXT: umaxv s0, p0, z0.s
1298 ; CHECK-NEXT: fmov w0, s0
1299 ; CHECK-NEXT: ret
1300 %op = load <32 x i32>, ptr %a
1301 %res = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> %op)
1302 ret i32 %res
1303 }
1305 define i32 @umaxv_v64i32(ptr %a) vscale_range(16,0) #0 {
1306 ; CHECK-LABEL: umaxv_v64i32:
1307 ; CHECK: // %bb.0:
1308 ; CHECK-NEXT: ptrue p0.s, vl64
1309 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
1310 ; CHECK-NEXT: umaxv s0, p0, z0.s
1311 ; CHECK-NEXT: fmov w0, s0
1312 ; CHECK-NEXT: ret
1313 %op = load <64 x i32>, ptr %a
1314 %res = call i32 @llvm.vector.reduce.umax.v64i32(<64 x i32> %op)
1315 ret i32 %res
1316 }
1318 ; Nothing to do for single element vectors.
1319 define i64 @umaxv_v1i64(<1 x i64> %a) vscale_range(2,0) #0 {
1320 ; CHECK-LABEL: umaxv_v1i64:
1321 ; CHECK: // %bb.0:
1322 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
1323 ; CHECK-NEXT: fmov x0, d0
1324 ; CHECK-NEXT: ret
1325 %res = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> %a)
1326 ret i64 %res
1327 }
1329 ; No NEON 64-bit vector UMAXV support. Use SVE.
1330 define i64 @umaxv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 {
1331 ; CHECK-LABEL: umaxv_v2i64:
1332 ; CHECK: // %bb.0:
1333 ; CHECK-NEXT: ptrue p0.d, vl2
1334 ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
1335 ; CHECK-NEXT: umaxv d0, p0, z0.d
1336 ; CHECK-NEXT: fmov x0, d0
1337 ; CHECK-NEXT: ret
1338 %res = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %a)
1339 ret i64 %res
1340 }
1342 define i64 @umaxv_v4i64(ptr %a) vscale_range(2,0) #0 {
1343 ; CHECK-LABEL: umaxv_v4i64:
1344 ; CHECK: // %bb.0:
1345 ; CHECK-NEXT: ptrue p0.d, vl4
1346 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
1347 ; CHECK-NEXT: umaxv d0, p0, z0.d
1348 ; CHECK-NEXT: fmov x0, d0
1349 ; CHECK-NEXT: ret
1350 %op = load <4 x i64>, ptr %a
1351 %res = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %op)
1352 ret i64 %res
1353 }
1355 define i64 @umaxv_v8i64(ptr %a) #0 {
1356 ; VBITS_GE_256-LABEL: umaxv_v8i64:
1357 ; VBITS_GE_256: // %bb.0:
1358 ; VBITS_GE_256-NEXT: ptrue p0.d, vl4
1359 ; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
1360 ; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
1361 ; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]
1362 ; VBITS_GE_256-NEXT: umax z0.d, p0/m, z0.d, z1.d
1363 ; VBITS_GE_256-NEXT: umaxv d0, p0, z0.d
1364 ; VBITS_GE_256-NEXT: fmov x0, d0
1365 ; VBITS_GE_256-NEXT: ret
1366 ;
1367 ; VBITS_GE_512-LABEL: umaxv_v8i64:
1368 ; VBITS_GE_512: // %bb.0:
1369 ; VBITS_GE_512-NEXT: ptrue p0.d, vl8
1370 ; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
1371 ; VBITS_GE_512-NEXT: umaxv d0, p0, z0.d
1372 ; VBITS_GE_512-NEXT: fmov x0, d0
1373 ; VBITS_GE_512-NEXT: ret
1374 %op = load <8 x i64>, ptr %a
1375 %res = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> %op)
1376 ret i64 %res
1377 }
1379 define i64 @umaxv_v16i64(ptr %a) vscale_range(8,0) #0 {
1380 ; CHECK-LABEL: umaxv_v16i64:
1381 ; CHECK: // %bb.0:
1382 ; CHECK-NEXT: ptrue p0.d, vl16
1383 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
1384 ; CHECK-NEXT: umaxv d0, p0, z0.d
1385 ; CHECK-NEXT: fmov x0, d0
1386 ; CHECK-NEXT: ret
1387 %op = load <16 x i64>, ptr %a
1388 %res = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> %op)
1389 ret i64 %res
1390 }
1392 define i64 @umaxv_v32i64(ptr %a) vscale_range(16,0) #0 {
1393 ; CHECK-LABEL: umaxv_v32i64:
1394 ; CHECK: // %bb.0:
1395 ; CHECK-NEXT: ptrue p0.d, vl32
1396 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
1397 ; CHECK-NEXT: umaxv d0, p0, z0.d
1398 ; CHECK-NEXT: fmov x0, d0
1399 ; CHECK-NEXT: ret
1400 %op = load <32 x i64>, ptr %a
1401 %res = call i64 @llvm.vector.reduce.umax.v32i64(<32 x i64> %op)
1402 ret i64 %res
1403 }
1405 ;
1406 ; UMINV
1407 ;
1409 ; Don't use SVE for 64-bit vectors.
1410 define i8 @uminv_v8i8(<8 x i8> %a) vscale_range(2,0) #0 {
1411 ; CHECK-LABEL: uminv_v8i8:
1412 ; CHECK: // %bb.0:
1413 ; CHECK-NEXT: uminv b0, v0.8b
1414 ; CHECK-NEXT: fmov w0, s0
1415 ; CHECK-NEXT: ret
1416 %res = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> %a)
1417 ret i8 %res
1418 }
1420 ; Don't use SVE for 128-bit vectors.
1421 define i8 @uminv_v16i8(<16 x i8> %a) vscale_range(2,0) #0 {
1422 ; CHECK-LABEL: uminv_v16i8:
1423 ; CHECK: // %bb.0:
1424 ; CHECK-NEXT: uminv b0, v0.16b
1425 ; CHECK-NEXT: fmov w0, s0
1426 ; CHECK-NEXT: ret
1427 %res = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %a)
1428 ret i8 %res
1429 }
1431 define i8 @uminv_v32i8(ptr %a) vscale_range(2,0) #0 {
1432 ; CHECK-LABEL: uminv_v32i8:
1433 ; CHECK: // %bb.0:
1434 ; CHECK-NEXT: ptrue p0.b, vl32
1435 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
1436 ; CHECK-NEXT: uminv b0, p0, z0.b
1437 ; CHECK-NEXT: fmov w0, s0
1438 ; CHECK-NEXT: ret
1439 %op = load <32 x i8>, ptr %a
1440 %res = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> %op)
1441 ret i8 %res
1442 }
1444 define i8 @uminv_v64i8(ptr %a) #0 {
1445 ; VBITS_GE_256-LABEL: uminv_v64i8:
1446 ; VBITS_GE_256: // %bb.0:
1447 ; VBITS_GE_256-NEXT: ptrue p0.b, vl32
1448 ; VBITS_GE_256-NEXT: mov w8, #32 // =0x20
1449 ; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
1450 ; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x0]
1451 ; VBITS_GE_256-NEXT: umin z0.b, p0/m, z0.b, z1.b
1452 ; VBITS_GE_256-NEXT: uminv b0, p0, z0.b
1453 ; VBITS_GE_256-NEXT: fmov w0, s0
1454 ; VBITS_GE_256-NEXT: ret
1455 ;
1456 ; VBITS_GE_512-LABEL: uminv_v64i8:
1457 ; VBITS_GE_512: // %bb.0:
1458 ; VBITS_GE_512-NEXT: ptrue p0.b, vl64
1459 ; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]
1460 ; VBITS_GE_512-NEXT: uminv b0, p0, z0.b
1461 ; VBITS_GE_512-NEXT: fmov w0, s0
1462 ; VBITS_GE_512-NEXT: ret
1463 %op = load <64 x i8>, ptr %a
1464 %res = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> %op)
1465 ret i8 %res
1466 }
1468 define i8 @uminv_v128i8(ptr %a) vscale_range(8,0) #0 {
1469 ; CHECK-LABEL: uminv_v128i8:
1470 ; CHECK: // %bb.0:
1471 ; CHECK-NEXT: ptrue p0.b, vl128
1472 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
1473 ; CHECK-NEXT: uminv b0, p0, z0.b
1474 ; CHECK-NEXT: fmov w0, s0
1475 ; CHECK-NEXT: ret
1476 %op = load <128 x i8>, ptr %a
1477 %res = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> %op)
1478 ret i8 %res
1479 }
1481 define i8 @uminv_v256i8(ptr %a) vscale_range(16,0) #0 {
1482 ; CHECK-LABEL: uminv_v256i8:
1483 ; CHECK: // %bb.0:
1484 ; CHECK-NEXT: ptrue p0.b, vl256
1485 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
1486 ; CHECK-NEXT: uminv b0, p0, z0.b
1487 ; CHECK-NEXT: fmov w0, s0
1488 ; CHECK-NEXT: ret
1489 %op = load <256 x i8>, ptr %a
1490 %res = call i8 @llvm.vector.reduce.umin.v256i8(<256 x i8> %op)
1491 ret i8 %res
1492 }
1494 ; Don't use SVE for 64-bit vectors.
1495 define i16 @uminv_v4i16(<4 x i16> %a) vscale_range(2,0) #0 {
1496 ; CHECK-LABEL: uminv_v4i16:
1497 ; CHECK: // %bb.0:
1498 ; CHECK-NEXT: uminv h0, v0.4h
1499 ; CHECK-NEXT: fmov w0, s0
1500 ; CHECK-NEXT: ret
1501 %res = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> %a)
1502 ret i16 %res
1503 }
1505 ; Don't use SVE for 128-bit vectors.
1506 define i16 @uminv_v8i16(<8 x i16> %a) vscale_range(2,0) #0 {
1507 ; CHECK-LABEL: uminv_v8i16:
1508 ; CHECK: // %bb.0:
1509 ; CHECK-NEXT: uminv h0, v0.8h
1510 ; CHECK-NEXT: fmov w0, s0
1511 ; CHECK-NEXT: ret
1512 %res = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %a)
1513 ret i16 %res
1514 }
1516 define i16 @uminv_v16i16(ptr %a) vscale_range(2,0) #0 {
1517 ; CHECK-LABEL: uminv_v16i16:
1518 ; CHECK: // %bb.0:
1519 ; CHECK-NEXT: ptrue p0.h, vl16
1520 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
1521 ; CHECK-NEXT: uminv h0, p0, z0.h
1522 ; CHECK-NEXT: fmov w0, s0
1523 ; CHECK-NEXT: ret
1524 %op = load <16 x i16>, ptr %a
1525 %res = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %op)
1526 ret i16 %res
1527 }
1529 define i16 @uminv_v32i16(ptr %a) #0 {
1530 ; VBITS_GE_256-LABEL: uminv_v32i16:
1531 ; VBITS_GE_256: // %bb.0:
1532 ; VBITS_GE_256-NEXT: ptrue p0.h, vl16
1533 ; VBITS_GE_256-NEXT: mov x8, #16 // =0x10
1534 ; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
1535 ; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]
1536 ; VBITS_GE_256-NEXT: umin z0.h, p0/m, z0.h, z1.h
1537 ; VBITS_GE_256-NEXT: uminv h0, p0, z0.h
1538 ; VBITS_GE_256-NEXT: fmov w0, s0
1539 ; VBITS_GE_256-NEXT: ret
1540 ;
1541 ; VBITS_GE_512-LABEL: uminv_v32i16:
1542 ; VBITS_GE_512: // %bb.0:
1543 ; VBITS_GE_512-NEXT: ptrue p0.h, vl32
1544 ; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
1545 ; VBITS_GE_512-NEXT: uminv h0, p0, z0.h
1546 ; VBITS_GE_512-NEXT: fmov w0, s0
1547 ; VBITS_GE_512-NEXT: ret
1548 %op = load <32 x i16>, ptr %a
1549 %res = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> %op)
1550 ret i16 %res
1551 }
1553 define i16 @uminv_v64i16(ptr %a) vscale_range(8,0) #0 {
1554 ; CHECK-LABEL: uminv_v64i16:
1555 ; CHECK: // %bb.0:
1556 ; CHECK-NEXT: ptrue p0.h, vl64
1557 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
1558 ; CHECK-NEXT: uminv h0, p0, z0.h
1559 ; CHECK-NEXT: fmov w0, s0
1560 ; CHECK-NEXT: ret
1561 %op = load <64 x i16>, ptr %a
1562 %res = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> %op)
1563 ret i16 %res
1564 }
1566 define i16 @uminv_v128i16(ptr %a) vscale_range(16,0) #0 {
1567 ; CHECK-LABEL: uminv_v128i16:
1568 ; CHECK: // %bb.0:
1569 ; CHECK-NEXT: ptrue p0.h, vl128
1570 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
1571 ; CHECK-NEXT: uminv h0, p0, z0.h
1572 ; CHECK-NEXT: fmov w0, s0
1573 ; CHECK-NEXT: ret
1574 %op = load <128 x i16>, ptr %a
1575 %res = call i16 @llvm.vector.reduce.umin.v128i16(<128 x i16> %op)
1576 ret i16 %res
1577 }
1579 ; Don't use SVE for 64-bit vectors.
1580 define i32 @uminv_v2i32(<2 x i32> %a) vscale_range(2,0) #0 {
1581 ; CHECK-LABEL: uminv_v2i32:
1582 ; CHECK: // %bb.0:
1583 ; CHECK-NEXT: uminp v0.2s, v0.2s, v0.2s
1584 ; CHECK-NEXT: fmov w0, s0
1585 ; CHECK-NEXT: ret
1586 %res = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> %a)
1587 ret i32 %res
1588 }
1590 ; Don't use SVE for 128-bit vectors.
1591 define i32 @uminv_v4i32(<4 x i32> %a) vscale_range(2,0) #0 {
1592 ; CHECK-LABEL: uminv_v4i32:
1593 ; CHECK: // %bb.0:
1594 ; CHECK-NEXT: uminv s0, v0.4s
1595 ; CHECK-NEXT: fmov w0, s0
1596 ; CHECK-NEXT: ret
1597 %res = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %a)
1598 ret i32 %res
1599 }
1601 define i32 @uminv_v8i32(ptr %a) vscale_range(2,0) #0 {
1602 ; CHECK-LABEL: uminv_v8i32:
1603 ; CHECK: // %bb.0:
1604 ; CHECK-NEXT: ptrue p0.s, vl8
1605 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
1606 ; CHECK-NEXT: uminv s0, p0, z0.s
1607 ; CHECK-NEXT: fmov w0, s0
1608 ; CHECK-NEXT: ret
1609 %op = load <8 x i32>, ptr %a
1610 %res = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %op)
1611 ret i32 %res
1612 }
1614 define i32 @uminv_v16i32(ptr %a) #0 {
1615 ; VBITS_GE_256-LABEL: uminv_v16i32:
1616 ; VBITS_GE_256: // %bb.0:
1617 ; VBITS_GE_256-NEXT: ptrue p0.s, vl8
1618 ; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
1619 ; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
1620 ; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]
1621 ; VBITS_GE_256-NEXT: umin z0.s, p0/m, z0.s, z1.s
1622 ; VBITS_GE_256-NEXT: uminv s0, p0, z0.s
1623 ; VBITS_GE_256-NEXT: fmov w0, s0
1624 ; VBITS_GE_256-NEXT: ret
1625 ;
1626 ; VBITS_GE_512-LABEL: uminv_v16i32:
1627 ; VBITS_GE_512: // %bb.0:
1628 ; VBITS_GE_512-NEXT: ptrue p0.s, vl16
1629 ; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
1630 ; VBITS_GE_512-NEXT: uminv s0, p0, z0.s
1631 ; VBITS_GE_512-NEXT: fmov w0, s0
1632 ; VBITS_GE_512-NEXT: ret
1633 %op = load <16 x i32>, ptr %a
1634 %res = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %op)
1635 ret i32 %res
1636 }
1638 define i32 @uminv_v32i32(ptr %a) vscale_range(8,0) #0 {
1639 ; CHECK-LABEL: uminv_v32i32:
1640 ; CHECK: // %bb.0:
1641 ; CHECK-NEXT: ptrue p0.s, vl32
1642 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
1643 ; CHECK-NEXT: uminv s0, p0, z0.s
1644 ; CHECK-NEXT: fmov w0, s0
1645 ; CHECK-NEXT: ret
1646 %op = load <32 x i32>, ptr %a
1647 %res = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> %op)
1648 ret i32 %res
1649 }
1651 define i32 @uminv_v64i32(ptr %a) vscale_range(16,0) #0 {
1652 ; CHECK-LABEL: uminv_v64i32:
1653 ; CHECK: // %bb.0:
1654 ; CHECK-NEXT: ptrue p0.s, vl64
1655 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
1656 ; CHECK-NEXT: uminv s0, p0, z0.s
1657 ; CHECK-NEXT: fmov w0, s0
1658 ; CHECK-NEXT: ret
1659 %op = load <64 x i32>, ptr %a
1660 %res = call i32 @llvm.vector.reduce.umin.v64i32(<64 x i32> %op)
1661 ret i32 %res
1662 }
1664 ; Nothing to do for single element vectors.
1665 define i64 @uminv_v1i64(<1 x i64> %a) vscale_range(2,0) #0 {
1666 ; CHECK-LABEL: uminv_v1i64:
1667 ; CHECK: // %bb.0:
1668 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
1669 ; CHECK-NEXT: fmov x0, d0
1670 ; CHECK-NEXT: ret
1671 %res = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> %a)
1672 ret i64 %res
1673 }
1675 ; No NEON 64-bit vector UMINV support. Use SVE.
1676 define i64 @uminv_v2i64(<2 x i64> %a) vscale_range(2,0) #0 {
1677 ; CHECK-LABEL: uminv_v2i64:
1678 ; CHECK: // %bb.0:
1679 ; CHECK-NEXT: ptrue p0.d, vl2
1680 ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
1681 ; CHECK-NEXT: uminv d0, p0, z0.d
1682 ; CHECK-NEXT: fmov x0, d0
1683 ; CHECK-NEXT: ret
1684 %res = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %a)
1685 ret i64 %res
1686 }
1688 define i64 @uminv_v4i64(ptr %a) vscale_range(2,0) #0 {
1689 ; CHECK-LABEL: uminv_v4i64:
1690 ; CHECK: // %bb.0:
1691 ; CHECK-NEXT: ptrue p0.d, vl4
1692 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
1693 ; CHECK-NEXT: uminv d0, p0, z0.d
1694 ; CHECK-NEXT: fmov x0, d0
1695 ; CHECK-NEXT: ret
1696 %op = load <4 x i64>, ptr %a
1697 %res = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %op)
1698 ret i64 %res
1699 }
1701 define i64 @uminv_v8i64(ptr %a) #0 {
1702 ; VBITS_GE_256-LABEL: uminv_v8i64:
1703 ; VBITS_GE_256: // %bb.0:
1704 ; VBITS_GE_256-NEXT: ptrue p0.d, vl4
1705 ; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
1706 ; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
1707 ; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]
1708 ; VBITS_GE_256-NEXT: umin z0.d, p0/m, z0.d, z1.d
1709 ; VBITS_GE_256-NEXT: uminv d0, p0, z0.d
1710 ; VBITS_GE_256-NEXT: fmov x0, d0
1711 ; VBITS_GE_256-NEXT: ret
1712 ;
1713 ; VBITS_GE_512-LABEL: uminv_v8i64:
1714 ; VBITS_GE_512: // %bb.0:
1715 ; VBITS_GE_512-NEXT: ptrue p0.d, vl8
1716 ; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
1717 ; VBITS_GE_512-NEXT: uminv d0, p0, z0.d
1718 ; VBITS_GE_512-NEXT: fmov x0, d0
1719 ; VBITS_GE_512-NEXT: ret
1720 %op = load <8 x i64>, ptr %a
1721 %res = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> %op)
1722 ret i64 %res
1723 }
1725 define i64 @uminv_v16i64(ptr %a) vscale_range(8,0) #0 {
1726 ; CHECK-LABEL: uminv_v16i64:
1727 ; CHECK: // %bb.0:
1728 ; CHECK-NEXT: ptrue p0.d, vl16
1729 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
1730 ; CHECK-NEXT: uminv d0, p0, z0.d
1731 ; CHECK-NEXT: fmov x0, d0
1732 ; CHECK-NEXT: ret
1733 %op = load <16 x i64>, ptr %a
1734 %res = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> %op)
1735 ret i64 %res
1736 }
1738 define i64 @uminv_v32i64(ptr %a) vscale_range(16,0) #0 {
1739 ; CHECK-LABEL: uminv_v32i64:
1740 ; CHECK: // %bb.0:
1741 ; CHECK-NEXT: ptrue p0.d, vl32
1742 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
1743 ; CHECK-NEXT: uminv d0, p0, z0.d
1744 ; CHECK-NEXT: fmov x0, d0
1745 ; CHECK-NEXT: ret
1746 %op = load <32 x i64>, ptr %a
1747 %res = call i64 @llvm.vector.reduce.umin.v32i64(<32 x i64> %op)
1748 ret i64 %res
1749 }
1751 attributes #0 = { "target-features"="+sve" }
1753 declare i8 @llvm.vector.reduce.add.v8i8(<8 x i8>)
1754 declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)
1755 declare i8 @llvm.vector.reduce.add.v32i8(<32 x i8>)
1756 declare i8 @llvm.vector.reduce.add.v64i8(<64 x i8>)
1757 declare i8 @llvm.vector.reduce.add.v128i8(<128 x i8>)
1758 declare i8 @llvm.vector.reduce.add.v256i8(<256 x i8>)
1760 declare i16 @llvm.vector.reduce.add.v4i16(<4 x i16>)
1761 declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
1762 declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)
1763 declare i16 @llvm.vector.reduce.add.v32i16(<32 x i16>)
1764 declare i16 @llvm.vector.reduce.add.v64i16(<64 x i16>)
1765 declare i16 @llvm.vector.reduce.add.v128i16(<128 x i16>)
1767 declare i32 @llvm.vector.reduce.add.v2i32(<2 x i32>)
1768 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
1769 declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
1770 declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
1771 declare i32 @llvm.vector.reduce.add.v32i32(<32 x i32>)
1772 declare i32 @llvm.vector.reduce.add.v64i32(<64 x i32>)
1774 declare i64 @llvm.vector.reduce.add.v1i64(<1 x i64>)
1775 declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)
1776 declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
1777 declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64>)
1778 declare i64 @llvm.vector.reduce.add.v16i64(<16 x i64>)
1779 declare i64 @llvm.vector.reduce.add.v32i64(<32 x i64>)
1781 declare i8 @llvm.vector.reduce.smax.v8i8(<8 x i8>)
1782 declare i8 @llvm.vector.reduce.smax.v16i8(<16 x i8>)
1783 declare i8 @llvm.vector.reduce.smax.v32i8(<32 x i8>)
1784 declare i8 @llvm.vector.reduce.smax.v64i8(<64 x i8>)
1785 declare i8 @llvm.vector.reduce.smax.v128i8(<128 x i8>)
1786 declare i8 @llvm.vector.reduce.smax.v256i8(<256 x i8>)
1788 declare i16 @llvm.vector.reduce.smax.v4i16(<4 x i16>)
1789 declare i16 @llvm.vector.reduce.smax.v8i16(<8 x i16>)
1790 declare i16 @llvm.vector.reduce.smax.v16i16(<16 x i16>)
1791 declare i16 @llvm.vector.reduce.smax.v32i16(<32 x i16>)
1792 declare i16 @llvm.vector.reduce.smax.v64i16(<64 x i16>)
1793 declare i16 @llvm.vector.reduce.smax.v128i16(<128 x i16>)
1795 declare i32 @llvm.vector.reduce.smax.v2i32(<2 x i32>)
1796 declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)
1797 declare i32 @llvm.vector.reduce.smax.v8i32(<8 x i32>)
1798 declare i32 @llvm.vector.reduce.smax.v16i32(<16 x i32>)
1799 declare i32 @llvm.vector.reduce.smax.v32i32(<32 x i32>)
1800 declare i32 @llvm.vector.reduce.smax.v64i32(<64 x i32>)
1802 declare i64 @llvm.vector.reduce.smax.v1i64(<1 x i64>)
1803 declare i64 @llvm.vector.reduce.smax.v2i64(<2 x i64>)
1804 declare i64 @llvm.vector.reduce.smax.v4i64(<4 x i64>)
1805 declare i64 @llvm.vector.reduce.smax.v8i64(<8 x i64>)
1806 declare i64 @llvm.vector.reduce.smax.v16i64(<16 x i64>)
1807 declare i64 @llvm.vector.reduce.smax.v32i64(<32 x i64>)
1809 declare i8 @llvm.vector.reduce.smin.v8i8(<8 x i8>)
1810 declare i8 @llvm.vector.reduce.smin.v16i8(<16 x i8>)
1811 declare i8 @llvm.vector.reduce.smin.v32i8(<32 x i8>)
1812 declare i8 @llvm.vector.reduce.smin.v64i8(<64 x i8>)
1813 declare i8 @llvm.vector.reduce.smin.v128i8(<128 x i8>)
1814 declare i8 @llvm.vector.reduce.smin.v256i8(<256 x i8>)
1816 declare i16 @llvm.vector.reduce.smin.v4i16(<4 x i16>)
1817 declare i16 @llvm.vector.reduce.smin.v8i16(<8 x i16>)
1818 declare i16 @llvm.vector.reduce.smin.v16i16(<16 x i16>)
1819 declare i16 @llvm.vector.reduce.smin.v32i16(<32 x i16>)
1820 declare i16 @llvm.vector.reduce.smin.v64i16(<64 x i16>)
1821 declare i16 @llvm.vector.reduce.smin.v128i16(<128 x i16>)
1823 declare i32 @llvm.vector.reduce.smin.v2i32(<2 x i32>)
1824 declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)
1825 declare i32 @llvm.vector.reduce.smin.v8i32(<8 x i32>)
1826 declare i32 @llvm.vector.reduce.smin.v16i32(<16 x i32>)
1827 declare i32 @llvm.vector.reduce.smin.v32i32(<32 x i32>)
1828 declare i32 @llvm.vector.reduce.smin.v64i32(<64 x i32>)
1830 declare i64 @llvm.vector.reduce.smin.v1i64(<1 x i64>)
1831 declare i64 @llvm.vector.reduce.smin.v2i64(<2 x i64>)
1832 declare i64 @llvm.vector.reduce.smin.v4i64(<4 x i64>)
1833 declare i64 @llvm.vector.reduce.smin.v8i64(<8 x i64>)
1834 declare i64 @llvm.vector.reduce.smin.v16i64(<16 x i64>)
1835 declare i64 @llvm.vector.reduce.smin.v32i64(<32 x i64>)
1837 declare i8 @llvm.vector.reduce.umax.v8i8(<8 x i8>)
1838 declare i8 @llvm.vector.reduce.umax.v16i8(<16 x i8>)
1839 declare i8 @llvm.vector.reduce.umax.v32i8(<32 x i8>)
1840 declare i8 @llvm.vector.reduce.umax.v64i8(<64 x i8>)
1841 declare i8 @llvm.vector.reduce.umax.v128i8(<128 x i8>)
1842 declare i8 @llvm.vector.reduce.umax.v256i8(<256 x i8>)
1844 declare i16 @llvm.vector.reduce.umax.v4i16(<4 x i16>)
1845 declare i16 @llvm.vector.reduce.umax.v8i16(<8 x i16>)
1846 declare i16 @llvm.vector.reduce.umax.v16i16(<16 x i16>)
1847 declare i16 @llvm.vector.reduce.umax.v32i16(<32 x i16>)
1848 declare i16 @llvm.vector.reduce.umax.v64i16(<64 x i16>)
1849 declare i16 @llvm.vector.reduce.umax.v128i16(<128 x i16>)
1851 declare i32 @llvm.vector.reduce.umax.v2i32(<2 x i32>)
1852 declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)
1853 declare i32 @llvm.vector.reduce.umax.v8i32(<8 x i32>)
1854 declare i32 @llvm.vector.reduce.umax.v16i32(<16 x i32>)
1855 declare i32 @llvm.vector.reduce.umax.v32i32(<32 x i32>)
1856 declare i32 @llvm.vector.reduce.umax.v64i32(<64 x i32>)
1858 declare i64 @llvm.vector.reduce.umax.v1i64(<1 x i64>)
1859 declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64>)
1860 declare i64 @llvm.vector.reduce.umax.v4i64(<4 x i64>)
1861 declare i64 @llvm.vector.reduce.umax.v8i64(<8 x i64>)
1862 declare i64 @llvm.vector.reduce.umax.v16i64(<16 x i64>)
1863 declare i64 @llvm.vector.reduce.umax.v32i64(<32 x i64>)
1865 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
1866 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
1867 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
1868 declare i8 @llvm.vector.reduce.umin.v64i8(<64 x i8>)
1869 declare i8 @llvm.vector.reduce.umin.v128i8(<128 x i8>)
1870 declare i8 @llvm.vector.reduce.umin.v256i8(<256 x i8>)
1872 declare i16 @llvm.vector.reduce.umin.v4i16(<4 x i16>)
1873 declare i16 @llvm.vector.reduce.umin.v8i16(<8 x i16>)
1874 declare i16 @llvm.vector.reduce.umin.v16i16(<16 x i16>)
1875 declare i16 @llvm.vector.reduce.umin.v32i16(<32 x i16>)
1876 declare i16 @llvm.vector.reduce.umin.v64i16(<64 x i16>)
1877 declare i16 @llvm.vector.reduce.umin.v128i16(<128 x i16>)
1879 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
1880 declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)
1881 declare i32 @llvm.vector.reduce.umin.v8i32(<8 x i32>)
1882 declare i32 @llvm.vector.reduce.umin.v16i32(<16 x i32>)
1883 declare i32 @llvm.vector.reduce.umin.v32i32(<32 x i32>)
1884 declare i32 @llvm.vector.reduce.umin.v64i32(<64 x i32>)
1886 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
1887 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
1888 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
1889 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
1890 declare i64 @llvm.vector.reduce.umin.v16i64(<16 x i64>)
1891 declare i64 @llvm.vector.reduce.umin.v32i64(<32 x i64>)