| blob | 933c6506d02709a6b9056d15ee877fa373f4d9ce |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
4 define i32 @mullohi_u32(i32 %arg, i32 %arg1, ptr %arg2) {
5 ; CHECK-LABEL: mullohi_u32:
6 ; CHECK: ; %bb.0: ; %bb
7 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v1, v0, 0
9 ; CHECK-NEXT: flat_store_dword v[2:3], v1
10 ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
11 ; CHECK-NEXT: s_setpc_b64 s[30:31]
12 bb:
13 %i = zext i32 %arg to i64
14 %i3 = zext i32 %arg1 to i64
15 %i4 = mul nuw i64 %i3, %i
16 %i5 = lshr i64 %i4, 32
17 %i6 = trunc i64 %i5 to i32
18 store i32 %i6, ptr %arg2, align 4
19 %i7 = trunc i64 %i4 to i32
20 ret i32 %i7
21 }
23 define i32 @mullohi_s32(i32 %arg, i32 %arg1, ptr %arg2) {
24 ; CHECK-LABEL: mullohi_s32:
25 ; CHECK: ; %bb.0: ; %bb
26 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
27 ; CHECK-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v1, v0, 0
28 ; CHECK-NEXT: flat_store_dword v[2:3], v1
29 ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
30 ; CHECK-NEXT: s_setpc_b64 s[30:31]
31 bb:
32 %i = sext i32 %arg to i64
33 %i3 = sext i32 %arg1 to i64
34 %i4 = mul nsw i64 %i3, %i
35 %i5 = ashr i64 %i4, 32
36 %i6 = trunc i64 %i5 to i32
37 store i32 %i6, ptr %arg2, align 4
38 %i7 = trunc i64 %i4 to i32
39 ret i32 %i7
40 }
42 define i32 @mullohi_u32_non_const_shift(i32 %arg, i32 %arg1, ptr %arg2, i64 %shift) {
43 ; CHECK-LABEL: mullohi_u32_non_const_shift:
44 ; CHECK: ; %bb.0: ; %bb
45 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
46 ; CHECK-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v1, v0, 0
47 ; CHECK-NEXT: v_lshrrev_b64 v[0:1], v4, v[5:6]
48 ; CHECK-NEXT: flat_store_dword v[2:3], v6
49 ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
50 ; CHECK-NEXT: s_setpc_b64 s[30:31]
51 bb:
52 %i = zext i32 %arg to i64
53 %i3 = zext i32 %arg1 to i64
54 %i4 = mul nuw i64 %i3, %i
55 %i5 = lshr i64 %i4, 32
56 %i6 = trunc i64 %i5 to i32
57 store i32 %i6, ptr %arg2, align 4
58 %i7 = lshr i64 %i4, %shift
59 %i8 = trunc i64 %i7 to i32
60 ret i32 %i8
61 }
63 define <2 x i32> @mullohi_2xu32(<2 x i32> %arg, <2 x i32> %arg1, ptr %arg2) {
64 ; CHECK-LABEL: mullohi_2xu32:
65 ; CHECK: ; %bb.0: ; %bb
66 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
67 ; CHECK-NEXT: v_mov_b32_e32 v6, v1
68 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v0, 0
69 ; CHECK-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v3, v6, 0
70 ; CHECK-NEXT: v_mov_b32_e32 v6, v1
71 ; CHECK-NEXT: v_mov_b32_e32 v7, v3
72 ; CHECK-NEXT: v_mov_b32_e32 v1, v2
73 ; CHECK-NEXT: flat_store_dwordx2 v[4:5], v[6:7]
74 ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
75 ; CHECK-NEXT: s_setpc_b64 s[30:31]
76 bb:
77 %i = zext <2 x i32> %arg to <2 x i64>
78 %i3 = zext <2 x i32> %arg1 to <2 x i64>
79 %i4 = mul nuw <2 x i64> %i3, %i
80 %i5 = lshr <2 x i64> %i4, <i64 32, i64 32>
81 %i6 = trunc <2 x i64> %i5 to <2 x i32>
82 store <2 x i32> %i6, ptr %arg2, align 8
83 %i7 = trunc <2 x i64> %i4 to <2 x i32>
84 ret <2 x i32> %i7
85 }
87 define i8 @mullohi_illegal_ty(i8 %arg, i8 %arg1, ptr %arg2) {
88 ; CHECK-LABEL: mullohi_illegal_ty:
89 ; CHECK: ; %bb.0: ; %bb
90 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
91 ; CHECK-NEXT: v_mul_lo_u16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
92 ; CHECK-NEXT: v_lshrrev_b16_e32 v1, 8, v0
93 ; CHECK-NEXT: flat_store_byte v[2:3], v1
94 ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
95 ; CHECK-NEXT: s_setpc_b64 s[30:31]
96 bb:
97 %i = zext i8 %arg to i16
98 %i3 = zext i8 %arg1 to i16
99 %i4 = mul nuw i16 %i3, %i
100 %i5 = lshr i16 %i4, 8
101 %i6 = trunc i16 %i5 to i8
102 store i8 %i6, ptr %arg2, align 1
103 %i7 = trunc i16 %i4 to i8
104 ret i8 %i7
105 }
107 define i32 @mul_one_bit_low_hi_u32(i32 %arg, i32 %arg1, ptr %arg2) {
108 ; CHECK-LABEL: mul_one_bit_low_hi_u32:
109 ; CHECK: ; %bb.0: ; %bb
110 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
111 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v1, v0, 0
112 ; CHECK-NEXT: v_alignbit_b32 v0, v1, v0, 31
113 ; CHECK-NEXT: flat_store_dword v[2:3], v1
114 ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
115 ; CHECK-NEXT: s_setpc_b64 s[30:31]
116 bb:
117 %i = zext i32 %arg to i64
118 %i3 = zext i32 %arg1 to i64
119 %i4 = mul nsw i64 %i3, %i
120 %i5 = lshr i64 %i4, 32
121 %i6 = trunc i64 %i5 to i32
122 store i32 %i6, ptr %arg2, align 4
123 %i7 = lshr i64 %i4, 31
124 %i8 = trunc i64 %i7 to i32
125 ret i32 %i8
126 }
128 define i32 @mul_one_bit_hi_hi_u32_lshr_lshr(i32 %arg, i32 %arg1, ptr %arg2) {
129 ; CHECK-LABEL: mul_one_bit_hi_hi_u32_lshr_lshr:
130 ; CHECK: ; %bb.0: ; %bb
131 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
132 ; CHECK-NEXT: v_mul_hi_u32 v0, v1, v0
133 ; CHECK-NEXT: flat_store_dword v[2:3], v0
134 ; CHECK-NEXT: v_lshrrev_b32_e32 v0, 1, v0
135 ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
136 ; CHECK-NEXT: s_setpc_b64 s[30:31]
137 bb:
138 %i = zext i32 %arg to i64
139 %i3 = zext i32 %arg1 to i64
140 %i4 = mul nsw i64 %i3, %i
141 %i5 = lshr i64 %i4, 32
142 %i6 = trunc i64 %i5 to i32
143 store i32 %i6, ptr %arg2, align 4
144 %i7 = lshr i64 %i4, 33
145 %i8 = trunc i64 %i7 to i32
146 ret i32 %i8
147 }
149 define i32 @mul_one_bit_hi_hi_u32_lshr_ashr(i32 %arg, i32 %arg1, ptr %arg2) {
150 ; CHECK-LABEL: mul_one_bit_hi_hi_u32_lshr_ashr:
151 ; CHECK: ; %bb.0: ; %bb
152 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
153 ; CHECK-NEXT: v_mul_hi_u32 v4, v1, v0
154 ; CHECK-NEXT: v_ashrrev_i64 v[0:1], 33, v[3:4]
155 ; CHECK-NEXT: flat_store_dword v[2:3], v4
156 ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
157 ; CHECK-NEXT: s_setpc_b64 s[30:31]
158 bb:
159 %i = zext i32 %arg to i64
160 %i3 = zext i32 %arg1 to i64
161 %i4 = mul nsw i64 %i3, %i
162 %i5 = lshr i64 %i4, 32
163 %i6 = trunc i64 %i5 to i32
164 store i32 %i6, ptr %arg2, align 4
165 %i7 = ashr i64 %i4, 33
166 %i8 = trunc i64 %i7 to i32
167 ret i32 %i8
168 }