| blob | 17e509acfb6e63c0c01594061692795970c95a87 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn < %s | FileCheck --check-prefixes=SI,FUNC %s
3 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga < %s | FileCheck --check-prefixes=VI,FUNC %s
5 define amdgpu_kernel void @fneg_fabsf_fadd_f32(ptr addrspace(1) %out, float %x, float %y) {
6 ; SI-LABEL: fneg_fabsf_fadd_f32:
7 ; SI: ; %bb.0:
8 ; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
9 ; SI-NEXT: s_mov_b32 s7, 0xf000
10 ; SI-NEXT: s_mov_b32 s6, -1
11 ; SI-NEXT: s_waitcnt lgkmcnt(0)
12 ; SI-NEXT: s_mov_b32 s4, s0
13 ; SI-NEXT: s_mov_b32 s5, s1
14 ; SI-NEXT: v_mov_b32_e32 v0, s2
15 ; SI-NEXT: v_sub_f32_e64 v0, s3, |v0|
16 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
17 ; SI-NEXT: s_endpgm
18 ;
19 ; VI-LABEL: fneg_fabsf_fadd_f32:
20 ; VI: ; %bb.0:
21 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
22 ; VI-NEXT: s_waitcnt lgkmcnt(0)
23 ; VI-NEXT: v_mov_b32_e32 v0, s2
24 ; VI-NEXT: v_sub_f32_e64 v2, s3, |v0|
25 ; VI-NEXT: v_mov_b32_e32 v0, s0
26 ; VI-NEXT: v_mov_b32_e32 v1, s1
27 ; VI-NEXT: flat_store_dword v[0:1], v2
28 ; VI-NEXT: s_endpgm
29 %fabs = call float @llvm.fabs.f32(float %x)
30 %fsub = fsub float -0.000000e+00, %fabs
31 %fadd = fadd float %y, %fsub
32 store float %fadd, ptr addrspace(1) %out, align 4
33 ret void
34 }
36 define amdgpu_kernel void @fneg_fabsf_fmul_f32(ptr addrspace(1) %out, float %x, float %y) {
37 ; SI-LABEL: fneg_fabsf_fmul_f32:
38 ; SI: ; %bb.0:
39 ; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
40 ; SI-NEXT: s_mov_b32 s7, 0xf000
41 ; SI-NEXT: s_mov_b32 s6, -1
42 ; SI-NEXT: s_waitcnt lgkmcnt(0)
43 ; SI-NEXT: s_mov_b32 s4, s0
44 ; SI-NEXT: s_mov_b32 s5, s1
45 ; SI-NEXT: v_mov_b32_e32 v0, s2
46 ; SI-NEXT: v_mul_f32_e64 v0, s3, -|v0|
47 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
48 ; SI-NEXT: s_endpgm
49 ;
50 ; VI-LABEL: fneg_fabsf_fmul_f32:
51 ; VI: ; %bb.0:
52 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
53 ; VI-NEXT: s_waitcnt lgkmcnt(0)
54 ; VI-NEXT: v_mov_b32_e32 v0, s2
55 ; VI-NEXT: v_mul_f32_e64 v2, s3, -|v0|
56 ; VI-NEXT: v_mov_b32_e32 v0, s0
57 ; VI-NEXT: v_mov_b32_e32 v1, s1
58 ; VI-NEXT: flat_store_dword v[0:1], v2
59 ; VI-NEXT: s_endpgm
60 %fabs = call float @llvm.fabs.f32(float %x)
61 %fsub = fsub float -0.000000e+00, %fabs
62 %fmul = fmul float %y, %fsub
63 store float %fmul, ptr addrspace(1) %out, align 4
64 ret void
65 }
67 define amdgpu_kernel void @fneg_fabsf_free_f32(ptr addrspace(1) %out, i32 %in) {
68 ; SI-LABEL: fneg_fabsf_free_f32:
69 ; SI: ; %bb.0:
70 ; SI-NEXT: s_load_dword s2, s[4:5], 0xb
71 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
72 ; SI-NEXT: s_mov_b32 s3, 0xf000
73 ; SI-NEXT: s_waitcnt lgkmcnt(0)
74 ; SI-NEXT: s_or_b32 s4, s2, 0x80000000
75 ; SI-NEXT: s_mov_b32 s2, -1
76 ; SI-NEXT: v_mov_b32_e32 v0, s4
77 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
78 ; SI-NEXT: s_endpgm
79 ;
80 ; VI-LABEL: fneg_fabsf_free_f32:
81 ; VI: ; %bb.0:
82 ; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
83 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
84 ; VI-NEXT: s_waitcnt lgkmcnt(0)
85 ; VI-NEXT: s_bitset1_b32 s2, 31
86 ; VI-NEXT: v_mov_b32_e32 v0, s0
87 ; VI-NEXT: v_mov_b32_e32 v1, s1
88 ; VI-NEXT: v_mov_b32_e32 v2, s2
89 ; VI-NEXT: flat_store_dword v[0:1], v2
90 ; VI-NEXT: s_endpgm
91 %bc = bitcast i32 %in to float
92 %fabs = call float @llvm.fabs.f32(float %bc)
93 %fsub = fsub float -0.000000e+00, %fabs
94 store float %fsub, ptr addrspace(1) %out
95 ret void
96 }
98 define amdgpu_kernel void @fneg_fabsf_fn_free_f32(ptr addrspace(1) %out, i32 %in) {
99 ; SI-LABEL: fneg_fabsf_fn_free_f32:
100 ; SI: ; %bb.0:
101 ; SI-NEXT: s_load_dword s2, s[4:5], 0xb
102 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
103 ; SI-NEXT: s_mov_b32 s3, 0xf000
104 ; SI-NEXT: s_waitcnt lgkmcnt(0)
105 ; SI-NEXT: s_or_b32 s4, s2, 0x80000000
106 ; SI-NEXT: s_mov_b32 s2, -1
107 ; SI-NEXT: v_mov_b32_e32 v0, s4
108 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
109 ; SI-NEXT: s_endpgm
110 ;
111 ; VI-LABEL: fneg_fabsf_fn_free_f32:
112 ; VI: ; %bb.0:
113 ; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
114 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
115 ; VI-NEXT: s_waitcnt lgkmcnt(0)
116 ; VI-NEXT: s_bitset1_b32 s2, 31
117 ; VI-NEXT: v_mov_b32_e32 v0, s0
118 ; VI-NEXT: v_mov_b32_e32 v1, s1
119 ; VI-NEXT: v_mov_b32_e32 v2, s2
120 ; VI-NEXT: flat_store_dword v[0:1], v2
121 ; VI-NEXT: s_endpgm
122 %bc = bitcast i32 %in to float
123 %fabs = call float @fabsf(float %bc)
124 %fsub = fsub float -0.000000e+00, %fabs
125 store float %fsub, ptr addrspace(1) %out
126 ret void
127 }
129 define amdgpu_kernel void @fneg_fabsf_f32(ptr addrspace(1) %out, float %in) {
130 ; SI-LABEL: fneg_fabsf_f32:
131 ; SI: ; %bb.0:
132 ; SI-NEXT: s_load_dword s2, s[4:5], 0xb
133 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
134 ; SI-NEXT: s_mov_b32 s3, 0xf000
135 ; SI-NEXT: s_waitcnt lgkmcnt(0)
136 ; SI-NEXT: s_or_b32 s4, s2, 0x80000000
137 ; SI-NEXT: s_mov_b32 s2, -1
138 ; SI-NEXT: v_mov_b32_e32 v0, s4
139 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
140 ; SI-NEXT: s_endpgm
141 ;
142 ; VI-LABEL: fneg_fabsf_f32:
143 ; VI: ; %bb.0:
144 ; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
145 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
146 ; VI-NEXT: s_waitcnt lgkmcnt(0)
147 ; VI-NEXT: s_bitset1_b32 s2, 31
148 ; VI-NEXT: v_mov_b32_e32 v0, s0
149 ; VI-NEXT: v_mov_b32_e32 v1, s1
150 ; VI-NEXT: v_mov_b32_e32 v2, s2
151 ; VI-NEXT: flat_store_dword v[0:1], v2
152 ; VI-NEXT: s_endpgm
153 %fabs = call float @llvm.fabs.f32(float %in)
154 %fsub = fsub float -0.000000e+00, %fabs
155 store float %fsub, ptr addrspace(1) %out, align 4
156 ret void
157 }
159 define amdgpu_kernel void @v_fneg_fabsf_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
160 ; SI-LABEL: v_fneg_fabsf_f32:
161 ; SI: ; %bb.0:
162 ; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
163 ; SI-NEXT: s_mov_b32 s7, 0xf000
164 ; SI-NEXT: s_mov_b32 s6, -1
165 ; SI-NEXT: s_mov_b32 s10, s6
166 ; SI-NEXT: s_mov_b32 s11, s7
167 ; SI-NEXT: s_waitcnt lgkmcnt(0)
168 ; SI-NEXT: s_mov_b32 s8, s2
169 ; SI-NEXT: s_mov_b32 s9, s3
170 ; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
171 ; SI-NEXT: s_mov_b32 s4, s0
172 ; SI-NEXT: s_mov_b32 s5, s1
173 ; SI-NEXT: s_waitcnt vmcnt(0)
174 ; SI-NEXT: v_or_b32_e32 v0, 0x80000000, v0
175 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
176 ; SI-NEXT: s_endpgm
177 ;
178 ; VI-LABEL: v_fneg_fabsf_f32:
179 ; VI: ; %bb.0:
180 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
181 ; VI-NEXT: s_waitcnt lgkmcnt(0)
182 ; VI-NEXT: v_mov_b32_e32 v0, s2
183 ; VI-NEXT: v_mov_b32_e32 v1, s3
184 ; VI-NEXT: flat_load_dword v2, v[0:1]
185 ; VI-NEXT: v_mov_b32_e32 v0, s0
186 ; VI-NEXT: v_mov_b32_e32 v1, s1
187 ; VI-NEXT: s_waitcnt vmcnt(0)
188 ; VI-NEXT: v_or_b32_e32 v2, 0x80000000, v2
189 ; VI-NEXT: flat_store_dword v[0:1], v2
190 ; VI-NEXT: s_endpgm
191 %val = load float, ptr addrspace(1) %in, align 4
192 %fabs = call float @llvm.fabs.f32(float %val)
193 %fsub = fsub float -0.000000e+00, %fabs
194 store float %fsub, ptr addrspace(1) %out, align 4
195 ret void
196 }
198 define amdgpu_kernel void @fneg_fabsf_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
199 ; SI-LABEL: fneg_fabsf_v2f32:
200 ; SI: ; %bb.0:
201 ; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
202 ; SI-NEXT: s_mov_b32 s7, 0xf000
203 ; SI-NEXT: s_waitcnt lgkmcnt(0)
204 ; SI-NEXT: s_bitset1_b32 s3, 31
205 ; SI-NEXT: s_bitset1_b32 s2, 31
206 ; SI-NEXT: s_mov_b32 s6, -1
207 ; SI-NEXT: s_mov_b32 s4, s0
208 ; SI-NEXT: s_mov_b32 s5, s1
209 ; SI-NEXT: v_mov_b32_e32 v0, s2
210 ; SI-NEXT: v_mov_b32_e32 v1, s3
211 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
212 ; SI-NEXT: s_endpgm
213 ;
214 ; VI-LABEL: fneg_fabsf_v2f32:
215 ; VI: ; %bb.0:
216 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
217 ; VI-NEXT: s_waitcnt lgkmcnt(0)
218 ; VI-NEXT: s_bitset1_b32 s3, 31
219 ; VI-NEXT: s_bitset1_b32 s2, 31
220 ; VI-NEXT: v_mov_b32_e32 v3, s1
221 ; VI-NEXT: v_mov_b32_e32 v0, s2
222 ; VI-NEXT: v_mov_b32_e32 v1, s3
223 ; VI-NEXT: v_mov_b32_e32 v2, s0
224 ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
225 ; VI-NEXT: s_endpgm
226 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
227 %fsub = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %fabs
228 store <2 x float> %fsub, ptr addrspace(1) %out
229 ret void
230 }
232 define amdgpu_kernel void @fneg_fabsf_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
233 ; SI-LABEL: fneg_fabsf_v4f32:
234 ; SI: ; %bb.0:
235 ; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
236 ; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
237 ; SI-NEXT: s_mov_b32 s7, 0xf000
238 ; SI-NEXT: s_waitcnt lgkmcnt(0)
239 ; SI-NEXT: s_bitset1_b32 s3, 31
240 ; SI-NEXT: s_bitset1_b32 s2, 31
241 ; SI-NEXT: s_bitset1_b32 s1, 31
242 ; SI-NEXT: s_bitset1_b32 s0, 31
243 ; SI-NEXT: s_mov_b32 s6, -1
244 ; SI-NEXT: v_mov_b32_e32 v0, s0
245 ; SI-NEXT: v_mov_b32_e32 v1, s1
246 ; SI-NEXT: v_mov_b32_e32 v2, s2
247 ; SI-NEXT: v_mov_b32_e32 v3, s3
248 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
249 ; SI-NEXT: s_endpgm
250 ;
251 ; VI-LABEL: fneg_fabsf_v4f32:
252 ; VI: ; %bb.0:
253 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
254 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
255 ; VI-NEXT: s_waitcnt lgkmcnt(0)
256 ; VI-NEXT: s_bitset1_b32 s3, 31
257 ; VI-NEXT: s_bitset1_b32 s2, 31
258 ; VI-NEXT: s_bitset1_b32 s1, 31
259 ; VI-NEXT: s_bitset1_b32 s0, 31
260 ; VI-NEXT: v_mov_b32_e32 v4, s4
261 ; VI-NEXT: v_mov_b32_e32 v0, s0
262 ; VI-NEXT: v_mov_b32_e32 v1, s1
263 ; VI-NEXT: v_mov_b32_e32 v2, s2
264 ; VI-NEXT: v_mov_b32_e32 v3, s3
265 ; VI-NEXT: v_mov_b32_e32 v5, s5
266 ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
267 ; VI-NEXT: s_endpgm
268 %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
269 %fsub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %fabs
270 store <4 x float> %fsub, ptr addrspace(1) %out
271 ret void
272 }
274 declare float @fabsf(float) readnone
275 declare float @llvm.fabs.f32(float) readnone
276 declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone
277 declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone
279 !llvm.module.flags = !{!0}
280 !0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
281 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
282 ; FUNC: {{.*}}