llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
   2 # RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
   3
   4 # The constant is 0xffffffff80000000. It is 64-bit negative constant, but it passes the test
   5 # isInt<32>(). Nonetheless it is not a legal literal for a binary or unsigned operand and
   6 # cannot be used right in the shift as HW will zero extend it.
   7
   8 ---
   9 name:            imm64_shift_int32_const_0xffffffff80000000
  10 body: |
  11   bb.0:
  12     ; GCN-LABEL: name: imm64_shift_int32_const_0xffffffff80000000
  13     ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -2147483648
  14     ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc
  15     ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
  16     %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 18446744071562067968
  17     %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
  18     S_ENDPGM 0, implicit %1
  19
  20 ...
  21
  22 ---
  23 name:            imm64_shift_int32_const_0xffffffff
  24 body: |
  25   bb.0:
  26     ; GCN-LABEL: name: imm64_shift_int32_const_0xffffffff
  27     ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
  28     ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc
  29     ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
  30     %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
  31     %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
  32     S_ENDPGM 0, implicit %1
  33
  34 ...
  35
  36 ---
  37 name:            imm64_shift_int32_const_0x80000000
  38 body: |
  39   bb.0:
  40     ; GCN-LABEL: name: imm64_shift_int32_const_0x80000000
  41     ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 2147483648
  42     ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc
  43     ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
  44     %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 2147483648
  45     %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
  46     S_ENDPGM 0, implicit %1
  47
  48 ...
  49
  50 ---
  51 name:            imm64_shift_int32_const_0x7fffffff
  52 body: |
  53   bb.0:
  54     ; GCN-LABEL: name: imm64_shift_int32_const_0x7fffffff
  55     ; GCN: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 2147483647, 1, implicit-def $scc
  56     ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
  57     %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 2147483647
  58     %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
  59     S_ENDPGM 0, implicit %1
  60
  61 ...
  62
  63 ---
  64 name:            imm64_shift_int32_const_0x1ffffffff
  65 body: |
  66   bb.0:
  67     ; GCN-LABEL: name: imm64_shift_int32_const_0x1ffffffff
  68     ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 8589934591
  69     ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc
  70     ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
  71     %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 8589934591
  72     %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
  73     S_ENDPGM 0, implicit %1
  74
  75 ...
  76
  77 ---
  78 name:            imm64_shift_int32_const_0xffffffffffffffff
  79 body: |
  80   bb.0:
  81     ; GCN-LABEL: name: imm64_shift_int32_const_0xffffffffffffffff
  82     ; GCN: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 -1, 1, implicit-def $scc
  83     ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
  84     %0:sreg_64 = S_MOV_B64_IMM_PSEUDO -1
  85     %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
  86     S_ENDPGM 0, implicit %1
  87
  88 ...
  89
  90 ---
  91 name:            imm64_ashr_int32_const_0xffffffff
  92 body: |
  93   bb.0:
  94     ; GCN-LABEL: name: imm64_ashr_int32_const_0xffffffff
  95     ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
  96     ; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[S_MOV_B]], 1, implicit-def $scc
  97     ; GCN-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
  98     %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
  99     %1:sreg_64 = S_ASHR_I64 %0, 1, implicit-def $scc
 100     S_ENDPGM 0, implicit %1
 101
 102 ...
 103
 104 ---
 105 name:            imm64_ashr_int32_const_0x7fffffff
 106 body: |
 107   bb.0:
 108     ; GCN-LABEL: name: imm64_ashr_int32_const_0x7fffffff
 109     ; GCN: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 2147483647, 1, implicit-def $scc
 110     ; GCN-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
 111     %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 2147483647
 112     %1:sreg_64 = S_ASHR_I64 %0, 1, implicit-def $scc
 113     S_ENDPGM 0, implicit %1
 114
 115 ...
 116
 117 ---
 118 name:            imm64_ashr_int32_const_0xffffffffffffffff
 119 body: |
 120   bb.0:
 121     ; GCN-LABEL: name: imm64_ashr_int32_const_0xffffffffffffffff
 122     ; GCN: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 -1, 1, implicit-def $scc
 123     ; GCN-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
 124     %0:sreg_64 = S_MOV_B64_IMM_PSEUDO -1
 125     %1:sreg_64 = S_ASHR_I64 %0, 1, implicit-def $scc
 126     S_ENDPGM 0, implicit %1
 127
 128 ...