llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
   2 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-before=greedy,0 -stop-after=virtregrewriter,0 -simplify-mir -o - %s | FileCheck %s
   3 --- |
   4   define void @main() #0 {
   5     ret void
   6   }
   7
   8   attributes #0 = { "amdgpu-waves-per-eu"="10,10" }
   9
  10 ...
  11 ---
  12 name:            main
  13 tracksRegLiveness: true
  14 machineFunctionInfo:
  15   scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
  16   frameOffsetReg:  '$sgpr33'
  17   stackPtrOffsetReg: '$sgpr32'
  18   sgprForEXECCopy: '$sgpr58_sgpr59'
  19 body:             |
  20   ; CHECK-LABEL: name: main
  21   ; CHECK: bb.0:
  22   ; CHECK-NEXT:   liveins: $vgpr0
  23   ; CHECK-NEXT: {{  $}}
  24   ; CHECK-NEXT:   dead renamable $sgpr5 = IMPLICIT_DEF
  25   ; CHECK-NEXT:   dead undef [[DEF:%[0-9]+]].sub0:vreg_64 = IMPLICIT_DEF
  26   ; CHECK-NEXT:   dead renamable $sgpr5 = IMPLICIT_DEF
  27   ; CHECK-NEXT:   dead [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  28   ; CHECK-NEXT:   dead undef [[DEF2:%[0-9]+]].sub0:vreg_64 = IMPLICIT_DEF
  29   ; CHECK-NEXT:   dead renamable $sgpr5 = IMPLICIT_DEF
  30   ; CHECK-NEXT:   dead undef [[DEF3:%[0-9]+]].sub1:vreg_64 = IMPLICIT_DEF
  31   ; CHECK-NEXT:   dead renamable $sgpr5 = IMPLICIT_DEF
  32   ; CHECK-NEXT:   renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = S_LOAD_DWORDX16_IMM undef renamable $sgpr4_sgpr5, 0, 0 :: (invariant load (s512), align 32, addrspace 4)
  33   ; CHECK-NEXT:   renamable $sgpr24 = IMPLICIT_DEF implicit-def $sgpr25
  34   ; CHECK-NEXT:   renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = S_LOAD_DWORDX16_IMM undef renamable $sgpr4_sgpr5, 0, 0 :: (invariant load (s512), align 32, addrspace 4)
  35   ; CHECK-NEXT:   $exec = S_MOV_B64_term undef renamable $sgpr4_sgpr5
  36   ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.5, implicit $exec
  37   ; CHECK-NEXT:   S_BRANCH %bb.4
  38   ; CHECK-NEXT: {{  $}}
  39   ; CHECK-NEXT: bb.1:
  40   ; CHECK-NEXT:   liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x000000000000FFFF
  41   ; CHECK-NEXT: {{  $}}
  42   ; CHECK-NEXT:   $exec = S_MOV_B64_term undef renamable $sgpr4_sgpr5
  43   ; CHECK-NEXT:   S_CBRANCH_EXECNZ %bb.3, implicit $exec
  44   ; CHECK-NEXT: {{  $}}
  45   ; CHECK-NEXT: bb.2:
  46   ; CHECK-NEXT:   liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x000000000000FFFF
  47   ; CHECK-NEXT: {{  $}}
  48   ; CHECK-NEXT:   dead [[IMAGE_SAMPLE_LZ_V1_V2_:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF3]], killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43, undef renamable $sgpr24_sgpr25_sgpr26_sgpr27, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
  49   ; CHECK-NEXT:   dead [[IMAGE_SAMPLE_LZ_V1_V2_1:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF3]], killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, renamable $sgpr24_sgpr25_sgpr26_sgpr27, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
  50   ; CHECK-NEXT:   SI_RETURN
  51   ; CHECK-NEXT: {{  $}}
  52   ; CHECK-NEXT: bb.3:
  53   ; CHECK-NEXT:   liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF
  54   ; CHECK-NEXT: {{  $}}
  55   ; CHECK-NEXT:   renamable $sgpr12 = IMPLICIT_DEF
  56   ; CHECK-NEXT:   renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = IMPLICIT_DEF
  57   ; CHECK-NEXT:   dead undef [[IMAGE_SAMPLE_LZ_V1_V2_2:%[0-9]+]].sub0:vreg_96 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF3]], killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43, renamable $sgpr12_sgpr13_sgpr14_sgpr15, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
  58   ; CHECK-NEXT:   renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = S_LOAD_DWORDX16_IMM undef renamable $sgpr4_sgpr5, 0, 0 :: (invariant load (s512), align 32, addrspace 4)
  59   ; CHECK-NEXT:   renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = IMPLICIT_DEF
  60   ; CHECK-NEXT:   dead undef [[IMAGE_SAMPLE_LZ_V1_V2_3:%[0-9]+]].sub0:vreg_128 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF3]], undef renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, killed renamable $sgpr12_sgpr13_sgpr14_sgpr15, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
  61   ; CHECK-NEXT:   S_BRANCH %bb.2
  62   ; CHECK-NEXT: {{  $}}
  63   ; CHECK-NEXT: bb.4:
  64   ; CHECK-NEXT:   liveins: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x00000000FFFFFFFF
  65   ; CHECK-NEXT: {{  $}}
  66   ; CHECK-NEXT:   renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 = COPY killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
  67   ; CHECK-NEXT:   renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = IMPLICIT_DEF
  68   ; CHECK-NEXT:   dead [[IMAGE_SAMPLE_LZ_V1_V2_4:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF]], killed renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, undef renamable $sgpr24_sgpr25_sgpr26_sgpr27, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
  69   ; CHECK-NEXT:   renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = COPY killed renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27
  70   ; CHECK-NEXT:   S_BRANCH %bb.6
  71   ; CHECK-NEXT: {{  $}}
  72   ; CHECK-NEXT: bb.5:
  73   ; CHECK-NEXT:   liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x000000000000FFFF
  74   ; CHECK-NEXT: {{  $}}
  75   ; CHECK-NEXT:   $exec = S_XOR_B64_term $exec, undef renamable $sgpr4_sgpr5, implicit-def $scc
  76   ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.7, implicit $exec
  77   ; CHECK-NEXT:   S_BRANCH %bb.1
  78   ; CHECK-NEXT: {{  $}}
  79   ; CHECK-NEXT: bb.6:
  80   ; CHECK-NEXT:   liveins: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x00000000FFFFFFFF
  81   ; CHECK-NEXT: {{  $}}
  82   ; CHECK-NEXT:   dead [[IMAGE_SAMPLE_LZ_V1_V2_5:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF]], renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, undef renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
  83   ; CHECK-NEXT:   renamable $sgpr25 = COPY undef renamable $sgpr24, implicit-def $sgpr24
  84   ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.6, implicit undef $vcc
  85   ; CHECK-NEXT:   S_BRANCH %bb.5
  86   ; CHECK-NEXT: {{  $}}
  87   ; CHECK-NEXT: bb.7:
  88   ; CHECK-NEXT:   SI_RETURN
  89   bb.0:
  90     liveins: $vgpr0
  91
  92     undef %0.sub1:sreg_64 = IMPLICIT_DEF
  93     %1:sgpr_512 = IMPLICIT_DEF
  94     undef %2.sub0:vreg_64 = IMPLICIT_DEF
  95     %3:sgpr_256 = IMPLICIT_DEF
  96     undef %4.sub1:sgpr_64 = IMPLICIT_DEF
  97     %5:vgpr_32 = IMPLICIT_DEF
  98     undef %6.sub0:vreg_64 = IMPLICIT_DEF
  99     undef %7.sub1:sreg_64 = IMPLICIT_DEF
 100     undef %8.sub1:vreg_64 = IMPLICIT_DEF
 101     undef %9.sub1:sreg_64 = IMPLICIT_DEF
 102     %10:sgpr_512 = S_LOAD_DWORDX16_IMM undef %0, 0, 0 :: (invariant load (s512), align 32, addrspace 4)
 103     undef %11.sub0:sgpr_128 = IMPLICIT_DEF
 104     %12:sgpr_512 = S_LOAD_DWORDX16_IMM undef %7, 0, 0 :: (invariant load (s512), align 32, addrspace 4)
 105     $exec = S_MOV_B64_term undef %9
 106     S_CBRANCH_EXECZ %bb.5, implicit $exec
 107     S_BRANCH %bb.4
 108
 109   bb.1:
 110     $exec = S_MOV_B64_term undef %9
 111     S_CBRANCH_EXECNZ %bb.3, implicit $exec
 112
 113   bb.2:
 114     %13:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %8, %10.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, undef %11, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
 115     %14:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %8, %12.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, %11, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
 116     SI_RETURN
 117
 118   bb.3:
 119     undef %15.sub0:sgpr_128 = IMPLICIT_DEF
 120     undef %16.sub0:vreg_96 = IMAGE_SAMPLE_LZ_V1_V2 undef %8, %1.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, %15, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
 121     undef %17.sub0:vreg_128 = IMAGE_SAMPLE_LZ_V1_V2 undef %8, undef %10.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, %3.sub0_sub1_sub2_sub3, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
 122     S_BRANCH %bb.2
 123
 124   bb.4:
 125     %18:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %2, %1.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, undef %11, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
 126     S_BRANCH %bb.6
 127
 128   bb.5:
 129     $exec = S_XOR_B64_term $exec, undef %9, implicit-def $scc
 130     S_CBRANCH_EXECZ %bb.7, implicit $exec
 131     S_BRANCH %bb.1
 132
 133   bb.6:
 134     %19:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %2, %10.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, undef %3.sub4_sub5_sub6_sub7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
 135     undef %11.sub1:sgpr_128 = COPY undef %11.sub0
 136     S_CBRANCH_VCCNZ %bb.6, implicit undef $vcc
 137     S_BRANCH %bb.5
 138
 139   bb.7:
 140     SI_RETURN
 141
 142 ...