| blob | b42ba7d75094a631a04b4cbec0222bab813daf37 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ;RUN: llc < %s -mtriple=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s --check-prefixes=PREGFX10
3 ;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefixes=PREGFX10
4 ;RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX10
5 ;RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX11
6 ;RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX12,GFX12-SDAG
7 ;RUN: llc < %s -global-isel -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX12,GFX12-GISEL
9 define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
10 ; PREGFX10-LABEL: buffer_load:
11 ; PREGFX10: ; %bb.0: ; %main_body
12 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
13 ; PREGFX10-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc
14 ; PREGFX10-NEXT: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc
15 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
16 ; PREGFX10-NEXT: ; return to shader part epilog
17 ;
18 ; GFX10-LABEL: buffer_load:
19 ; GFX10: ; %bb.0: ; %main_body
20 ; GFX10-NEXT: s_clause 0x2
21 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
22 ; GFX10-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc
23 ; GFX10-NEXT: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc
24 ; GFX10-NEXT: s_waitcnt vmcnt(0)
25 ; GFX10-NEXT: ; return to shader part epilog
26 ;
27 ; GFX11-LABEL: buffer_load:
28 ; GFX11: ; %bb.0: ; %main_body
29 ; GFX11-NEXT: s_clause 0x2
30 ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0
31 ; GFX11-NEXT: buffer_load_b128 v[4:7], off, s[0:3], 0 glc
32 ; GFX11-NEXT: buffer_load_b128 v[8:11], off, s[0:3], 0 slc
33 ; GFX11-NEXT: s_waitcnt vmcnt(0)
34 ; GFX11-NEXT: ; return to shader part epilog
35 ;
36 ; GFX12-LABEL: buffer_load:
37 ; GFX12: ; %bb.0: ; %main_body
38 ; GFX12-NEXT: s_clause 0x2
39 ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null
40 ; GFX12-NEXT: buffer_load_b128 v[4:7], off, s[0:3], null th:TH_LOAD_NT
41 ; GFX12-NEXT: buffer_load_b128 v[8:11], off, s[0:3], null th:TH_LOAD_HT
42 ; GFX12-NEXT: s_wait_loadcnt 0x0
43 ; GFX12-NEXT: ; return to shader part epilog
44 main_body:
45 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0)
46 %data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 1)
47 %data_slc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 2)
48 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
49 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
50 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
51 ret {<4 x float>, <4 x float>, <4 x float>} %r2
52 }
54 define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load_dlc(<4 x i32> inreg) {
55 ; PREGFX10-LABEL: buffer_load_dlc:
56 ; PREGFX10: ; %bb.0: ; %main_body
57 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
58 ; PREGFX10-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc
59 ; PREGFX10-NEXT: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc
60 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
61 ; PREGFX10-NEXT: ; return to shader part epilog
62 ;
63 ; GFX10-LABEL: buffer_load_dlc:
64 ; GFX10: ; %bb.0: ; %main_body
65 ; GFX10-NEXT: s_clause 0x2
66 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 dlc
67 ; GFX10-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc dlc
68 ; GFX10-NEXT: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc dlc
69 ; GFX10-NEXT: s_waitcnt vmcnt(0)
70 ; GFX10-NEXT: ; return to shader part epilog
71 ;
72 ; GFX11-LABEL: buffer_load_dlc:
73 ; GFX11: ; %bb.0: ; %main_body
74 ; GFX11-NEXT: s_clause 0x2
75 ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 dlc
76 ; GFX11-NEXT: buffer_load_b128 v[4:7], off, s[0:3], 0 glc dlc
77 ; GFX11-NEXT: buffer_load_b128 v[8:11], off, s[0:3], 0 slc dlc
78 ; GFX11-NEXT: s_waitcnt vmcnt(0)
79 ; GFX11-NEXT: ; return to shader part epilog
80 ;
81 ; GFX12-LABEL: buffer_load_dlc:
82 ; GFX12: ; %bb.0: ; %main_body
83 ; GFX12-NEXT: s_clause 0x2
84 ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null th:TH_LOAD_NT_RT
85 ; GFX12-NEXT: buffer_load_b128 v[4:7], off, s[0:3], null th:TH_LOAD_RT_NT
86 ; GFX12-NEXT: buffer_load_b128 v[8:11], off, s[0:3], null th:TH_LOAD_NT_HT
87 ; GFX12-NEXT: s_wait_loadcnt 0x0
88 ; GFX12-NEXT: ; return to shader part epilog
89 main_body:
90 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 4)
91 %data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 5)
92 %data_slc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 6)
93 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
94 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
95 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
96 ret {<4 x float>, <4 x float>, <4 x float>} %r2
97 }
99 define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) {
100 ; PREGFX10-LABEL: buffer_load_immoffs:
101 ; PREGFX10: ; %bb.0: ; %main_body
102 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40
103 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
104 ; PREGFX10-NEXT: ; return to shader part epilog
105 ;
106 ; GFX10-LABEL: buffer_load_immoffs:
107 ; GFX10: ; %bb.0: ; %main_body
108 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40
109 ; GFX10-NEXT: s_waitcnt vmcnt(0)
110 ; GFX10-NEXT: ; return to shader part epilog
111 ;
112 ; GFX11-LABEL: buffer_load_immoffs:
113 ; GFX11: ; %bb.0: ; %main_body
114 ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:40
115 ; GFX11-NEXT: s_waitcnt vmcnt(0)
116 ; GFX11-NEXT: ; return to shader part epilog
117 ;
118 ; GFX12-LABEL: buffer_load_immoffs:
119 ; GFX12: ; %bb.0: ; %main_body
120 ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null offset:40
121 ; GFX12-NEXT: s_wait_loadcnt 0x0
122 ; GFX12-NEXT: ; return to shader part epilog
123 main_body:
124 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 40, i32 0, i32 0)
125 ret <4 x float> %data
126 }
128 define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) {
129 ; PREGFX10-LABEL: buffer_load_immoffs_large:
130 ; PREGFX10: ; %bb.0: ; %main_body
131 ; PREGFX10-NEXT: s_movk_i32 s4, 0x1ffc
132 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], s4 offset:4
133 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
134 ; PREGFX10-NEXT: ; return to shader part epilog
135 ;
136 ; GFX10-LABEL: buffer_load_immoffs_large:
137 ; GFX10: ; %bb.0: ; %main_body
138 ; GFX10-NEXT: s_movk_i32 s4, 0x1ffc
139 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], s4 offset:4
140 ; GFX10-NEXT: s_waitcnt vmcnt(0)
141 ; GFX10-NEXT: ; return to shader part epilog
142 ;
143 ; GFX11-LABEL: buffer_load_immoffs_large:
144 ; GFX11: ; %bb.0: ; %main_body
145 ; GFX11-NEXT: s_movk_i32 s4, 0x1ffc
146 ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], s4 offset:4
147 ; GFX11-NEXT: s_waitcnt vmcnt(0)
148 ; GFX11-NEXT: ; return to shader part epilog
149 ;
150 ; GFX12-LABEL: buffer_load_immoffs_large:
151 ; GFX12: ; %bb.0: ; %main_body
152 ; GFX12-NEXT: s_movk_i32 s4, 0x1ffc
153 ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], s4 offset:4
154 ; GFX12-NEXT: s_wait_loadcnt 0x0
155 ; GFX12-NEXT: ; return to shader part epilog
156 main_body:
157 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 4, i32 8188, i32 0)
158 ret <4 x float> %data
159 }
161 define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) {
162 ; PREGFX10-LABEL: buffer_load_ofs:
163 ; PREGFX10: ; %bb.0: ; %main_body
164 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen
165 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
166 ; PREGFX10-NEXT: ; return to shader part epilog
167 ;
168 ; GFX10-LABEL: buffer_load_ofs:
169 ; GFX10: ; %bb.0: ; %main_body
170 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen
171 ; GFX10-NEXT: s_waitcnt vmcnt(0)
172 ; GFX10-NEXT: ; return to shader part epilog
173 ;
174 ; GFX11-LABEL: buffer_load_ofs:
175 ; GFX11: ; %bb.0: ; %main_body
176 ; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen
177 ; GFX11-NEXT: s_waitcnt vmcnt(0)
178 ; GFX11-NEXT: ; return to shader part epilog
179 ;
180 ; GFX12-LABEL: buffer_load_ofs:
181 ; GFX12: ; %bb.0: ; %main_body
182 ; GFX12-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], null offen
183 ; GFX12-NEXT: s_wait_loadcnt 0x0
184 ; GFX12-NEXT: ; return to shader part epilog
185 main_body:
186 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i32 0)
187 ret <4 x float> %data
188 }
190 define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) {
191 ; PREGFX10-LABEL: buffer_load_ofs_imm:
192 ; PREGFX10: ; %bb.0: ; %main_body
193 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:60
194 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
195 ; PREGFX10-NEXT: ; return to shader part epilog
196 ;
197 ; GFX10-LABEL: buffer_load_ofs_imm:
198 ; GFX10: ; %bb.0: ; %main_body
199 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:60
200 ; GFX10-NEXT: s_waitcnt vmcnt(0)
201 ; GFX10-NEXT: ; return to shader part epilog
202 ;
203 ; GFX11-LABEL: buffer_load_ofs_imm:
204 ; GFX11: ; %bb.0: ; %main_body
205 ; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:60
206 ; GFX11-NEXT: s_waitcnt vmcnt(0)
207 ; GFX11-NEXT: ; return to shader part epilog
208 ;
209 ; GFX12-LABEL: buffer_load_ofs_imm:
210 ; GFX12: ; %bb.0: ; %main_body
211 ; GFX12-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], null offen offset:60
212 ; GFX12-NEXT: s_wait_loadcnt 0x0
213 ; GFX12-NEXT: ; return to shader part epilog
214 main_body:
215 %ofs = add i32 %1, 60
216 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %ofs, i32 0, i32 0)
217 ret <4 x float> %data
218 }
220 define amdgpu_ps <4 x float> @buffer_load_voffset_large_12bit(<4 x i32> inreg) {
221 ; PREGFX10-LABEL: buffer_load_voffset_large_12bit:
222 ; PREGFX10: ; %bb.0: ; %main_body
223 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4092
224 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
225 ; PREGFX10-NEXT: ; return to shader part epilog
226 ;
227 ; GFX10-LABEL: buffer_load_voffset_large_12bit:
228 ; GFX10: ; %bb.0: ; %main_body
229 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4092
230 ; GFX10-NEXT: s_waitcnt vmcnt(0)
231 ; GFX10-NEXT: ; return to shader part epilog
232 ;
233 ; GFX11-LABEL: buffer_load_voffset_large_12bit:
234 ; GFX11: ; %bb.0: ; %main_body
235 ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4092
236 ; GFX11-NEXT: s_waitcnt vmcnt(0)
237 ; GFX11-NEXT: ; return to shader part epilog
238 ;
239 ; GFX12-LABEL: buffer_load_voffset_large_12bit:
240 ; GFX12: ; %bb.0: ; %main_body
241 ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null offset:4092
242 ; GFX12-NEXT: s_wait_loadcnt 0x0
243 ; GFX12-NEXT: ; return to shader part epilog
244 main_body:
245 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 4092, i32 0, i32 0)
246 ret <4 x float> %data
247 }
249 define amdgpu_ps <4 x float> @buffer_load_voffset_large_13bit(<4 x i32> inreg) {
250 ; PREGFX10-LABEL: buffer_load_voffset_large_13bit:
251 ; PREGFX10: ; %bb.0: ; %main_body
252 ; PREGFX10-NEXT: v_mov_b32_e32 v0, 0x1000
253 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4092
254 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
255 ; PREGFX10-NEXT: ; return to shader part epilog
256 ;
257 ; GFX10-LABEL: buffer_load_voffset_large_13bit:
258 ; GFX10: ; %bb.0: ; %main_body
259 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x1000
260 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4092
261 ; GFX10-NEXT: s_waitcnt vmcnt(0)
262 ; GFX10-NEXT: ; return to shader part epilog
263 ;
264 ; GFX11-LABEL: buffer_load_voffset_large_13bit:
265 ; GFX11: ; %bb.0: ; %main_body
266 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x1000
267 ; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4092
268 ; GFX11-NEXT: s_waitcnt vmcnt(0)
269 ; GFX11-NEXT: ; return to shader part epilog
270 ;
271 ; GFX12-LABEL: buffer_load_voffset_large_13bit:
272 ; GFX12: ; %bb.0: ; %main_body
273 ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null offset:8188
274 ; GFX12-NEXT: s_wait_loadcnt 0x0
275 ; GFX12-NEXT: ; return to shader part epilog
276 main_body:
277 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 8188, i32 0, i32 0)
278 ret <4 x float> %data
279 }
281 define amdgpu_ps <4 x float> @buffer_load_voffset_large_16bit(<4 x i32> inreg) {
282 ; PREGFX10-LABEL: buffer_load_voffset_large_16bit:
283 ; PREGFX10: ; %bb.0: ; %main_body
284 ; PREGFX10-NEXT: v_mov_b32_e32 v0, 0xf000
285 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4092
286 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
287 ; PREGFX10-NEXT: ; return to shader part epilog
288 ;
289 ; GFX10-LABEL: buffer_load_voffset_large_16bit:
290 ; GFX10: ; %bb.0: ; %main_body
291 ; GFX10-NEXT: v_mov_b32_e32 v0, 0xf000
292 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4092
293 ; GFX10-NEXT: s_waitcnt vmcnt(0)
294 ; GFX10-NEXT: ; return to shader part epilog
295 ;
296 ; GFX11-LABEL: buffer_load_voffset_large_16bit:
297 ; GFX11: ; %bb.0: ; %main_body
298 ; GFX11-NEXT: v_mov_b32_e32 v0, 0xf000
299 ; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4092
300 ; GFX11-NEXT: s_waitcnt vmcnt(0)
301 ; GFX11-NEXT: ; return to shader part epilog
302 ;
303 ; GFX12-LABEL: buffer_load_voffset_large_16bit:
304 ; GFX12: ; %bb.0: ; %main_body
305 ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null offset:65532
306 ; GFX12-NEXT: s_wait_loadcnt 0x0
307 ; GFX12-NEXT: ; return to shader part epilog
308 main_body:
309 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 65532, i32 0, i32 0)
310 ret <4 x float> %data
311 }
313 define amdgpu_ps <4 x float> @buffer_load_voffset_large_23bit(<4 x i32> inreg) {
314 ; PREGFX10-LABEL: buffer_load_voffset_large_23bit:
315 ; PREGFX10: ; %bb.0: ; %main_body
316 ; PREGFX10-NEXT: v_mov_b32_e32 v0, 0x7ff000
317 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4092
318 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
319 ; PREGFX10-NEXT: ; return to shader part epilog
320 ;
321 ; GFX10-LABEL: buffer_load_voffset_large_23bit:
322 ; GFX10: ; %bb.0: ; %main_body
323 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x7ff000
324 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4092
325 ; GFX10-NEXT: s_waitcnt vmcnt(0)
326 ; GFX10-NEXT: ; return to shader part epilog
327 ;
328 ; GFX11-LABEL: buffer_load_voffset_large_23bit:
329 ; GFX11: ; %bb.0: ; %main_body
330 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x7ff000
331 ; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4092
332 ; GFX11-NEXT: s_waitcnt vmcnt(0)
333 ; GFX11-NEXT: ; return to shader part epilog
334 ;
335 ; GFX12-LABEL: buffer_load_voffset_large_23bit:
336 ; GFX12: ; %bb.0: ; %main_body
337 ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null offset:8388604
338 ; GFX12-NEXT: s_wait_loadcnt 0x0
339 ; GFX12-NEXT: ; return to shader part epilog
340 main_body:
341 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 8388604, i32 0, i32 0)
342 ret <4 x float> %data
343 }
345 define amdgpu_ps <4 x float> @buffer_load_voffset_large_24bit(<4 x i32> inreg) {
346 ; PREGFX10-LABEL: buffer_load_voffset_large_24bit:
347 ; PREGFX10: ; %bb.0: ; %main_body
348 ; PREGFX10-NEXT: v_mov_b32_e32 v0, 0xfff000
349 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4092
350 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
351 ; PREGFX10-NEXT: ; return to shader part epilog
352 ;
353 ; GFX10-LABEL: buffer_load_voffset_large_24bit:
354 ; GFX10: ; %bb.0: ; %main_body
355 ; GFX10-NEXT: v_mov_b32_e32 v0, 0xfff000
356 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4092
357 ; GFX10-NEXT: s_waitcnt vmcnt(0)
358 ; GFX10-NEXT: ; return to shader part epilog
359 ;
360 ; GFX11-LABEL: buffer_load_voffset_large_24bit:
361 ; GFX11: ; %bb.0: ; %main_body
362 ; GFX11-NEXT: v_mov_b32_e32 v0, 0xfff000
363 ; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4092
364 ; GFX11-NEXT: s_waitcnt vmcnt(0)
365 ; GFX11-NEXT: ; return to shader part epilog
366 ;
367 ; GFX12-LABEL: buffer_load_voffset_large_24bit:
368 ; GFX12: ; %bb.0: ; %main_body
369 ; GFX12-NEXT: v_mov_b32_e32 v0, 0x800000
370 ; GFX12-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], null offen offset:8388604
371 ; GFX12-NEXT: s_wait_loadcnt 0x0
372 ; GFX12-NEXT: ; return to shader part epilog
373 main_body:
374 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 16777212, i32 0, i32 0)
375 ret <4 x float> %data
376 }
379 define amdgpu_ps float @buffer_load_x1(<4 x i32> inreg %rsrc, i32 %ofs) {
380 ; PREGFX10-LABEL: buffer_load_x1:
381 ; PREGFX10: ; %bb.0: ; %main_body
382 ; PREGFX10-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
383 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
384 ; PREGFX10-NEXT: ; return to shader part epilog
385 ;
386 ; GFX10-LABEL: buffer_load_x1:
387 ; GFX10: ; %bb.0: ; %main_body
388 ; GFX10-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
389 ; GFX10-NEXT: s_waitcnt vmcnt(0)
390 ; GFX10-NEXT: ; return to shader part epilog
391 ;
392 ; GFX11-LABEL: buffer_load_x1:
393 ; GFX11: ; %bb.0: ; %main_body
394 ; GFX11-NEXT: buffer_load_b32 v0, v0, s[0:3], 0 offen
395 ; GFX11-NEXT: s_waitcnt vmcnt(0)
396 ; GFX11-NEXT: ; return to shader part epilog
397 ;
398 ; GFX12-LABEL: buffer_load_x1:
399 ; GFX12: ; %bb.0: ; %main_body
400 ; GFX12-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen
401 ; GFX12-NEXT: s_wait_loadcnt 0x0
402 ; GFX12-NEXT: ; return to shader part epilog
403 main_body:
404 %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 0, i32 0)
405 ret float %data
406 }
408 define amdgpu_ps <2 x float> @buffer_load_x2(<4 x i32> inreg %rsrc, i32 %ofs) {
409 ; PREGFX10-LABEL: buffer_load_x2:
410 ; PREGFX10: ; %bb.0: ; %main_body
411 ; PREGFX10-NEXT: buffer_load_dwordx2 v[0:1], v0, s[0:3], 0 offen
412 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
413 ; PREGFX10-NEXT: ; return to shader part epilog
414 ;
415 ; GFX10-LABEL: buffer_load_x2:
416 ; GFX10: ; %bb.0: ; %main_body
417 ; GFX10-NEXT: buffer_load_dwordx2 v[0:1], v0, s[0:3], 0 offen
418 ; GFX10-NEXT: s_waitcnt vmcnt(0)
419 ; GFX10-NEXT: ; return to shader part epilog
420 ;
421 ; GFX11-LABEL: buffer_load_x2:
422 ; GFX11: ; %bb.0: ; %main_body
423 ; GFX11-NEXT: buffer_load_b64 v[0:1], v0, s[0:3], 0 offen
424 ; GFX11-NEXT: s_waitcnt vmcnt(0)
425 ; GFX11-NEXT: ; return to shader part epilog
426 ;
427 ; GFX12-LABEL: buffer_load_x2:
428 ; GFX12: ; %bb.0: ; %main_body
429 ; GFX12-NEXT: buffer_load_b64 v[0:1], v0, s[0:3], null offen
430 ; GFX12-NEXT: s_wait_loadcnt 0x0
431 ; GFX12-NEXT: ; return to shader part epilog
432 main_body:
433 %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 0, i32 0)
434 ret <2 x float> %data
435 }
437 define amdgpu_ps <4 x float> @buffer_load_negative_offset(<4 x i32> inreg, i32 %ofs) {
438 ; GFX10-LABEL: buffer_load_negative_offset:
439 ; GFX10: ; %bb.0: ; %main_body
440 ; GFX10-NEXT: v_add_nc_u32_e32 v0, -16, v0
441 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen
442 ; GFX10-NEXT: s_waitcnt vmcnt(0)
443 ; GFX10-NEXT: ; return to shader part epilog
444 ;
445 ; GFX11-LABEL: buffer_load_negative_offset:
446 ; GFX11: ; %bb.0: ; %main_body
447 ; GFX11-NEXT: v_add_nc_u32_e32 v0, -16, v0
448 ; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen
449 ; GFX11-NEXT: s_waitcnt vmcnt(0)
450 ; GFX11-NEXT: ; return to shader part epilog
451 ;
452 ; GFX12-LABEL: buffer_load_negative_offset:
453 ; GFX12: ; %bb.0: ; %main_body
454 ; GFX12-NEXT: v_add_nc_u32_e32 v0, -16, v0
455 ; GFX12-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], null offen
456 ; GFX12-NEXT: s_wait_loadcnt 0x0
457 ; GFX12-NEXT: ; return to shader part epilog
458 main_body:
459 %ofs.1 = add i32 %ofs, -16
460 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %ofs.1, i32 0, i32 0)
461 ret <4 x float> %data
462 }
464 define amdgpu_ps float @buffer_load_mmo(<4 x i32> inreg %rsrc, ptr addrspace(3) %lds) {
465 ; GFX10-LABEL: buffer_load_mmo:
466 ; GFX10: ; %bb.0: ; %entry
467 ; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], 0
468 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
469 ; GFX10-NEXT: ds_write2_b32 v0, v2, v2 offset1:4
470 ; GFX10-NEXT: s_waitcnt vmcnt(0)
471 ; GFX10-NEXT: v_mov_b32_e32 v0, v1
472 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
473 ; GFX10-NEXT: ; return to shader part epilog
474 ;
475 ; GFX11-LABEL: buffer_load_mmo:
476 ; GFX11: ; %bb.0: ; %entry
477 ; GFX11-NEXT: buffer_load_b32 v1, off, s[0:3], 0
478 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
479 ; GFX11-NEXT: ds_store_2addr_b32 v0, v2, v2 offset1:4
480 ; GFX11-NEXT: s_waitcnt vmcnt(0)
481 ; GFX11-NEXT: v_mov_b32_e32 v0, v1
482 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
483 ; GFX11-NEXT: ; return to shader part epilog
484 ;
485 ; GFX12-LABEL: buffer_load_mmo:
486 ; GFX12: ; %bb.0: ; %entry
487 ; GFX12-NEXT: buffer_load_b32 v1, off, s[0:3], null
488 ; GFX12-NEXT: v_mov_b32_e32 v2, 0
489 ; GFX12-NEXT: ds_store_2addr_b32 v0, v2, v2 offset1:4
490 ; GFX12-NEXT: s_wait_loadcnt 0x0
491 ; GFX12-NEXT: v_mov_b32_e32 v0, v1
492 ; GFX12-NEXT: s_wait_dscnt 0x0
493 ; GFX12-NEXT: ; return to shader part epilog
494 entry:
495 store float 0.0, ptr addrspace(3) %lds
496 %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
497 %tmp2 = getelementptr float, ptr addrspace(3) %lds, i32 4
498 store float 0.0, ptr addrspace(3) %tmp2
499 ret float %val
500 }
502 define amdgpu_ps void @buffer_load_x1_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a) {
503 ; PREGFX10-LABEL: buffer_load_x1_offen_merged_and:
504 ; PREGFX10: ; %bb.0: ; %main_body
505 ; PREGFX10-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:4
506 ; PREGFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28
507 ; PREGFX10-NEXT: s_waitcnt vmcnt(1)
508 ; PREGFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm
509 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
510 ; PREGFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm
511 ; PREGFX10-NEXT: s_endpgm
512 ;
513 ; GFX10-LABEL: buffer_load_x1_offen_merged_and:
514 ; GFX10: ; %bb.0: ; %main_body
515 ; GFX10-NEXT: s_clause 0x1
516 ; GFX10-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:4
517 ; GFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28
518 ; GFX10-NEXT: s_waitcnt vmcnt(1)
519 ; GFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm
520 ; GFX10-NEXT: s_waitcnt vmcnt(0)
521 ; GFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm
522 ; GFX10-NEXT: s_endpgm
523 ;
524 ; GFX11-LABEL: buffer_load_x1_offen_merged_and:
525 ; GFX11: ; %bb.0: ; %main_body
526 ; GFX11-NEXT: s_clause 0x1
527 ; GFX11-NEXT: buffer_load_b128 v[1:4], v0, s[0:3], 0 offen offset:4
528 ; GFX11-NEXT: buffer_load_b64 v[5:6], v0, s[0:3], 0 offen offset:28
529 ; GFX11-NEXT: s_waitcnt vmcnt(1)
530 ; GFX11-NEXT: exp mrt0 v1, v2, v3, v4 done
531 ; GFX11-NEXT: s_waitcnt vmcnt(0)
532 ; GFX11-NEXT: exp mrt0 v5, v6, v0, v0 done
533 ; GFX11-NEXT: s_endpgm
534 ;
535 ; GFX12-LABEL: buffer_load_x1_offen_merged_and:
536 ; GFX12: ; %bb.0: ; %main_body
537 ; GFX12-NEXT: s_clause 0x1
538 ; GFX12-NEXT: buffer_load_b128 v[1:4], v0, s[0:3], null offen offset:4
539 ; GFX12-NEXT: buffer_load_b64 v[5:6], v0, s[0:3], null offen offset:28
540 ; GFX12-NEXT: s_wait_loadcnt 0x1
541 ; GFX12-NEXT: export mrt0 v1, v2, v3, v4 done
542 ; GFX12-NEXT: s_wait_loadcnt 0x0
543 ; GFX12-NEXT: export mrt0 v5, v6, v0, v0 done
544 ; GFX12-NEXT: s_endpgm
545 main_body:
546 %a1 = add i32 %a, 4
547 %a2 = add i32 %a, 8
548 %a3 = add i32 %a, 12
549 %a4 = add i32 %a, 16
550 %a5 = add i32 %a, 28
551 %a6 = add i32 %a, 32
552 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
553 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
554 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a3, i32 0, i32 0)
555 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a4, i32 0, i32 0)
556 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 0)
557 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 0)
558 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
559 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
560 ret void
561 }
563 define amdgpu_ps void @buffer_load_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp) {
564 ; PREGFX10-LABEL: buffer_load_x1_offen_merged_or:
565 ; PREGFX10: ; %bb.0: ; %main_body
566 ; PREGFX10-NEXT: v_lshlrev_b32_e32 v4, 6, v0
567 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v4, s[0:3], 0 offen offset:4
568 ; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], v4, s[0:3], 0 offen offset:28
569 ; PREGFX10-NEXT: s_waitcnt vmcnt(1)
570 ; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
571 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
572 ; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
573 ; PREGFX10-NEXT: s_endpgm
574 ;
575 ; GFX10-LABEL: buffer_load_x1_offen_merged_or:
576 ; GFX10: ; %bb.0: ; %main_body
577 ; GFX10-NEXT: v_lshlrev_b32_e32 v6, 6, v0
578 ; GFX10-NEXT: s_clause 0x1
579 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v6, s[0:3], 0 offen offset:4
580 ; GFX10-NEXT: buffer_load_dwordx2 v[4:5], v6, s[0:3], 0 offen offset:28
581 ; GFX10-NEXT: s_waitcnt vmcnt(1)
582 ; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
583 ; GFX10-NEXT: s_waitcnt vmcnt(0)
584 ; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
585 ; GFX10-NEXT: s_endpgm
586 ;
587 ; GFX11-LABEL: buffer_load_x1_offen_merged_or:
588 ; GFX11: ; %bb.0: ; %main_body
589 ; GFX11-NEXT: v_lshlrev_b32_e32 v4, 6, v0
590 ; GFX11-NEXT: s_clause 0x1
591 ; GFX11-NEXT: buffer_load_b128 v[0:3], v4, s[0:3], 0 offen offset:4
592 ; GFX11-NEXT: buffer_load_b64 v[4:5], v4, s[0:3], 0 offen offset:28
593 ; GFX11-NEXT: s_waitcnt vmcnt(1)
594 ; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done
595 ; GFX11-NEXT: s_waitcnt vmcnt(0)
596 ; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done
597 ; GFX11-NEXT: s_endpgm
598 ;
599 ; GFX12-SDAG-LABEL: buffer_load_x1_offen_merged_or:
600 ; GFX12-SDAG: ; %bb.0: ; %main_body
601 ; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v4, 6, v0
602 ; GFX12-SDAG-NEXT: s_clause 0x1
603 ; GFX12-SDAG-NEXT: buffer_load_b128 v[0:3], v4, s[0:3], null offen offset:4
604 ; GFX12-SDAG-NEXT: buffer_load_b64 v[4:5], v4, s[0:3], null offen offset:28
605 ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x1
606 ; GFX12-SDAG-NEXT: export mrt0 v0, v1, v2, v3 done
607 ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
608 ; GFX12-SDAG-NEXT: export mrt0 v4, v5, v0, v0 done
609 ; GFX12-SDAG-NEXT: s_endpgm
610 ;
611 ; GFX12-GISEL-LABEL: buffer_load_x1_offen_merged_or:
612 ; GFX12-GISEL: ; %bb.0: ; %main_body
613 ; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v0, 6, v0
614 ; GFX12-GISEL-NEXT: v_or_b32_e32 v1, 4, v0
615 ; GFX12-GISEL-NEXT: v_or_b32_e32 v2, 8, v0
616 ; GFX12-GISEL-NEXT: v_or_b32_e32 v3, 12, v0
617 ; GFX12-GISEL-NEXT: v_or_b32_e32 v4, 16, v0
618 ; GFX12-GISEL-NEXT: v_or_b32_e32 v5, 28, v0
619 ; GFX12-GISEL-NEXT: v_or_b32_e32 v0, 32, v0
620 ; GFX12-GISEL-NEXT: s_clause 0x5
621 ; GFX12-GISEL-NEXT: buffer_load_b32 v1, v1, s[0:3], null offen
622 ; GFX12-GISEL-NEXT: buffer_load_b32 v2, v2, s[0:3], null offen
623 ; GFX12-GISEL-NEXT: buffer_load_b32 v3, v3, s[0:3], null offen
624 ; GFX12-GISEL-NEXT: buffer_load_b32 v4, v4, s[0:3], null offen
625 ; GFX12-GISEL-NEXT: buffer_load_b32 v5, v5, s[0:3], null offen
626 ; GFX12-GISEL-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen
627 ; GFX12-GISEL-NEXT: s_wait_loadcnt 0x2
628 ; GFX12-GISEL-NEXT: export mrt0 v1, v2, v3, v4 done
629 ; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
630 ; GFX12-GISEL-NEXT: export mrt0 v5, v0, v0, v0 done
631 ; GFX12-GISEL-NEXT: s_endpgm
632 main_body:
633 %a = shl i32 %inp, 6
634 %a1 = or i32 %a, 4
635 %a2 = or i32 %a, 8
636 %a3 = or i32 %a, 12
637 %a4 = or i32 %a, 16
638 %a5 = or i32 %a, 28
639 %a6 = or i32 %a, 32
640 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
641 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
642 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a3, i32 0, i32 0)
643 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a4, i32 0, i32 0)
644 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 0)
645 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 0)
646 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
647 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
648 ret void
649 }
651 define amdgpu_ps void @buffer_load_x1_offen_merged_glc_slc(<4 x i32> inreg %rsrc, i32 %a) {
652 ; PREGFX10-LABEL: buffer_load_x1_offen_merged_glc_slc:
653 ; PREGFX10: ; %bb.0: ; %main_body
654 ; PREGFX10-NEXT: buffer_load_dwordx2 v[1:2], v0, s[0:3], 0 offen offset:4
655 ; PREGFX10-NEXT: buffer_load_dwordx2 v[3:4], v0, s[0:3], 0 offen offset:12 glc
656 ; PREGFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc
657 ; PREGFX10-NEXT: s_waitcnt vmcnt(1)
658 ; PREGFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm
659 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
660 ; PREGFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm
661 ; PREGFX10-NEXT: s_endpgm
662 ;
663 ; GFX10-LABEL: buffer_load_x1_offen_merged_glc_slc:
664 ; GFX10: ; %bb.0: ; %main_body
665 ; GFX10-NEXT: s_clause 0x2
666 ; GFX10-NEXT: buffer_load_dwordx2 v[1:2], v0, s[0:3], 0 offen offset:4
667 ; GFX10-NEXT: buffer_load_dwordx2 v[3:4], v0, s[0:3], 0 offen offset:12 glc
668 ; GFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc
669 ; GFX10-NEXT: s_waitcnt vmcnt(1)
670 ; GFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm
671 ; GFX10-NEXT: s_waitcnt vmcnt(0)
672 ; GFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm
673 ; GFX10-NEXT: s_endpgm
674 ;
675 ; GFX11-LABEL: buffer_load_x1_offen_merged_glc_slc:
676 ; GFX11: ; %bb.0: ; %main_body
677 ; GFX11-NEXT: s_clause 0x2
678 ; GFX11-NEXT: buffer_load_b64 v[1:2], v0, s[0:3], 0 offen offset:4
679 ; GFX11-NEXT: buffer_load_b64 v[3:4], v0, s[0:3], 0 offen offset:12 glc
680 ; GFX11-NEXT: buffer_load_b64 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc
681 ; GFX11-NEXT: s_waitcnt vmcnt(1)
682 ; GFX11-NEXT: exp mrt0 v1, v2, v3, v4 done
683 ; GFX11-NEXT: s_waitcnt vmcnt(0)
684 ; GFX11-NEXT: exp mrt0 v5, v6, v0, v0 done
685 ; GFX11-NEXT: s_endpgm
686 ;
687 ; GFX12-LABEL: buffer_load_x1_offen_merged_glc_slc:
688 ; GFX12: ; %bb.0: ; %main_body
689 ; GFX12-NEXT: s_clause 0x2
690 ; GFX12-NEXT: buffer_load_b64 v[1:2], v0, s[0:3], null offen offset:4
691 ; GFX12-NEXT: buffer_load_b64 v[3:4], v0, s[0:3], null offen offset:12 th:TH_LOAD_NT
692 ; GFX12-NEXT: buffer_load_b64 v[5:6], v0, s[0:3], null offen offset:28 th:TH_LOAD_LU
693 ; GFX12-NEXT: s_wait_loadcnt 0x1
694 ; GFX12-NEXT: export mrt0 v1, v2, v3, v4 done
695 ; GFX12-NEXT: s_wait_loadcnt 0x0
696 ; GFX12-NEXT: export mrt0 v5, v6, v0, v0 done
697 ; GFX12-NEXT: s_endpgm
698 main_body:
699 %a1 = add i32 %a, 4
700 %a2 = add i32 %a, 8
701 %a3 = add i32 %a, 12
702 %a4 = add i32 %a, 16
703 %a5 = add i32 %a, 28
704 %a6 = add i32 %a, 32
705 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
706 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
707 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a3, i32 0, i32 1)
708 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a4, i32 0, i32 1)
709 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 3)
710 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 3)
711 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
712 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
713 ret void
714 }
716 define amdgpu_ps void @buffer_load_x2_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a) {
717 ; PREGFX10-LABEL: buffer_load_x2_offen_merged_and:
718 ; PREGFX10: ; %bb.0: ; %main_body
719 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4
720 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
721 ; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
722 ; PREGFX10-NEXT: s_endpgm
723 ;
724 ; GFX10-LABEL: buffer_load_x2_offen_merged_and:
725 ; GFX10: ; %bb.0: ; %main_body
726 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4
727 ; GFX10-NEXT: s_waitcnt vmcnt(0)
728 ; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
729 ; GFX10-NEXT: s_endpgm
730 ;
731 ; GFX11-LABEL: buffer_load_x2_offen_merged_and:
732 ; GFX11: ; %bb.0: ; %main_body
733 ; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4
734 ; GFX11-NEXT: s_waitcnt vmcnt(0)
735 ; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done
736 ; GFX11-NEXT: s_endpgm
737 ;
738 ; GFX12-LABEL: buffer_load_x2_offen_merged_and:
739 ; GFX12: ; %bb.0: ; %main_body
740 ; GFX12-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], null offen offset:4
741 ; GFX12-NEXT: s_wait_loadcnt 0x0
742 ; GFX12-NEXT: export mrt0 v0, v1, v2, v3 done
743 ; GFX12-NEXT: s_endpgm
744 main_body:
745 %a1 = add i32 %a, 4
746 %a2 = add i32 %a, 12
747 %vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
748 %vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
749 %r1 = extractelement <2 x float> %vr1, i32 0
750 %r2 = extractelement <2 x float> %vr1, i32 1
751 %r3 = extractelement <2 x float> %vr2, i32 0
752 %r4 = extractelement <2 x float> %vr2, i32 1
753 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
754 ret void
755 }
757 define amdgpu_ps void @buffer_load_x2_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp) {
758 ; PREGFX10-LABEL: buffer_load_x2_offen_merged_or:
759 ; PREGFX10: ; %bb.0: ; %main_body
760 ; PREGFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0
761 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4
762 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
763 ; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
764 ; PREGFX10-NEXT: s_endpgm
765 ;
766 ; GFX10-LABEL: buffer_load_x2_offen_merged_or:
767 ; GFX10: ; %bb.0: ; %main_body
768 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0
769 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4
770 ; GFX10-NEXT: s_waitcnt vmcnt(0)
771 ; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
772 ; GFX10-NEXT: s_endpgm
773 ;
774 ; GFX11-LABEL: buffer_load_x2_offen_merged_or:
775 ; GFX11: ; %bb.0: ; %main_body
776 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0
777 ; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4
778 ; GFX11-NEXT: s_waitcnt vmcnt(0)
779 ; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done
780 ; GFX11-NEXT: s_endpgm
781 ;
782 ; GFX12-LABEL: buffer_load_x2_offen_merged_or:
783 ; GFX12: ; %bb.0: ; %main_body
784 ; GFX12-NEXT: v_lshlrev_b32_e32 v0, 4, v0
785 ; GFX12-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], null offen offset:4
786 ; GFX12-NEXT: s_wait_loadcnt 0x0
787 ; GFX12-NEXT: export mrt0 v0, v1, v2, v3 done
788 ; GFX12-NEXT: s_endpgm
789 main_body:
790 %a = shl i32 %inp, 4
791 %a1 = add i32 %a, 4
792 %a2 = add i32 %a, 12
793 %vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
794 %vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
795 %r1 = extractelement <2 x float> %vr1, i32 0
796 %r2 = extractelement <2 x float> %vr1, i32 1
797 %r3 = extractelement <2 x float> %vr2, i32 0
798 %r4 = extractelement <2 x float> %vr2, i32 1
799 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
800 ret void
801 }
803 define amdgpu_ps void @buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) {
804 ; PREGFX10-LABEL: buffer_load_x1_offset_merged:
805 ; PREGFX10: ; %bb.0: ; %main_body
806 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
807 ; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28
808 ; PREGFX10-NEXT: s_waitcnt vmcnt(1)
809 ; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
810 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
811 ; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
812 ; PREGFX10-NEXT: s_endpgm
813 ;
814 ; GFX10-LABEL: buffer_load_x1_offset_merged:
815 ; GFX10: ; %bb.0: ; %main_body
816 ; GFX10-NEXT: s_clause 0x1
817 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
818 ; GFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28
819 ; GFX10-NEXT: s_waitcnt vmcnt(1)
820 ; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
821 ; GFX10-NEXT: s_waitcnt vmcnt(0)
822 ; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
823 ; GFX10-NEXT: s_endpgm
824 ;
825 ; GFX11-LABEL: buffer_load_x1_offset_merged:
826 ; GFX11: ; %bb.0: ; %main_body
827 ; GFX11-NEXT: s_clause 0x1
828 ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4
829 ; GFX11-NEXT: buffer_load_b64 v[4:5], off, s[0:3], 0 offset:28
830 ; GFX11-NEXT: s_waitcnt vmcnt(1)
831 ; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done
832 ; GFX11-NEXT: s_waitcnt vmcnt(0)
833 ; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done
834 ; GFX11-NEXT: s_endpgm
835 ;
836 ; GFX12-LABEL: buffer_load_x1_offset_merged:
837 ; GFX12: ; %bb.0: ; %main_body
838 ; GFX12-NEXT: s_clause 0x1
839 ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null offset:4
840 ; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[0:3], null offset:28
841 ; GFX12-NEXT: s_wait_loadcnt 0x1
842 ; GFX12-NEXT: export mrt0 v0, v1, v2, v3 done
843 ; GFX12-NEXT: s_wait_loadcnt 0x0
844 ; GFX12-NEXT: export mrt0 v4, v5, v0, v0 done
845 ; GFX12-NEXT: s_endpgm
846 main_body:
847 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0)
848 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 0)
849 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 12, i32 0, i32 0)
850 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 16, i32 0, i32 0)
851 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 0)
852 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 0)
853 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
854 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
855 ret void
856 }
858 define amdgpu_ps void @buffer_load_x2_offset_merged(<4 x i32> inreg %rsrc) {
859 ; PREGFX10-LABEL: buffer_load_x2_offset_merged:
860 ; PREGFX10: ; %bb.0: ; %main_body
861 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
862 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
863 ; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
864 ; PREGFX10-NEXT: s_endpgm
865 ;
866 ; GFX10-LABEL: buffer_load_x2_offset_merged:
867 ; GFX10: ; %bb.0: ; %main_body
868 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
869 ; GFX10-NEXT: s_waitcnt vmcnt(0)
870 ; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
871 ; GFX10-NEXT: s_endpgm
872 ;
873 ; GFX11-LABEL: buffer_load_x2_offset_merged:
874 ; GFX11: ; %bb.0: ; %main_body
875 ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4
876 ; GFX11-NEXT: s_waitcnt vmcnt(0)
877 ; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done
878 ; GFX11-NEXT: s_endpgm
879 ;
880 ; GFX12-LABEL: buffer_load_x2_offset_merged:
881 ; GFX12: ; %bb.0: ; %main_body
882 ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null offset:4
883 ; GFX12-NEXT: s_wait_loadcnt 0x0
884 ; GFX12-NEXT: export mrt0 v0, v1, v2, v3 done
885 ; GFX12-NEXT: s_endpgm
886 main_body:
887 %vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0)
888 %vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 12, i32 0, i32 0)
889 %r1 = extractelement <2 x float> %vr1, i32 0
890 %r2 = extractelement <2 x float> %vr1, i32 1
891 %r3 = extractelement <2 x float> %vr2, i32 0
892 %r4 = extractelement <2 x float> %vr2, i32 1
893 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
894 ret void
895 }
897 define amdgpu_ps {<4 x float>, <2 x float>, float} @buffer_load_int(<4 x i32> inreg) {
898 ; PREGFX10-LABEL: buffer_load_int:
899 ; PREGFX10: ; %bb.0: ; %main_body
900 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
901 ; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 glc
902 ; PREGFX10-NEXT: buffer_load_dword v6, off, s[0:3], 0 slc
903 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
904 ; PREGFX10-NEXT: ; return to shader part epilog
905 ;
906 ; GFX10-LABEL: buffer_load_int:
907 ; GFX10: ; %bb.0: ; %main_body
908 ; GFX10-NEXT: s_clause 0x2
909 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
910 ; GFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 glc
911 ; GFX10-NEXT: buffer_load_dword v6, off, s[0:3], 0 slc
912 ; GFX10-NEXT: s_waitcnt vmcnt(0)
913 ; GFX10-NEXT: ; return to shader part epilog
914 ;
915 ; GFX11-LABEL: buffer_load_int:
916 ; GFX11: ; %bb.0: ; %main_body
917 ; GFX11-NEXT: s_clause 0x2
918 ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0
919 ; GFX11-NEXT: buffer_load_b64 v[4:5], off, s[0:3], 0 glc
920 ; GFX11-NEXT: buffer_load_b32 v6, off, s[0:3], 0 slc
921 ; GFX11-NEXT: s_waitcnt vmcnt(0)
922 ; GFX11-NEXT: ; return to shader part epilog
923 ;
924 ; GFX12-LABEL: buffer_load_int:
925 ; GFX12: ; %bb.0: ; %main_body
926 ; GFX12-NEXT: s_clause 0x2
927 ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null
928 ; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[0:3], null th:TH_LOAD_NT
929 ; GFX12-NEXT: buffer_load_b32 v6, off, s[0:3], null th:TH_LOAD_HT
930 ; GFX12-NEXT: s_wait_loadcnt 0x0
931 ; GFX12-NEXT: ; return to shader part epilog
932 main_body:
933 %data = call <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0)
934 %data_glc = call <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32> %0, i32 0, i32 0, i32 1)
935 %data_slc = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> %0, i32 0, i32 0, i32 2)
936 %fdata = bitcast <4 x i32> %data to <4 x float>
937 %fdata_glc = bitcast <2 x i32> %data_glc to <2 x float>
938 %fdata_slc = bitcast i32 %data_slc to float
939 %r0 = insertvalue {<4 x float>, <2 x float>, float} undef, <4 x float> %fdata, 0
940 %r1 = insertvalue {<4 x float>, <2 x float>, float} %r0, <2 x float> %fdata_glc, 1
941 %r2 = insertvalue {<4 x float>, <2 x float>, float} %r1, float %fdata_slc, 2
942 ret {<4 x float>, <2 x float>, float} %r2
943 }
945 define amdgpu_ps float @raw_buffer_load_ubyte(<4 x i32> inreg %rsrc) {
946 ; PREGFX10-LABEL: raw_buffer_load_ubyte:
947 ; PREGFX10: ; %bb.0: ; %main_body
948 ; PREGFX10-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
949 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
950 ; PREGFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
951 ; PREGFX10-NEXT: ; return to shader part epilog
952 ;
953 ; GFX10-LABEL: raw_buffer_load_ubyte:
954 ; GFX10: ; %bb.0: ; %main_body
955 ; GFX10-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
956 ; GFX10-NEXT: s_waitcnt vmcnt(0)
957 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
958 ; GFX10-NEXT: ; return to shader part epilog
959 ;
960 ; GFX11-LABEL: raw_buffer_load_ubyte:
961 ; GFX11: ; %bb.0: ; %main_body
962 ; GFX11-NEXT: buffer_load_u8 v0, off, s[0:3], 0
963 ; GFX11-NEXT: s_waitcnt vmcnt(0)
964 ; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
965 ; GFX11-NEXT: ; return to shader part epilog
966 ;
967 ; GFX12-LABEL: raw_buffer_load_ubyte:
968 ; GFX12: ; %bb.0: ; %main_body
969 ; GFX12-NEXT: buffer_load_u8 v0, off, s[0:3], null
970 ; GFX12-NEXT: s_wait_loadcnt 0x0
971 ; GFX12-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
972 ; GFX12-NEXT: ; return to shader part epilog
973 main_body:
974 %tmp = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
975 %tmp2 = zext i8 %tmp to i32
976 %val = uitofp i32 %tmp2 to float
977 ret float %val
978 }
980 define amdgpu_ps float @raw_buffer_load_i16(<4 x i32> inreg %rsrc) {
981 ; PREGFX10-LABEL: raw_buffer_load_i16:
982 ; PREGFX10: ; %bb.0: ; %main_body
983 ; PREGFX10-NEXT: buffer_load_ushort v0, off, s[0:3], 0
984 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
985 ; PREGFX10-NEXT: v_cvt_f32_u32_e32 v0, v0
986 ; PREGFX10-NEXT: ; return to shader part epilog
987 ;
988 ; GFX10-LABEL: raw_buffer_load_i16:
989 ; GFX10: ; %bb.0: ; %main_body
990 ; GFX10-NEXT: buffer_load_ushort v0, off, s[0:3], 0
991 ; GFX10-NEXT: s_waitcnt vmcnt(0)
992 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, v0
993 ; GFX10-NEXT: ; return to shader part epilog
994 ;
995 ; GFX11-LABEL: raw_buffer_load_i16:
996 ; GFX11: ; %bb.0: ; %main_body
997 ; GFX11-NEXT: buffer_load_u16 v0, off, s[0:3], 0
998 ; GFX11-NEXT: s_waitcnt vmcnt(0)
999 ; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
1000 ; GFX11-NEXT: ; return to shader part epilog
1001 ;
1002 ; GFX12-LABEL: raw_buffer_load_i16:
1003 ; GFX12: ; %bb.0: ; %main_body
1004 ; GFX12-NEXT: buffer_load_u16 v0, off, s[0:3], null
1005 ; GFX12-NEXT: s_wait_loadcnt 0x0
1006 ; GFX12-NEXT: v_cvt_f32_u32_e32 v0, v0
1007 ; GFX12-NEXT: ; return to shader part epilog
1008 main_body:
1009 %tmp = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
1010 %tmp2 = zext i16 %tmp to i32
1011 %val = uitofp i32 %tmp2 to float
1012 ret float %val
1013 }
1015 define amdgpu_ps float @raw_buffer_load_sbyte(<4 x i32> inreg %rsrc) {
1016 ; PREGFX10-LABEL: raw_buffer_load_sbyte:
1017 ; PREGFX10: ; %bb.0: ; %main_body
1018 ; PREGFX10-NEXT: buffer_load_sbyte v0, off, s[0:3], 0
1019 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
1020 ; PREGFX10-NEXT: v_cvt_f32_i32_e32 v0, v0
1021 ; PREGFX10-NEXT: ; return to shader part epilog
1022 ;
1023 ; GFX10-LABEL: raw_buffer_load_sbyte:
1024 ; GFX10: ; %bb.0: ; %main_body
1025 ; GFX10-NEXT: buffer_load_sbyte v0, off, s[0:3], 0
1026 ; GFX10-NEXT: s_waitcnt vmcnt(0)
1027 ; GFX10-NEXT: v_cvt_f32_i32_e32 v0, v0
1028 ; GFX10-NEXT: ; return to shader part epilog
1029 ;
1030 ; GFX11-LABEL: raw_buffer_load_sbyte:
1031 ; GFX11: ; %bb.0: ; %main_body
1032 ; GFX11-NEXT: buffer_load_i8 v0, off, s[0:3], 0
1033 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1034 ; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
1035 ; GFX11-NEXT: ; return to shader part epilog
1036 ;
1037 ; GFX12-LABEL: raw_buffer_load_sbyte:
1038 ; GFX12: ; %bb.0: ; %main_body
1039 ; GFX12-NEXT: buffer_load_i8 v0, off, s[0:3], null
1040 ; GFX12-NEXT: s_wait_loadcnt 0x0
1041 ; GFX12-NEXT: v_cvt_f32_i32_e32 v0, v0
1042 ; GFX12-NEXT: ; return to shader part epilog
1043 main_body:
1044 %tmp = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
1045 %tmp2 = sext i8 %tmp to i32
1046 %val = sitofp i32 %tmp2 to float
1047 ret float %val
1048 }
1050 define amdgpu_ps float @raw_buffer_load_sshort(<4 x i32> inreg %rsrc) {
1051 ; PREGFX10-LABEL: raw_buffer_load_sshort:
1052 ; PREGFX10: ; %bb.0: ; %main_body
1053 ; PREGFX10-NEXT: buffer_load_sshort v0, off, s[0:3], 0
1054 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
1055 ; PREGFX10-NEXT: v_cvt_f32_i32_e32 v0, v0
1056 ; PREGFX10-NEXT: ; return to shader part epilog
1057 ;
1058 ; GFX10-LABEL: raw_buffer_load_sshort:
1059 ; GFX10: ; %bb.0: ; %main_body
1060 ; GFX10-NEXT: buffer_load_sshort v0, off, s[0:3], 0
1061 ; GFX10-NEXT: s_waitcnt vmcnt(0)
1062 ; GFX10-NEXT: v_cvt_f32_i32_e32 v0, v0
1063 ; GFX10-NEXT: ; return to shader part epilog
1064 ;
1065 ; GFX11-LABEL: raw_buffer_load_sshort:
1066 ; GFX11: ; %bb.0: ; %main_body
1067 ; GFX11-NEXT: buffer_load_i16 v0, off, s[0:3], 0
1068 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1069 ; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
1070 ; GFX11-NEXT: ; return to shader part epilog
1071 ;
1072 ; GFX12-LABEL: raw_buffer_load_sshort:
1073 ; GFX12: ; %bb.0: ; %main_body
1074 ; GFX12-NEXT: buffer_load_i16 v0, off, s[0:3], null
1075 ; GFX12-NEXT: s_wait_loadcnt 0x0
1076 ; GFX12-NEXT: v_cvt_f32_i32_e32 v0, v0
1077 ; GFX12-NEXT: ; return to shader part epilog
1078 main_body:
1079 %tmp = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
1080 %tmp2 = sext i16 %tmp to i32
1081 %val = sitofp i32 %tmp2 to float
1082 ret float %val
1083 }
1085 define amdgpu_ps void @raw_buffer_load_f16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr) {
1086 ; PREGFX10-LABEL: raw_buffer_load_f16:
1087 ; PREGFX10: ; %bb.0: ; %main_body
1088 ; PREGFX10-NEXT: buffer_load_ushort v1, off, s[0:3], 0
1089 ; PREGFX10-NEXT: s_mov_b32 m0, -1
1090 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
1091 ; PREGFX10-NEXT: ds_write_b16 v0, v1
1092 ; PREGFX10-NEXT: s_endpgm
1093 ;
1094 ; GFX10-LABEL: raw_buffer_load_f16:
1095 ; GFX10: ; %bb.0: ; %main_body
1096 ; GFX10-NEXT: buffer_load_ushort v1, off, s[0:3], 0
1097 ; GFX10-NEXT: s_waitcnt vmcnt(0)
1098 ; GFX10-NEXT: ds_write_b16 v0, v1
1099 ; GFX10-NEXT: s_endpgm
1100 ;
1101 ; GFX11-LABEL: raw_buffer_load_f16:
1102 ; GFX11: ; %bb.0: ; %main_body
1103 ; GFX11-NEXT: buffer_load_u16 v1, off, s[0:3], 0
1104 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1105 ; GFX11-NEXT: ds_store_b16 v0, v1
1106 ; GFX11-NEXT: s_endpgm
1107 ;
1108 ; GFX12-LABEL: raw_buffer_load_f16:
1109 ; GFX12: ; %bb.0: ; %main_body
1110 ; GFX12-NEXT: buffer_load_u16 v1, off, s[0:3], null
1111 ; GFX12-NEXT: s_wait_loadcnt 0x0
1112 ; GFX12-NEXT: ds_store_b16 v0, v1
1113 ; GFX12-NEXT: s_endpgm
1114 main_body:
1115 %val = call half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
1116 store half %val, ptr addrspace(3) %ptr
1117 ret void
1118 }
1120 define amdgpu_ps void @raw_buffer_load_v2f16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr) {
1121 ; PREGFX10-LABEL: raw_buffer_load_v2f16:
1122 ; PREGFX10: ; %bb.0: ; %main_body
1123 ; PREGFX10-NEXT: buffer_load_dword v1, off, s[0:3], 0
1124 ; PREGFX10-NEXT: s_mov_b32 m0, -1
1125 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
1126 ; PREGFX10-NEXT: ds_write_b32 v0, v1
1127 ; PREGFX10-NEXT: s_endpgm
1128 ;
1129 ; GFX10-LABEL: raw_buffer_load_v2f16:
1130 ; GFX10: ; %bb.0: ; %main_body
1131 ; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], 0
1132 ; GFX10-NEXT: s_waitcnt vmcnt(0)
1133 ; GFX10-NEXT: ds_write_b32 v0, v1
1134 ; GFX10-NEXT: s_endpgm
1135 ;
1136 ; GFX11-LABEL: raw_buffer_load_v2f16:
1137 ; GFX11: ; %bb.0: ; %main_body
1138 ; GFX11-NEXT: buffer_load_b32 v1, off, s[0:3], 0
1139 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1140 ; GFX11-NEXT: ds_store_b32 v0, v1
1141 ; GFX11-NEXT: s_endpgm
1142 ;
1143 ; GFX12-LABEL: raw_buffer_load_v2f16:
1144 ; GFX12: ; %bb.0: ; %main_body
1145 ; GFX12-NEXT: buffer_load_b32 v1, off, s[0:3], null
1146 ; GFX12-NEXT: s_wait_loadcnt 0x0
1147 ; GFX12-NEXT: ds_store_b32 v0, v1
1148 ; GFX12-NEXT: s_endpgm
1149 main_body:
1150 %val = call <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
1151 store <2 x half> %val, ptr addrspace(3) %ptr
1152 ret void
1153 }
1155 define amdgpu_ps void @raw_buffer_load_v4f16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr) {
1156 ; PREGFX10-LABEL: raw_buffer_load_v4f16:
1157 ; PREGFX10: ; %bb.0: ; %main_body
1158 ; PREGFX10-NEXT: buffer_load_dwordx2 v[1:2], off, s[0:3], 0
1159 ; PREGFX10-NEXT: s_mov_b32 m0, -1
1160 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
1161 ; PREGFX10-NEXT: ds_write_b64 v0, v[1:2]
1162 ; PREGFX10-NEXT: s_endpgm
1163 ;
1164 ; GFX10-LABEL: raw_buffer_load_v4f16:
1165 ; GFX10: ; %bb.0: ; %main_body
1166 ; GFX10-NEXT: buffer_load_dwordx2 v[1:2], off, s[0:3], 0
1167 ; GFX10-NEXT: s_waitcnt vmcnt(0)
1168 ; GFX10-NEXT: ds_write_b64 v0, v[1:2]
1169 ; GFX10-NEXT: s_endpgm
1170 ;
1171 ; GFX11-LABEL: raw_buffer_load_v4f16:
1172 ; GFX11: ; %bb.0: ; %main_body
1173 ; GFX11-NEXT: buffer_load_b64 v[1:2], off, s[0:3], 0
1174 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1175 ; GFX11-NEXT: ds_store_b64 v0, v[1:2]
1176 ; GFX11-NEXT: s_endpgm
1177 ;
1178 ; GFX12-LABEL: raw_buffer_load_v4f16:
1179 ; GFX12: ; %bb.0: ; %main_body
1180 ; GFX12-NEXT: buffer_load_b64 v[1:2], off, s[0:3], null
1181 ; GFX12-NEXT: s_wait_loadcnt 0x0
1182 ; GFX12-NEXT: ds_store_b64 v0, v[1:2]
1183 ; GFX12-NEXT: s_endpgm
1184 main_body:
1185 %val = call <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
1186 store <4 x half> %val, ptr addrspace(3) %ptr
1187 ret void
1188 }
1190 define amdgpu_ps void @raw_buffer_load_v2i16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr) {
1191 ; PREGFX10-LABEL: raw_buffer_load_v2i16:
1192 ; PREGFX10: ; %bb.0: ; %main_body
1193 ; PREGFX10-NEXT: buffer_load_dword v1, off, s[0:3], 0
1194 ; PREGFX10-NEXT: s_mov_b32 m0, -1
1195 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
1196 ; PREGFX10-NEXT: ds_write_b32 v0, v1
1197 ; PREGFX10-NEXT: s_endpgm
1198 ;
1199 ; GFX10-LABEL: raw_buffer_load_v2i16:
1200 ; GFX10: ; %bb.0: ; %main_body
1201 ; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], 0
1202 ; GFX10-NEXT: s_waitcnt vmcnt(0)
1203 ; GFX10-NEXT: ds_write_b32 v0, v1
1204 ; GFX10-NEXT: s_endpgm
1205 ;
1206 ; GFX11-LABEL: raw_buffer_load_v2i16:
1207 ; GFX11: ; %bb.0: ; %main_body
1208 ; GFX11-NEXT: buffer_load_b32 v1, off, s[0:3], 0
1209 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1210 ; GFX11-NEXT: ds_store_b32 v0, v1
1211 ; GFX11-NEXT: s_endpgm
1212 ;
1213 ; GFX12-LABEL: raw_buffer_load_v2i16:
1214 ; GFX12: ; %bb.0: ; %main_body
1215 ; GFX12-NEXT: buffer_load_b32 v1, off, s[0:3], null
1216 ; GFX12-NEXT: s_wait_loadcnt 0x0
1217 ; GFX12-NEXT: ds_store_b32 v0, v1
1218 ; GFX12-NEXT: s_endpgm
1219 main_body:
1220 %val = call <2 x i16> @llvm.amdgcn.raw.buffer.load.v2i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
1221 store <2 x i16> %val, ptr addrspace(3) %ptr
1222 ret void
1223 }
1225 define amdgpu_ps void @raw_buffer_load_v4i16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr) {
1226 ; PREGFX10-LABEL: raw_buffer_load_v4i16:
1227 ; PREGFX10: ; %bb.0: ; %main_body
1228 ; PREGFX10-NEXT: buffer_load_dwordx2 v[1:2], off, s[0:3], 0
1229 ; PREGFX10-NEXT: s_mov_b32 m0, -1
1230 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
1231 ; PREGFX10-NEXT: ds_write_b64 v0, v[1:2]
1232 ; PREGFX10-NEXT: s_endpgm
1233 ;
1234 ; GFX10-LABEL: raw_buffer_load_v4i16:
1235 ; GFX10: ; %bb.0: ; %main_body
1236 ; GFX10-NEXT: buffer_load_dwordx2 v[1:2], off, s[0:3], 0
1237 ; GFX10-NEXT: s_waitcnt vmcnt(0)
1238 ; GFX10-NEXT: ds_write_b64 v0, v[1:2]
1239 ; GFX10-NEXT: s_endpgm
1240 ;
1241 ; GFX11-LABEL: raw_buffer_load_v4i16:
1242 ; GFX11: ; %bb.0: ; %main_body
1243 ; GFX11-NEXT: buffer_load_b64 v[1:2], off, s[0:3], 0
1244 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1245 ; GFX11-NEXT: ds_store_b64 v0, v[1:2]
1246 ; GFX11-NEXT: s_endpgm
1247 ;
1248 ; GFX12-LABEL: raw_buffer_load_v4i16:
1249 ; GFX12: ; %bb.0: ; %main_body
1250 ; GFX12-NEXT: buffer_load_b64 v[1:2], off, s[0:3], null
1251 ; GFX12-NEXT: s_wait_loadcnt 0x0
1252 ; GFX12-NEXT: ds_store_b64 v0, v[1:2]
1253 ; GFX12-NEXT: s_endpgm
1254 main_body:
1255 %val = call <4 x i16> @llvm.amdgcn.raw.buffer.load.v4i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
1256 store <4 x i16> %val, ptr addrspace(3) %ptr
1257 ret void
1258 }
1260 define amdgpu_ps void @raw_buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) {
1261 ; PREGFX10-LABEL: raw_buffer_load_x1_offset_merged:
1262 ; PREGFX10: ; %bb.0: ; %main_body
1263 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
1264 ; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28
1265 ; PREGFX10-NEXT: s_waitcnt vmcnt(1)
1266 ; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
1267 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
1268 ; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
1269 ; PREGFX10-NEXT: s_endpgm
1270 ;
1271 ; GFX10-LABEL: raw_buffer_load_x1_offset_merged:
1272 ; GFX10: ; %bb.0: ; %main_body
1273 ; GFX10-NEXT: s_clause 0x1
1274 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
1275 ; GFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28
1276 ; GFX10-NEXT: s_waitcnt vmcnt(1)
1277 ; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
1278 ; GFX10-NEXT: s_waitcnt vmcnt(0)
1279 ; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
1280 ; GFX10-NEXT: s_endpgm
1281 ;
1282 ; GFX11-LABEL: raw_buffer_load_x1_offset_merged:
1283 ; GFX11: ; %bb.0: ; %main_body
1284 ; GFX11-NEXT: s_clause 0x1
1285 ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4
1286 ; GFX11-NEXT: buffer_load_b64 v[4:5], off, s[0:3], 0 offset:28
1287 ; GFX11-NEXT: s_waitcnt vmcnt(1)
1288 ; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done
1289 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1290 ; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done
1291 ; GFX11-NEXT: s_endpgm
1292 ;
1293 ; GFX12-LABEL: raw_buffer_load_x1_offset_merged:
1294 ; GFX12: ; %bb.0: ; %main_body
1295 ; GFX12-NEXT: s_clause 0x1
1296 ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null offset:4
1297 ; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[0:3], null offset:28
1298 ; GFX12-NEXT: s_wait_loadcnt 0x1
1299 ; GFX12-NEXT: export mrt0 v0, v1, v2, v3 done
1300 ; GFX12-NEXT: s_wait_loadcnt 0x0
1301 ; GFX12-NEXT: export mrt0 v4, v5, v0, v0 done
1302 ; GFX12-NEXT: s_endpgm
1303 main_body:
1304 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0)
1305 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 0)
1306 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 12, i32 0, i32 0)
1307 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 16, i32 0, i32 0)
1308 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 0)
1309 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 0)
1310 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
1311 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
1312 ret void
1313 }
1315 define amdgpu_ps void @raw_buffer_load_x1_offset_swizzled_not_merged_pregfx12(<4 x i32> inreg %rsrc) {
1316 ; PREGFX10-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged_pregfx12:
1317 ; PREGFX10: ; %bb.0: ; %main_body
1318 ; PREGFX10-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:4
1319 ; PREGFX10-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:8
1320 ; PREGFX10-NEXT: buffer_load_dword v2, off, s[0:3], 0 offset:12
1321 ; PREGFX10-NEXT: buffer_load_dword v3, off, s[0:3], 0 offset:16
1322 ; PREGFX10-NEXT: buffer_load_dword v4, off, s[0:3], 0 offset:28
1323 ; PREGFX10-NEXT: buffer_load_dword v5, off, s[0:3], 0 offset:32
1324 ; PREGFX10-NEXT: s_waitcnt vmcnt(2)
1325 ; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
1326 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
1327 ; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
1328 ; PREGFX10-NEXT: s_endpgm
1329 ;
1330 ; GFX10-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged_pregfx12:
1331 ; GFX10: ; %bb.0: ; %main_body
1332 ; GFX10-NEXT: s_clause 0x5
1333 ; GFX10-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:4
1334 ; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:8
1335 ; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], 0 offset:12
1336 ; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], 0 offset:16
1337 ; GFX10-NEXT: buffer_load_dword v4, off, s[0:3], 0 offset:28
1338 ; GFX10-NEXT: buffer_load_dword v5, off, s[0:3], 0 offset:32
1339 ; GFX10-NEXT: s_waitcnt vmcnt(2)
1340 ; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
1341 ; GFX10-NEXT: s_waitcnt vmcnt(0)
1342 ; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
1343 ; GFX10-NEXT: s_endpgm
1344 ;
1345 ; GFX11-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged_pregfx12:
1346 ; GFX11: ; %bb.0: ; %main_body
1347 ; GFX11-NEXT: s_clause 0x5
1348 ; GFX11-NEXT: buffer_load_b32 v0, off, s[0:3], 0 offset:4
1349 ; GFX11-NEXT: buffer_load_b32 v1, off, s[0:3], 0 offset:8
1350 ; GFX11-NEXT: buffer_load_b32 v2, off, s[0:3], 0 offset:12
1351 ; GFX11-NEXT: buffer_load_b32 v3, off, s[0:3], 0 offset:16
1352 ; GFX11-NEXT: buffer_load_b32 v4, off, s[0:3], 0 offset:28
1353 ; GFX11-NEXT: buffer_load_b32 v5, off, s[0:3], 0 offset:32
1354 ; GFX11-NEXT: s_waitcnt vmcnt(2)
1355 ; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done
1356 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1357 ; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done
1358 ; GFX11-NEXT: s_endpgm
1359 ;
1360 ; GFX12-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged_pregfx12:
1361 ; GFX12: ; %bb.0: ; %main_body
1362 ; GFX12-NEXT: s_clause 0x1
1363 ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null offset:4 scope:SCOPE_SE
1364 ; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[0:3], null offset:28 scope:SCOPE_SE
1365 ; GFX12-NEXT: s_wait_loadcnt 0x1
1366 ; GFX12-NEXT: export mrt0 v0, v1, v2, v3 done
1367 ; GFX12-NEXT: s_wait_loadcnt 0x0
1368 ; GFX12-NEXT: export mrt0 v4, v5, v0, v0 done
1369 ; GFX12-NEXT: s_endpgm
1370 main_body:
1371 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 8)
1372 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 8)
1373 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 12, i32 0, i32 8)
1374 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 16, i32 0, i32 8)
1375 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 8)
1376 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 8)
1377 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
1378 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
1379 ret void
1380 }
1382 define amdgpu_ps void @raw_buffer_load_x1_offset_swizzled_not_merged(<4 x i32> inreg %rsrc) {
1383 ; PREGFX10-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged:
1384 ; PREGFX10: ; %bb.0: ; %main_body
1385 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
1386 ; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28
1387 ; PREGFX10-NEXT: s_waitcnt vmcnt(1)
1388 ; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
1389 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
1390 ; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
1391 ; PREGFX10-NEXT: s_endpgm
1392 ;
1393 ; GFX10-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged:
1394 ; GFX10: ; %bb.0: ; %main_body
1395 ; GFX10-NEXT: s_clause 0x1
1396 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
1397 ; GFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28
1398 ; GFX10-NEXT: s_waitcnt vmcnt(1)
1399 ; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
1400 ; GFX10-NEXT: s_waitcnt vmcnt(0)
1401 ; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
1402 ; GFX10-NEXT: s_endpgm
1403 ;
1404 ; GFX11-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged:
1405 ; GFX11: ; %bb.0: ; %main_body
1406 ; GFX11-NEXT: s_clause 0x1
1407 ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4
1408 ; GFX11-NEXT: buffer_load_b64 v[4:5], off, s[0:3], 0 offset:28
1409 ; GFX11-NEXT: s_waitcnt vmcnt(1)
1410 ; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done
1411 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1412 ; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done
1413 ; GFX11-NEXT: s_endpgm
1414 ;
1415 ; GFX12-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged:
1416 ; GFX12: ; %bb.0: ; %main_body
1417 ; GFX12-NEXT: s_clause 0x5
1418 ; GFX12-NEXT: buffer_load_b32 v0, off, s[0:3], null offset:4
1419 ; GFX12-NEXT: buffer_load_b32 v1, off, s[0:3], null offset:8
1420 ; GFX12-NEXT: buffer_load_b32 v2, off, s[0:3], null offset:12
1421 ; GFX12-NEXT: buffer_load_b32 v3, off, s[0:3], null offset:16
1422 ; GFX12-NEXT: buffer_load_b32 v4, off, s[0:3], null offset:28
1423 ; GFX12-NEXT: buffer_load_b32 v5, off, s[0:3], null offset:32
1424 ; GFX12-NEXT: s_wait_loadcnt 0x2
1425 ; GFX12-NEXT: export mrt0 v0, v1, v2, v3 done
1426 ; GFX12-NEXT: s_wait_loadcnt 0x0
1427 ; GFX12-NEXT: export mrt0 v4, v5, v0, v0 done
1428 ; GFX12-NEXT: s_endpgm
1429 main_body:
1430 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 64)
1431 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 64)
1432 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 12, i32 0, i32 64)
1433 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 16, i32 0, i32 64)
1434 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 64)
1435 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 64)
1436 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
1437 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
1438 ret void
1439 }
1441 declare float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32>, i32, i32, i32) #0
1442 declare <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32>, i32, i32, i32) #0
1443 declare <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32>, i32, i32, i32) #0
1444 declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32) #0
1445 declare <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32>, i32, i32, i32) #0
1446 declare <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32>, i32, i32, i32) #0
1447 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
1448 declare i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32>, i32, i32, i32) #0
1449 declare i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32>, i32, i32, i32) #0
1450 declare <2 x i16> @llvm.amdgcn.raw.buffer.load.v2i16(<4 x i32>, i32, i32, i32) #0
1451 declare <4 x i16> @llvm.amdgcn.raw.buffer.load.v4i16(<4 x i32>, i32, i32, i32) #0
1452 declare half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32>, i32, i32, i32) #0
1453 declare <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32>, i32, i32, i32) #0
1454 declare <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32>, i32, i32, i32) #0
1455 attributes #0 = { nounwind readonly }