[llvm-project.git] / llvm / test / CodeGen / AMDGPU / llvm.amdgcn.struct.buffer.load.format.v3f16.ll
| blob | 0522d5258b9b5fe4fa10ff2aa01eb9f975be036e |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mcpu=gfx1010 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
3 ; RUN: llc -mcpu=gfx900 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
4 ; RUN: llc -mcpu=gfx810 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
5 ; RUN: llc -mcpu=gfx1100 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s
6 ; RUN: llc -mcpu=gfx1200 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s
8 @esgs_ring = external addrspace(3) global [0 x i32], align 65536
10 define amdgpu_gs void @main(<4 x i32> %arg, i32 %arg1) {
11 ; GFX10-LABEL: main:
12 ; GFX10: ; %bb.0: ; %bb
13 ; GFX10-NEXT: s_mov_b32 s1, exec_lo
14 ; GFX10-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
15 ; GFX10-NEXT: v_readfirstlane_b32 s4, v0
16 ; GFX10-NEXT: v_readfirstlane_b32 s5, v1
17 ; GFX10-NEXT: v_readfirstlane_b32 s6, v2
18 ; GFX10-NEXT: v_readfirstlane_b32 s7, v3
19 ; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
20 ; GFX10-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
21 ; GFX10-NEXT: s_and_b32 s0, vcc_lo, s0
22 ; GFX10-NEXT: s_and_saveexec_b32 s0, s0
23 ; GFX10-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen
24 ; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
25 ; GFX10-NEXT: ; implicit-def: $vgpr4
26 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
27 ; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s0
28 ; GFX10-NEXT: s_cbranch_execnz .LBB0_1
29 ; GFX10-NEXT: ; %bb.2:
30 ; GFX10-NEXT: s_mov_b32 exec_lo, s1
31 ; GFX10-NEXT: s_waitcnt vmcnt(0)
32 ; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v5
33 ; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v6
34 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
35 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
36 ; GFX10-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8
37 ;
38 ; GFX9-LABEL: main:
39 ; GFX9: ; %bb.0: ; %bb
40 ; GFX9-NEXT: s_mov_b64 s[2:3], exec
41 ; GFX9-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
42 ; GFX9-NEXT: v_readfirstlane_b32 s4, v0
43 ; GFX9-NEXT: v_readfirstlane_b32 s5, v1
44 ; GFX9-NEXT: v_readfirstlane_b32 s6, v2
45 ; GFX9-NEXT: v_readfirstlane_b32 s7, v3
46 ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1]
47 ; GFX9-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], v[2:3]
48 ; GFX9-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
49 ; GFX9-NEXT: s_and_saveexec_b64 s[0:1], s[0:1]
50 ; GFX9-NEXT: s_nop 0
51 ; GFX9-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen
52 ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
53 ; GFX9-NEXT: ; implicit-def: $vgpr4
54 ; GFX9-NEXT: s_xor_b64 exec, exec, s[0:1]
55 ; GFX9-NEXT: s_cbranch_execnz .LBB0_1
56 ; GFX9-NEXT: ; %bb.2:
57 ; GFX9-NEXT: s_mov_b64 exec, s[2:3]
58 ; GFX9-NEXT: s_waitcnt vmcnt(0)
59 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v5
60 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v6
61 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
62 ; GFX9-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8
63 ;
64 ; GFX8-LABEL: main:
65 ; GFX8: ; %bb.0: ; %bb
66 ; GFX8-NEXT: s_mov_b64 s[2:3], exec
67 ; GFX8-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
68 ; GFX8-NEXT: v_readfirstlane_b32 s4, v0
69 ; GFX8-NEXT: v_readfirstlane_b32 s5, v1
70 ; GFX8-NEXT: v_readfirstlane_b32 s6, v2
71 ; GFX8-NEXT: v_readfirstlane_b32 s7, v3
72 ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1]
73 ; GFX8-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], v[2:3]
74 ; GFX8-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
75 ; GFX8-NEXT: s_and_saveexec_b64 s[0:1], s[0:1]
76 ; GFX8-NEXT: s_nop 0
77 ; GFX8-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen
78 ; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
79 ; GFX8-NEXT: ; implicit-def: $vgpr4
80 ; GFX8-NEXT: s_xor_b64 exec, exec, s[0:1]
81 ; GFX8-NEXT: s_cbranch_execnz .LBB0_1
82 ; GFX8-NEXT: ; %bb.2:
83 ; GFX8-NEXT: s_mov_b64 exec, s[2:3]
84 ; GFX8-NEXT: s_waitcnt vmcnt(0)
85 ; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v5
86 ; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v6
87 ; GFX8-NEXT: v_mov_b32_e32 v2, 0
88 ; GFX8-NEXT: s_mov_b32 m0, -1
89 ; GFX8-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8
90 ;
91 ; GFX11-LABEL: main:
92 ; GFX11: ; %bb.0: ; %bb
93 ; GFX11-NEXT: s_mov_b32 s1, exec_lo
94 ; GFX11-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
95 ; GFX11-NEXT: v_readfirstlane_b32 s4, v0
96 ; GFX11-NEXT: v_readfirstlane_b32 s5, v1
97 ; GFX11-NEXT: v_readfirstlane_b32 s6, v2
98 ; GFX11-NEXT: v_readfirstlane_b32 s7, v3
99 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
100 ; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
101 ; GFX11-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
102 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
103 ; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
104 ; GFX11-NEXT: s_and_saveexec_b32 s0, s0
105 ; GFX11-NEXT: buffer_load_d16_format_xyz v[5:6], v4, s[4:7], 0 idxen
106 ; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
107 ; GFX11-NEXT: ; implicit-def: $vgpr4
108 ; GFX11-NEXT: s_xor_b32 exec_lo, exec_lo, s0
109 ; GFX11-NEXT: s_cbranch_execnz .LBB0_1
110 ; GFX11-NEXT: ; %bb.2:
111 ; GFX11-NEXT: s_mov_b32 exec_lo, s1
112 ; GFX11-NEXT: s_waitcnt vmcnt(0)
113 ; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v5
114 ; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
115 ; GFX11-NEXT: ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
116 ;
117 ; GFX12-LABEL: main:
118 ; GFX12: ; %bb.0: ; %bb
119 ; GFX12-NEXT: s_mov_b32 s1, exec_lo
120 ; GFX12-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
121 ; GFX12-NEXT: v_readfirstlane_b32 s4, v0
122 ; GFX12-NEXT: v_readfirstlane_b32 s5, v1
123 ; GFX12-NEXT: v_readfirstlane_b32 s6, v2
124 ; GFX12-NEXT: v_readfirstlane_b32 s7, v3
125 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
126 ; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
127 ; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
128 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
129 ; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
130 ; GFX12-NEXT: s_and_saveexec_b32 s0, s0
131 ; GFX12-NEXT: s_wait_loadcnt 0x0
132 ; GFX12-NEXT: buffer_load_d16_format_xyz v[5:6], v4, s[4:7], null idxen
133 ; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
134 ; GFX12-NEXT: ; implicit-def: $vgpr4
135 ; GFX12-NEXT: s_xor_b32 exec_lo, exec_lo, s0
136 ; GFX12-NEXT: s_cbranch_execnz .LBB0_1
137 ; GFX12-NEXT: ; %bb.2:
138 ; GFX12-NEXT: s_mov_b32 exec_lo, s1
139 ; GFX12-NEXT: s_wait_loadcnt 0x0
140 ; GFX12-NEXT: v_lshrrev_b32_e32 v0, 16, v5
141 ; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
142 ; GFX12-NEXT: ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
143 bb:
144 %i = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 undef)
145 %i2 = call nsz arcp <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32> %arg, i32 %arg1, i32 0, i32 0, i32 0)
146 %i3 = bitcast <3 x half> %i2 to <3 x i16>
147 %i4 = extractelement <3 x i16> %i3, i32 1
148 %i5 = bitcast <3 x half> %i2 to <3 x i16>
149 %i6 = extractelement <3 x i16> %i5, i32 2
150 %i7 = zext i16 %i4 to i32
151 %i8 = zext i16 %i6 to i32
152 %i9 = add nuw nsw i32 0, 7
153 %i10 = getelementptr [0 x i32], ptr addrspace(3) @esgs_ring, i32 0, i32 %i9
154 store i32 %i7, ptr addrspace(3) %i10, align 4
155 %i11 = add nuw nsw i32 0, 8
156 %i12 = getelementptr [0 x i32], ptr addrspace(3) @esgs_ring, i32 0, i32 %i11
157 store i32 %i8, ptr addrspace(3) %i12, align 4
158 unreachable
159 }
160 ; Function Attrs: nounwind readnone willreturn
161 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0
162 ; Function Attrs: nounwind readonly willreturn
163 declare <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32>, i32, i32, i32, i32 immarg) #1
164 attributes #0 = { nounwind readnone willreturn }
165 attributes #1 = { nounwind readonly willreturn }