| blob | 6b57f20f25e2ce5adb86bc65272563b7c6fdfcaf |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
3 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s
4 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
5 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
7 declare half @llvm.ceil.f16(half %a)
8 declare <2 x half> @llvm.ceil.v2f16(<2 x half> %a)
10 define amdgpu_kernel void @ceil_f16(
11 ; SI-LABEL: ceil_f16:
12 ; SI: ; %bb.0: ; %entry
13 ; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
14 ; SI-NEXT: s_mov_b32 s7, 0xf000
15 ; SI-NEXT: s_mov_b32 s6, -1
16 ; SI-NEXT: s_mov_b32 s10, s6
17 ; SI-NEXT: s_mov_b32 s11, s7
18 ; SI-NEXT: s_waitcnt lgkmcnt(0)
19 ; SI-NEXT: s_mov_b32 s8, s2
20 ; SI-NEXT: s_mov_b32 s9, s3
21 ; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
22 ; SI-NEXT: s_mov_b32 s4, s0
23 ; SI-NEXT: s_mov_b32 s5, s1
24 ; SI-NEXT: s_waitcnt vmcnt(0)
25 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
26 ; SI-NEXT: v_ceil_f32_e32 v0, v0
27 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
28 ; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
29 ; SI-NEXT: s_endpgm
30 ;
31 ; VI-LABEL: ceil_f16:
32 ; VI: ; %bb.0: ; %entry
33 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
34 ; VI-NEXT: s_mov_b32 s7, 0xf000
35 ; VI-NEXT: s_mov_b32 s6, -1
36 ; VI-NEXT: s_mov_b32 s10, s6
37 ; VI-NEXT: s_mov_b32 s11, s7
38 ; VI-NEXT: s_waitcnt lgkmcnt(0)
39 ; VI-NEXT: s_mov_b32 s8, s2
40 ; VI-NEXT: s_mov_b32 s9, s3
41 ; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
42 ; VI-NEXT: s_mov_b32 s4, s0
43 ; VI-NEXT: s_mov_b32 s5, s1
44 ; VI-NEXT: s_waitcnt vmcnt(0)
45 ; VI-NEXT: v_ceil_f16_e32 v0, v0
46 ; VI-NEXT: buffer_store_short v0, off, s[4:7], 0
47 ; VI-NEXT: s_endpgm
48 ;
49 ; GFX11-LABEL: ceil_f16:
50 ; GFX11: ; %bb.0: ; %entry
51 ; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
52 ; GFX11-NEXT: s_mov_b32 s6, -1
53 ; GFX11-NEXT: s_mov_b32 s7, 0x31016000
54 ; GFX11-NEXT: s_mov_b32 s10, s6
55 ; GFX11-NEXT: s_mov_b32 s11, s7
56 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
57 ; GFX11-NEXT: s_mov_b32 s8, s2
58 ; GFX11-NEXT: s_mov_b32 s9, s3
59 ; GFX11-NEXT: s_mov_b32 s4, s0
60 ; GFX11-NEXT: buffer_load_u16 v0, off, s[8:11], 0
61 ; GFX11-NEXT: s_mov_b32 s5, s1
62 ; GFX11-NEXT: s_waitcnt vmcnt(0)
63 ; GFX11-NEXT: v_ceil_f16_e32 v0.l, v0.l
64 ; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0
65 ; GFX11-NEXT: s_endpgm
66 ;
67 ; GFX11-FAKE16-LABEL: ceil_f16:
68 ; GFX11-FAKE16: ; %bb.0: ; %entry
69 ; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
70 ; GFX11-FAKE16-NEXT: s_mov_b32 s6, -1
71 ; GFX11-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
72 ; GFX11-FAKE16-NEXT: s_mov_b32 s10, s6
73 ; GFX11-FAKE16-NEXT: s_mov_b32 s11, s7
74 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
75 ; GFX11-FAKE16-NEXT: s_mov_b32 s8, s2
76 ; GFX11-FAKE16-NEXT: s_mov_b32 s9, s3
77 ; GFX11-FAKE16-NEXT: s_mov_b32 s4, s0
78 ; GFX11-FAKE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0
79 ; GFX11-FAKE16-NEXT: s_mov_b32 s5, s1
80 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
81 ; GFX11-FAKE16-NEXT: v_ceil_f16_e32 v0, v0
82 ; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0
83 ; GFX11-FAKE16-NEXT: s_endpgm
84 ptr addrspace(1) %r,
85 ptr addrspace(1) %a) {
86 entry:
87 %a.val = load half, ptr addrspace(1) %a
88 %r.val = call half @llvm.ceil.f16(half %a.val)
89 store half %r.val, ptr addrspace(1) %r
90 ret void
91 }
93 ; The original test with manual checks also had these NOT directives:
94 ; COM: SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
95 ; COM: SI-NOT: and
96 ; COM: SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
97 ; COM: VI-DAG: v_ceil_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
98 ; COM: VI-NOT: and
99 ; COM: VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]]
100 define amdgpu_kernel void @ceil_v2f16(
101 ; SI-LABEL: ceil_v2f16:
102 ; SI: ; %bb.0: ; %entry
103 ; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
104 ; SI-NEXT: s_mov_b32 s7, 0xf000
105 ; SI-NEXT: s_mov_b32 s6, -1
106 ; SI-NEXT: s_mov_b32 s10, s6
107 ; SI-NEXT: s_mov_b32 s11, s7
108 ; SI-NEXT: s_waitcnt lgkmcnt(0)
109 ; SI-NEXT: s_mov_b32 s8, s2
110 ; SI-NEXT: s_mov_b32 s9, s3
111 ; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
112 ; SI-NEXT: s_mov_b32 s4, s0
113 ; SI-NEXT: s_mov_b32 s5, s1
114 ; SI-NEXT: s_waitcnt vmcnt(0)
115 ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
116 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
117 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
118 ; SI-NEXT: v_ceil_f32_e32 v1, v1
119 ; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
120 ; SI-NEXT: v_ceil_f32_e32 v0, v0
121 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
122 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
123 ; SI-NEXT: v_or_b32_e32 v0, v0, v1
124 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
125 ; SI-NEXT: s_endpgm
126 ;
127 ; VI-LABEL: ceil_v2f16:
128 ; VI: ; %bb.0: ; %entry
129 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
130 ; VI-NEXT: s_mov_b32 s7, 0xf000
131 ; VI-NEXT: s_mov_b32 s6, -1
132 ; VI-NEXT: s_mov_b32 s10, s6
133 ; VI-NEXT: s_mov_b32 s11, s7
134 ; VI-NEXT: s_waitcnt lgkmcnt(0)
135 ; VI-NEXT: s_mov_b32 s8, s2
136 ; VI-NEXT: s_mov_b32 s9, s3
137 ; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0
138 ; VI-NEXT: s_mov_b32 s4, s0
139 ; VI-NEXT: s_mov_b32 s5, s1
140 ; VI-NEXT: s_waitcnt vmcnt(0)
141 ; VI-NEXT: v_ceil_f16_sdwa v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
142 ; VI-NEXT: v_ceil_f16_e32 v0, v0
143 ; VI-NEXT: v_or_b32_e32 v0, v0, v1
144 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
145 ; VI-NEXT: s_endpgm
146 ;
147 ; GFX11-LABEL: ceil_v2f16:
148 ; GFX11: ; %bb.0: ; %entry
149 ; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
150 ; GFX11-NEXT: s_mov_b32 s6, -1
151 ; GFX11-NEXT: s_mov_b32 s7, 0x31016000
152 ; GFX11-NEXT: s_mov_b32 s10, s6
153 ; GFX11-NEXT: s_mov_b32 s11, s7
154 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
155 ; GFX11-NEXT: s_mov_b32 s8, s2
156 ; GFX11-NEXT: s_mov_b32 s9, s3
157 ; GFX11-NEXT: s_mov_b32 s4, s0
158 ; GFX11-NEXT: buffer_load_b32 v0, off, s[8:11], 0
159 ; GFX11-NEXT: s_mov_b32 s5, s1
160 ; GFX11-NEXT: s_waitcnt vmcnt(0)
161 ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
162 ; GFX11-NEXT: v_ceil_f16_e32 v0.l, v0.l
163 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
164 ; GFX11-NEXT: v_ceil_f16_e32 v0.h, v1.l
165 ; GFX11-NEXT: v_mov_b16_e32 v1.l, v0.l
166 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
167 ; GFX11-NEXT: v_mov_b16_e32 v0.l, v0.h
168 ; GFX11-NEXT: v_pack_b32_f16 v0, v1, v0
169 ; GFX11-NEXT: buffer_store_b32 v0, off, s[4:7], 0
170 ; GFX11-NEXT: s_endpgm
171 ;
172 ; GFX11-FAKE16-LABEL: ceil_v2f16:
173 ; GFX11-FAKE16: ; %bb.0: ; %entry
174 ; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
175 ; GFX11-FAKE16-NEXT: s_mov_b32 s6, -1
176 ; GFX11-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
177 ; GFX11-FAKE16-NEXT: s_mov_b32 s10, s6
178 ; GFX11-FAKE16-NEXT: s_mov_b32 s11, s7
179 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
180 ; GFX11-FAKE16-NEXT: s_mov_b32 s8, s2
181 ; GFX11-FAKE16-NEXT: s_mov_b32 s9, s3
182 ; GFX11-FAKE16-NEXT: s_mov_b32 s4, s0
183 ; GFX11-FAKE16-NEXT: buffer_load_b32 v0, off, s[8:11], 0
184 ; GFX11-FAKE16-NEXT: s_mov_b32 s5, s1
185 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
186 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
187 ; GFX11-FAKE16-NEXT: v_ceil_f16_e32 v0, v0
188 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
189 ; GFX11-FAKE16-NEXT: v_ceil_f16_e32 v1, v1
190 ; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
191 ; GFX11-FAKE16-NEXT: buffer_store_b32 v0, off, s[4:7], 0
192 ; GFX11-FAKE16-NEXT: s_endpgm
193 ptr addrspace(1) %r,
194 ptr addrspace(1) %a) {
195 entry:
196 %a.val = load <2 x half>, ptr addrspace(1) %a
197 %r.val = call <2 x half> @llvm.ceil.v2f16(<2 x half> %a.val)
198 store <2 x half> %r.val, ptr addrspace(1) %r
199 ret void
200 }